mb8795.c revision 1.6 1 1.6 dbj /* $NetBSD: mb8795.c,v 1.6 1998/07/11 07:06:16 dbj Exp $ */
2 1.1 dbj /*
3 1.1 dbj * Copyright (c) 1998 Darrin B. Jewell
4 1.1 dbj * All rights reserved.
5 1.1 dbj *
6 1.1 dbj * Redistribution and use in source and binary forms, with or without
7 1.1 dbj * modification, are permitted provided that the following conditions
8 1.1 dbj * are met:
9 1.1 dbj * 1. Redistributions of source code must retain the above copyright
10 1.1 dbj * notice, this list of conditions and the following disclaimer.
11 1.1 dbj * 2. Redistributions in binary form must reproduce the above copyright
12 1.1 dbj * notice, this list of conditions and the following disclaimer in the
13 1.1 dbj * documentation and/or other materials provided with the distribution.
14 1.1 dbj * 3. All advertising materials mentioning features or use of this software
15 1.1 dbj * must display the following acknowledgement:
16 1.1 dbj * This product includes software developed by Darrin B. Jewell
17 1.1 dbj * 4. The name of the author may not be used to endorse or promote products
18 1.1 dbj * derived from this software without specific prior written permission
19 1.1 dbj *
20 1.1 dbj * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 1.1 dbj * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 1.1 dbj * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 1.1 dbj * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 1.1 dbj * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 1.1 dbj * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 1.1 dbj * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 1.1 dbj * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 1.1 dbj * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 1.1 dbj * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 1.1 dbj */
31 1.1 dbj
32 1.2 jonathan #include "opt_inet.h"
33 1.3 jonathan #include "opt_ccitt.h"
34 1.4 jonathan #include "opt_llc.h"
35 1.5 jonathan #include "opt_ns.h"
36 1.1 dbj #include "bpfilter.h"
37 1.1 dbj #include "rnd.h"
38 1.1 dbj
39 1.1 dbj #include <sys/param.h>
40 1.1 dbj #include <sys/systm.h>
41 1.1 dbj #include <sys/mbuf.h>
42 1.1 dbj #include <sys/syslog.h>
43 1.1 dbj #include <sys/socket.h>
44 1.1 dbj #include <sys/device.h>
45 1.1 dbj #include <sys/malloc.h>
46 1.1 dbj #include <sys/ioctl.h>
47 1.1 dbj #include <sys/errno.h>
48 1.1 dbj #if NRND > 0
49 1.1 dbj #include <sys/rnd.h>
50 1.1 dbj #endif
51 1.1 dbj
52 1.1 dbj #include <net/if.h>
53 1.1 dbj #include <net/if_dl.h>
54 1.1 dbj #include <net/if_ether.h>
55 1.1 dbj
56 1.1 dbj #if 0
57 1.1 dbj #include <net/if_media.h>
58 1.1 dbj #endif
59 1.1 dbj
60 1.1 dbj #ifdef INET
61 1.1 dbj #include <netinet/in.h>
62 1.1 dbj #include <netinet/if_inarp.h>
63 1.1 dbj #include <netinet/in_systm.h>
64 1.1 dbj #include <netinet/in_var.h>
65 1.1 dbj #include <netinet/ip.h>
66 1.1 dbj #endif
67 1.1 dbj
68 1.1 dbj #ifdef NS
69 1.1 dbj #include <netns/ns.h>
70 1.1 dbj #include <netns/ns_if.h>
71 1.1 dbj #endif
72 1.1 dbj
73 1.1 dbj #if defined(CCITT) && defined(LLC)
74 1.1 dbj #include <sys/socketvar.h>
75 1.1 dbj #include <netccitt/x25.h>
76 1.1 dbj #include <netccitt/pk.h>
77 1.1 dbj #include <netccitt/pk_var.h>
78 1.1 dbj #include <netccitt/pk_extern.h>
79 1.1 dbj #endif
80 1.1 dbj
81 1.1 dbj #if NBPFILTER > 0
82 1.1 dbj #include <net/bpf.h>
83 1.1 dbj #include <net/bpfdesc.h>
84 1.1 dbj #endif
85 1.1 dbj
86 1.1 dbj #include <machine/cpu.h>
87 1.1 dbj #include <machine/bus.h>
88 1.1 dbj #include <machine/intr.h>
89 1.1 dbj
90 1.1 dbj /* @@@ this is here for the REALIGN_DMABUF hack below */
91 1.1 dbj #include "nextdmareg.h"
92 1.1 dbj #include "nextdmavar.h"
93 1.1 dbj
94 1.1 dbj #include "mb8795reg.h"
95 1.1 dbj #include "mb8795var.h"
96 1.1 dbj
97 1.1 dbj #if 0
98 1.1 dbj #define XE_DEBUG
99 1.1 dbj #endif
100 1.1 dbj
101 1.1 dbj #ifdef XE_DEBUG
102 1.1 dbj #define DPRINTF(x) printf x;
103 1.1 dbj #else
104 1.1 dbj #define DPRINTF(x)
105 1.1 dbj #endif
106 1.1 dbj
107 1.1 dbj
108 1.1 dbj /*
109 1.1 dbj * Support for
110 1.1 dbj * Fujitsu Ethernet Data Link Controller (MB8795)
111 1.1 dbj * and the Fujitsu Manchester Encoder/Decoder (MB502).
112 1.1 dbj */
113 1.1 dbj
114 1.1 dbj int debugipkt = 0;
115 1.1 dbj
116 1.1 dbj
117 1.1 dbj void mb8795_shutdown __P((void *));
118 1.1 dbj
119 1.1 dbj #if 0
120 1.1 dbj int mb8795_mediachange __P((struct ifnet *));
121 1.1 dbj void mb8795_mediastatus __P((struct ifnet *, struct ifmediareq *));
122 1.1 dbj #endif
123 1.1 dbj
124 1.1 dbj struct mbuf * mb8795_rxdmamap_load __P((struct mb8795_softc *,
125 1.1 dbj bus_dmamap_t map));
126 1.1 dbj
127 1.1 dbj bus_dmamap_t mb8795_rxdma_continue __P((void *));
128 1.1 dbj void mb8795_rxdma_completed __P((bus_dmamap_t,void *));
129 1.1 dbj bus_dmamap_t mb8795_txdma_continue __P((void *));
130 1.1 dbj void mb8795_txdma_completed __P((bus_dmamap_t,void *));
131 1.1 dbj void mb8795_rxdma_shutdown __P((void *));
132 1.1 dbj void mb8795_txdma_shutdown __P((void *));
133 1.1 dbj bus_dmamap_t mb8795_txdma_restart __P((bus_dmamap_t,void *));
134 1.1 dbj
135 1.1 dbj void
136 1.1 dbj mb8795_config(sc)
137 1.1 dbj struct mb8795_softc *sc;
138 1.1 dbj {
139 1.1 dbj struct ifnet *ifp = &sc->sc_ethercom.ec_if;
140 1.1 dbj
141 1.1 dbj DPRINTF(("%s: mb8795_config()\n",sc->sc_dev.dv_xname));
142 1.1 dbj
143 1.1 dbj /* Initialize ifnet structure. */
144 1.1 dbj bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
145 1.1 dbj ifp->if_softc = sc;
146 1.1 dbj ifp->if_start = mb8795_start;
147 1.1 dbj ifp->if_ioctl = mb8795_ioctl;
148 1.1 dbj ifp->if_watchdog = mb8795_watchdog;
149 1.1 dbj ifp->if_flags =
150 1.1 dbj IFF_BROADCAST | IFF_NOTRAILERS;
151 1.1 dbj
152 1.1 dbj #if 0
153 1.1 dbj /* Initialize ifmedia structures. */
154 1.1 dbj ifmedia_init(&sc->sc_media, 0, mb8795_mediachange, mb8795_mediastatus);
155 1.1 dbj if (sc->sc_supmedia != NULL) {
156 1.1 dbj int i;
157 1.1 dbj for (i = 0; i < sc->sc_nsupmedia; i++)
158 1.1 dbj ifmedia_add(&sc->sc_media, sc->sc_supmedia[i],
159 1.1 dbj 0, NULL);
160 1.1 dbj ifmedia_set(&sc->sc_media, sc->sc_defaultmedia);
161 1.1 dbj } else {
162 1.1 dbj ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL);
163 1.1 dbj ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL);
164 1.1 dbj }
165 1.1 dbj #endif
166 1.1 dbj
167 1.1 dbj /* Attach the interface. */
168 1.1 dbj if_attach(ifp);
169 1.1 dbj ether_ifattach(ifp, sc->sc_enaddr);
170 1.1 dbj
171 1.1 dbj /* decrease the mtu on this interface to deal with
172 1.1 dbj * alignment problems
173 1.1 dbj */
174 1.1 dbj ifp->if_mtu -= 16;
175 1.1 dbj
176 1.1 dbj #if NBPFILTER > 0
177 1.1 dbj bpfattach(&ifp->if_bpf, ifp, DLT_EN10MB, sizeof(struct ether_header));
178 1.1 dbj #endif
179 1.1 dbj
180 1.1 dbj sc->sc_sh = shutdownhook_establish(mb8795_shutdown, sc);
181 1.1 dbj if (sc->sc_sh == NULL)
182 1.1 dbj panic("mb8795_config: can't establish shutdownhook");
183 1.1 dbj
184 1.1 dbj #if NRND > 0
185 1.1 dbj rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname,
186 1.1 dbj RND_TYPE_NET);
187 1.1 dbj #endif
188 1.1 dbj
189 1.1 dbj /* Initialize the dma maps */
190 1.1 dbj {
191 1.1 dbj int error;
192 1.1 dbj if ((error = bus_dmamap_create(sc->sc_tx_dmat, MCLBYTES,
193 1.1 dbj (MCLBYTES/MSIZE), MCLBYTES, 0, BUS_DMA_ALLOCNOW,
194 1.1 dbj &sc->sc_tx_dmamap)) != 0) {
195 1.1 dbj panic("%s: can't create tx DMA map, error = %d\n",
196 1.1 dbj sc->sc_dev.dv_xname, error);
197 1.1 dbj }
198 1.1 dbj {
199 1.1 dbj int i;
200 1.1 dbj for(i=0;i<MB8795_NRXBUFS;i++) {
201 1.1 dbj if ((error = bus_dmamap_create(sc->sc_rx_dmat, MCLBYTES,
202 1.1 dbj (MCLBYTES/MSIZE), MCLBYTES, 0, BUS_DMA_ALLOCNOW,
203 1.1 dbj &sc->sc_rx_dmamap[i])) != 0) {
204 1.1 dbj panic("%s: can't create rx DMA map, error = %d\n",
205 1.1 dbj sc->sc_dev.dv_xname, error);
206 1.1 dbj }
207 1.1 dbj sc->sc_rx_mb_head[i] = NULL;
208 1.1 dbj }
209 1.1 dbj sc->sc_rx_loaded_idx = 0;
210 1.1 dbj sc->sc_rx_completed_idx = 0;
211 1.1 dbj sc->sc_rx_handled_idx = 0;
212 1.1 dbj }
213 1.1 dbj }
214 1.1 dbj
215 1.1 dbj /* @@@ more next hacks
216 1.1 dbj * the 2000 covers at least a 1500 mtu + headers
217 1.1 dbj * + DMA_BEGINALIGNMENT+ ENDMA_ENDALIGNMENT
218 1.1 dbj */
219 1.1 dbj sc->sc_txbuf = malloc(2000, M_DEVBUF, M_NOWAIT);
220 1.1 dbj if (!sc->sc_txbuf) panic("%s: can't malloc tx DMA buffer",
221 1.1 dbj sc->sc_dev.dv_xname);
222 1.1 dbj
223 1.1 dbj sc->sc_tx_mb_head = NULL;
224 1.1 dbj sc->sc_tx_loaded = 0;
225 1.1 dbj
226 1.1 dbj sc->sc_tx_nd->nd_chaining_flag = 0;
227 1.1 dbj sc->sc_tx_nd->nd_shutdown_cb = mb8795_txdma_shutdown;
228 1.1 dbj sc->sc_tx_nd->nd_continue_cb = mb8795_txdma_continue;
229 1.1 dbj sc->sc_tx_nd->nd_completed_cb = mb8795_txdma_completed;
230 1.1 dbj sc->sc_tx_nd->nd_cb_arg = sc;
231 1.1 dbj
232 1.1 dbj sc->sc_rx_nd->nd_chaining_flag = 1;
233 1.1 dbj sc->sc_rx_nd->nd_shutdown_cb = mb8795_rxdma_shutdown;
234 1.1 dbj sc->sc_rx_nd->nd_continue_cb = mb8795_rxdma_continue;
235 1.1 dbj sc->sc_rx_nd->nd_completed_cb = mb8795_rxdma_completed;
236 1.1 dbj sc->sc_rx_nd->nd_cb_arg = sc;
237 1.1 dbj
238 1.1 dbj DPRINTF(("%s: leaving mb8795_config()\n",sc->sc_dev.dv_xname));
239 1.1 dbj }
240 1.1 dbj
241 1.1 dbj
242 1.1 dbj /****************************************************************/
243 1.1 dbj
244 1.1 dbj #define XCHR(x) "0123456789abcdef"[(x) & 0xf]
245 1.1 dbj static void
246 1.1 dbj hex_dump(unsigned char *pkt, size_t len)
247 1.1 dbj {
248 1.1 dbj size_t i, j;
249 1.1 dbj
250 1.1 dbj printf("0000: ");
251 1.1 dbj for(i=0; i<len; i++) {
252 1.1 dbj printf("%c%c ", XCHR(pkt[i]>>4), XCHR(pkt[i]));
253 1.1 dbj if ((i+1) % 16 == 0) {
254 1.1 dbj printf(" %c", '"');
255 1.1 dbj for(j=0; j<16; j++)
256 1.1 dbj printf("%c", pkt[i-15+j]>=32 && pkt[i-15+j]<127?pkt[i-15+j]:'.');
257 1.1 dbj printf("%c\n%c%c%c%c: ", '"', XCHR((i+1)>>12),
258 1.1 dbj XCHR((i+1)>>8), XCHR((i+1)>>4), XCHR(i+1));
259 1.1 dbj }
260 1.1 dbj }
261 1.1 dbj printf("\n");
262 1.1 dbj }
263 1.1 dbj
264 1.1 dbj
265 1.1 dbj /*
266 1.1 dbj * Controller receive interrupt.
267 1.1 dbj */
268 1.1 dbj void
269 1.1 dbj mb8795_rint(sc)
270 1.1 dbj struct mb8795_softc *sc;
271 1.1 dbj {
272 1.1 dbj struct ifnet *ifp = &sc->sc_ethercom.ec_if;
273 1.1 dbj int error = 0;
274 1.1 dbj u_char rxstat;
275 1.1 dbj u_char rxmask;
276 1.1 dbj
277 1.1 dbj rxstat = bus_space_read_1(sc->sc_bst,sc->sc_bsh, XE_RXSTAT);
278 1.1 dbj rxmask = bus_space_read_1(sc->sc_bst,sc->sc_bsh, XE_RXMASK);
279 1.1 dbj
280 1.1 dbj bus_space_write_1(sc->sc_bst,sc->sc_bsh, XE_RXSTAT, XE_RXSTAT_CLEAR);
281 1.1 dbj
282 1.1 dbj #if 0
283 1.1 dbj DPRINTF(("%s: rx interrupt, rxstat = %b\n",
284 1.1 dbj sc->sc_dev.dv_xname, rxstat, XE_RXSTAT_BITS));
285 1.1 dbj #endif
286 1.1 dbj
287 1.1 dbj if (rxstat & XE_RXSTAT_RESET) {
288 1.1 dbj DPRINTF(("%s: rx reset packet\n",
289 1.1 dbj sc->sc_dev.dv_xname));
290 1.1 dbj error++;
291 1.1 dbj }
292 1.1 dbj if (rxstat & XE_RXSTAT_SHORT) {
293 1.1 dbj DPRINTF(("%s: rx short packet\n",
294 1.1 dbj sc->sc_dev.dv_xname));
295 1.1 dbj error++;
296 1.1 dbj }
297 1.1 dbj if (rxstat & XE_RXSTAT_ALIGNERR) {
298 1.1 dbj DPRINTF(("%s: rx alignment error\n",
299 1.1 dbj sc->sc_dev.dv_xname));
300 1.1 dbj error++;
301 1.1 dbj }
302 1.1 dbj if (rxstat & XE_RXSTAT_CRCERR) {
303 1.1 dbj DPRINTF(("%s: rx CRC error\n",
304 1.1 dbj sc->sc_dev.dv_xname));
305 1.1 dbj error++;
306 1.1 dbj }
307 1.1 dbj if (rxstat & XE_RXSTAT_OVERFLOW) {
308 1.1 dbj DPRINTF(("%s: rx overflow error\n",
309 1.1 dbj sc->sc_dev.dv_xname));
310 1.1 dbj error++;
311 1.1 dbj }
312 1.1 dbj
313 1.1 dbj if (error) {
314 1.1 dbj ifp->if_ierrors++;
315 1.1 dbj /* @@@ handle more gracefully, free memory, etc. */
316 1.1 dbj }
317 1.1 dbj
318 1.1 dbj if (rxstat & XE_RXSTAT_OK) {
319 1.1 dbj int s;
320 1.1 dbj s = spldma();
321 1.1 dbj
322 1.1 dbj while(sc->sc_rx_handled_idx != sc->sc_rx_completed_idx) {
323 1.1 dbj struct mbuf *m;
324 1.1 dbj bus_dmamap_t map;
325 1.1 dbj
326 1.1 dbj sc->sc_rx_handled_idx++;
327 1.1 dbj sc->sc_rx_handled_idx %= MB8795_NRXBUFS;
328 1.1 dbj
329 1.1 dbj /* Should probably not do this much while interrupts
330 1.1 dbj * are disabled, but for now we will.
331 1.1 dbj */
332 1.1 dbj
333 1.1 dbj map = sc->sc_rx_dmamap[sc->sc_rx_handled_idx];
334 1.1 dbj m = sc->sc_rx_mb_head[sc->sc_rx_handled_idx];
335 1.1 dbj
336 1.1 dbj bus_dmamap_sync(sc->sc_rx_dmat, map,
337 1.1 dbj 0, map->dm_mapsize, BUS_DMASYNC_POSTREAD);
338 1.1 dbj
339 1.1 dbj
340 1.1 dbj /* Find receive length and chop off CRC */
341 1.1 dbj /* @@@ assumes packet is all in first segment
342 1.1 dbj * also assumes segment length is length of packet.
343 1.1 dbj * see comment in nextdma.c nextdma_intr();
344 1.1 dbj */
345 1.1 dbj m->m_pkthdr.len = map->dm_segs[0].ds_len-4;
346 1.1 dbj m->m_len = map->dm_segs[0].ds_len-4;
347 1.1 dbj m->m_pkthdr.rcvif = ifp;
348 1.1 dbj
349 1.1 dbj bus_dmamap_unload(sc->sc_rx_dmat, map);
350 1.1 dbj
351 1.1 dbj /* Install a fresh mbuf for next packet */
352 1.1 dbj
353 1.1 dbj sc->sc_rx_mb_head[sc->sc_rx_handled_idx] =
354 1.1 dbj mb8795_rxdmamap_load(sc,map);
355 1.1 dbj
356 1.1 dbj /* enable interrupts while we process the packet */
357 1.1 dbj splx(s);
358 1.1 dbj
359 1.1 dbj #if defined(XE_DEBUG)
360 1.1 dbj /* Peek at the packet */
361 1.1 dbj DPRINTF(("%s: received packet, at VA 0x%08x-0x%08x,len %d\n",
362 1.1 dbj sc->sc_dev.dv_xname,mtod(m,u_char *),mtod(m,u_char *)+m->m_len,m->m_len));
363 1.1 dbj #if 0
364 1.1 dbj hex_dump(mtod(m,u_char *), m->m_pkthdr.len < 255 ? m->m_pkthdr.len : 128 );
365 1.1 dbj #endif
366 1.1 dbj #endif
367 1.1 dbj
368 1.1 dbj {
369 1.1 dbj struct ether_header *eh;
370 1.1 dbj
371 1.1 dbj ifp->if_ipackets++;
372 1.1 dbj debugipkt++;
373 1.1 dbj
374 1.1 dbj /* We assume that the header fit entirely in one mbuf. */
375 1.1 dbj eh = mtod(m, struct ether_header *);
376 1.1 dbj
377 1.1 dbj /* Pass the packet up, with the ether header sort-of removed. */
378 1.1 dbj m_adj(m, sizeof(struct ether_header));
379 1.1 dbj ether_input(ifp, eh, m);
380 1.1 dbj }
381 1.1 dbj
382 1.1 dbj s = spldma();
383 1.1 dbj
384 1.1 dbj }
385 1.1 dbj
386 1.1 dbj splx(s);
387 1.1 dbj
388 1.1 dbj }
389 1.1 dbj
390 1.1 dbj DPRINTF(("%s: rx interrupt, rxstat = %b\n",
391 1.1 dbj sc->sc_dev.dv_xname, rxstat, XE_RXSTAT_BITS));
392 1.1 dbj
393 1.1 dbj #if 0 && defined(XE_DEBUG)
394 1.1 dbj {
395 1.1 dbj DPRINTF(("rxstat = 0x%b\n",
396 1.1 dbj bus_space_read_1(sc->sc_bst,sc->sc_bsh, XE_RXSTAT), XE_RXSTAT_BITS));
397 1.1 dbj DPRINTF(("rxmask = 0x%b\n",
398 1.1 dbj bus_space_read_1(sc->sc_bst,sc->sc_bsh, XE_RXMASK), XE_RXMASK_BITS));
399 1.1 dbj DPRINTF(("rxmode = 0x%b\n",
400 1.1 dbj bus_space_read_1(sc->sc_bst,sc->sc_bsh, XE_RXMODE), XE_RXMODE_BITS));
401 1.1 dbj }
402 1.1 dbj #endif
403 1.1 dbj
404 1.1 dbj return;
405 1.1 dbj }
406 1.1 dbj
407 1.1 dbj /*
408 1.1 dbj * Controller transmit interrupt.
409 1.1 dbj */
410 1.1 dbj void
411 1.1 dbj mb8795_tint(sc)
412 1.1 dbj struct mb8795_softc *sc;
413 1.1 dbj
414 1.1 dbj {
415 1.1 dbj int reset = 0;
416 1.1 dbj u_char txstat;
417 1.1 dbj u_char txmask;
418 1.1 dbj struct ifnet *ifp = &sc->sc_ethercom.ec_if;
419 1.1 dbj
420 1.1 dbj txstat = bus_space_read_1(sc->sc_bst,sc->sc_bsh, XE_TXSTAT);
421 1.1 dbj txmask = bus_space_read_1(sc->sc_bst,sc->sc_bsh, XE_TXMASK);
422 1.1 dbj
423 1.1 dbj #if 0
424 1.1 dbj DPRINTF(("%s: tx interrupt, txstat = %b\n",
425 1.1 dbj sc->sc_dev.dv_xname, txstat, XE_TXSTAT_BITS));
426 1.1 dbj #endif
427 1.1 dbj
428 1.1 dbj if (txstat & XE_TXSTAT_SHORTED) {
429 1.1 dbj printf("%s: tx cable shorted\n", sc->sc_dev.dv_xname);
430 1.1 dbj ifp->if_oerrors++;
431 1.1 dbj }
432 1.1 dbj if (txstat & XE_TXSTAT_UNDERFLOW) {
433 1.1 dbj printf("%s: tx underflow\n", sc->sc_dev.dv_xname);
434 1.1 dbj ifp->if_oerrors++;
435 1.1 dbj }
436 1.1 dbj if (txstat & XE_TXSTAT_COLLERR) {
437 1.1 dbj DPRINTF(("%s: tx collision\n", sc->sc_dev.dv_xname));
438 1.1 dbj ifp->if_collisions++;
439 1.1 dbj }
440 1.1 dbj if (txstat & XE_TXSTAT_COLLERR16) {
441 1.1 dbj printf("%s: tx 16th collision\n", sc->sc_dev.dv_xname);
442 1.1 dbj ifp->if_oerrors++;
443 1.1 dbj ifp->if_collisions += 16;
444 1.1 dbj }
445 1.1 dbj
446 1.1 dbj if (reset) {
447 1.1 dbj mb8795_reset(sc);
448 1.1 dbj return;
449 1.1 dbj }
450 1.1 dbj
451 1.1 dbj #if 0
452 1.1 dbj if (txstat & XE_TXSTAT_READY) {
453 1.1 dbj
454 1.1 dbj panic("%s: unexpected tx interrupt %b",
455 1.1 dbj sc->sc_dev.dv_xname,txstat,XE_TXSTAT_BITS);
456 1.1 dbj
457 1.1 dbj /* turn interrupt off */
458 1.1 dbj bus_space_write_1(sc->sc_bst,sc->sc_bsh, XE_TXMASK,
459 1.1 dbj txmask & ~XE_TXMASK_READYIE);
460 1.1 dbj }
461 1.1 dbj #endif
462 1.1 dbj
463 1.1 dbj return;
464 1.1 dbj }
465 1.1 dbj
466 1.1 dbj /****************************************************************/
467 1.1 dbj
468 1.1 dbj void
469 1.1 dbj mb8795_reset(sc)
470 1.1 dbj struct mb8795_softc *sc;
471 1.1 dbj {
472 1.1 dbj int s;
473 1.1 dbj
474 1.1 dbj s = splimp();
475 1.1 dbj mb8795_init(sc);
476 1.1 dbj splx(s);
477 1.1 dbj }
478 1.1 dbj
479 1.1 dbj void
480 1.1 dbj mb8795_watchdog(ifp)
481 1.1 dbj struct ifnet *ifp;
482 1.1 dbj {
483 1.1 dbj struct mb8795_softc *sc = ifp->if_softc;
484 1.1 dbj
485 1.1 dbj log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname);
486 1.1 dbj ++ifp->if_oerrors;
487 1.1 dbj
488 1.1 dbj DPRINTF(("%s: %d input errors, %d input packets\n",
489 1.1 dbj sc->sc_dev.dv_xname, ifp->if_ierrors, ifp->if_ipackets));
490 1.1 dbj
491 1.1 dbj mb8795_reset(sc);
492 1.1 dbj }
493 1.1 dbj
494 1.1 dbj /*
495 1.1 dbj * Initialization of interface; set up initialization block
496 1.1 dbj * and transmit/receive descriptor rings.
497 1.1 dbj * @@@ error handling is bogus in here. memory leaks
498 1.1 dbj */
499 1.1 dbj void
500 1.1 dbj mb8795_init(sc)
501 1.1 dbj struct mb8795_softc *sc;
502 1.1 dbj {
503 1.1 dbj struct ifnet *ifp = &sc->sc_ethercom.ec_if;
504 1.1 dbj
505 1.1 dbj m_freem(sc->sc_tx_mb_head);
506 1.1 dbj sc->sc_tx_mb_head = NULL;
507 1.1 dbj sc->sc_tx_loaded = 0;
508 1.1 dbj
509 1.1 dbj {
510 1.1 dbj int i;
511 1.1 dbj for(i=0;i<MB8795_NRXBUFS;i++) {
512 1.1 dbj if (sc->sc_rx_mb_head[i]) {
513 1.1 dbj bus_dmamap_unload(sc->sc_rx_dmat, sc->sc_rx_dmamap[i]);
514 1.1 dbj m_freem(sc->sc_rx_mb_head[i]);
515 1.1 dbj }
516 1.1 dbj sc->sc_rx_mb_head[i] =
517 1.1 dbj mb8795_rxdmamap_load(sc, sc->sc_rx_dmamap[i]);
518 1.1 dbj }
519 1.1 dbj sc->sc_rx_loaded_idx = 0;
520 1.1 dbj sc->sc_rx_completed_idx = 0;
521 1.1 dbj sc->sc_rx_handled_idx = 0;
522 1.1 dbj }
523 1.1 dbj
524 1.1 dbj bus_space_write_1(sc->sc_bst,sc->sc_bsh, XE_RESET, XE_RESET_MODE);
525 1.1 dbj
526 1.1 dbj bus_space_write_1(sc->sc_bst,sc->sc_bsh, XE_TXMODE, XE_TXMODE_LB_DISABLE);
527 1.1 dbj #if 0 /* This interrupt was sometimes failing to ack correctly
528 1.1 dbj * causing a loop @@@
529 1.1 dbj */
530 1.1 dbj bus_space_write_1(sc->sc_bst,sc->sc_bsh, XE_TXMASK,
531 1.1 dbj XE_TXMASK_UNDERFLOWIE | XE_TXMASK_COLLIE | XE_TXMASK_COLL16IE
532 1.1 dbj | XE_TXMASK_PARERRIE);
533 1.1 dbj #else
534 1.1 dbj bus_space_write_1(sc->sc_bst,sc->sc_bsh, XE_TXMASK, 0);
535 1.1 dbj #endif
536 1.1 dbj bus_space_write_1(sc->sc_bst,sc->sc_bsh, XE_TXSTAT, XE_TXSTAT_CLEAR);
537 1.1 dbj
538 1.1 dbj bus_space_write_1(sc->sc_bst,sc->sc_bsh, XE_RXMODE, XE_RXMODE_NORMAL);
539 1.1 dbj
540 1.1 dbj bus_space_write_1(sc->sc_bst,sc->sc_bsh, XE_RXMASK,
541 1.1 dbj XE_RXMASK_OKIE | XE_RXMASK_RESETIE | XE_RXMASK_SHORTIE |
542 1.1 dbj XE_RXMASK_ALIGNERRIE | XE_RXMASK_CRCERRIE | XE_RXMASK_OVERFLOWIE);
543 1.1 dbj
544 1.1 dbj bus_space_write_1(sc->sc_bst,sc->sc_bsh, XE_RXSTAT, XE_RXSTAT_CLEAR);
545 1.1 dbj
546 1.1 dbj {
547 1.1 dbj int i;
548 1.1 dbj for(i=0;i<sizeof(sc->sc_enaddr);i++) {
549 1.1 dbj bus_space_write_1(sc->sc_bst,sc->sc_bsh,XE_ENADDR+i,sc->sc_enaddr[i]);
550 1.1 dbj }
551 1.1 dbj }
552 1.1 dbj
553 1.1 dbj DPRINTF(("%s: initializing ethernet %02x:%02x:%02x:%02x:%02x:%02x, size=%d\n",
554 1.1 dbj sc->sc_dev.dv_xname,
555 1.1 dbj sc->sc_enaddr[0],sc->sc_enaddr[1],sc->sc_enaddr[2],
556 1.1 dbj sc->sc_enaddr[3],sc->sc_enaddr[4],sc->sc_enaddr[5],
557 1.1 dbj sizeof(sc->sc_enaddr)));
558 1.1 dbj
559 1.1 dbj bus_space_write_1(sc->sc_bst,sc->sc_bsh, XE_RESET, 0);
560 1.1 dbj
561 1.1 dbj ifp->if_flags |= IFF_RUNNING;
562 1.1 dbj ifp->if_flags &= ~IFF_OACTIVE;
563 1.1 dbj ifp->if_timer = 0;
564 1.1 dbj
565 1.1 dbj nextdma_init(sc->sc_tx_nd);
566 1.1 dbj nextdma_init(sc->sc_rx_nd);
567 1.1 dbj
568 1.1 dbj nextdma_start(sc->sc_rx_nd, DMACSR_READ);
569 1.1 dbj
570 1.1 dbj if (ifp->if_snd.ifq_head != NULL) {
571 1.1 dbj mb8795_start(ifp);
572 1.1 dbj }
573 1.1 dbj }
574 1.1 dbj
575 1.1 dbj void
576 1.1 dbj mb8795_stop(sc)
577 1.1 dbj struct mb8795_softc *sc;
578 1.1 dbj {
579 1.1 dbj printf("%s: stop not implemented\n", sc->sc_dev.dv_xname);
580 1.1 dbj }
581 1.1 dbj
582 1.1 dbj
583 1.1 dbj void
584 1.1 dbj mb8795_shutdown(arg)
585 1.1 dbj void *arg;
586 1.1 dbj {
587 1.1 dbj struct mb8795_softc *sc = (struct mb8795_softc *)arg;
588 1.1 dbj mb8795_stop(sc);
589 1.1 dbj }
590 1.1 dbj
591 1.1 dbj /****************************************************************/
592 1.1 dbj int
593 1.1 dbj mb8795_ioctl(ifp, cmd, data)
594 1.1 dbj register struct ifnet *ifp;
595 1.1 dbj u_long cmd;
596 1.1 dbj caddr_t data;
597 1.1 dbj {
598 1.1 dbj register struct mb8795_softc *sc = ifp->if_softc;
599 1.1 dbj struct ifaddr *ifa = (struct ifaddr *)data;
600 1.1 dbj struct ifreq *ifr = (struct ifreq *)data;
601 1.1 dbj int s, error = 0;
602 1.1 dbj
603 1.1 dbj s = splimp();
604 1.1 dbj
605 1.1 dbj switch (cmd) {
606 1.1 dbj
607 1.1 dbj case SIOCSIFADDR:
608 1.1 dbj ifp->if_flags |= IFF_UP;
609 1.1 dbj
610 1.1 dbj switch (ifa->ifa_addr->sa_family) {
611 1.1 dbj #ifdef INET
612 1.1 dbj case AF_INET:
613 1.1 dbj mb8795_init(sc);
614 1.1 dbj arp_ifinit(ifp, ifa);
615 1.1 dbj break;
616 1.1 dbj #endif
617 1.1 dbj #ifdef NS
618 1.1 dbj case AF_NS:
619 1.1 dbj {
620 1.1 dbj register struct ns_addr *ina = &IA_SNS(ifa)->sns_addr;
621 1.1 dbj
622 1.1 dbj if (ns_nullhost(*ina))
623 1.1 dbj ina->x_host =
624 1.1 dbj *(union ns_host *)LLADDR(ifp->if_sadl);
625 1.1 dbj else {
626 1.1 dbj bcopy(ina->x_host.c_host,
627 1.1 dbj LLADDR(ifp->if_sadl),
628 1.1 dbj sizeof(sc->sc_enaddr));
629 1.1 dbj }
630 1.1 dbj /* Set new address. */
631 1.1 dbj mb8795_init(sc);
632 1.1 dbj break;
633 1.1 dbj }
634 1.1 dbj #endif
635 1.1 dbj default:
636 1.1 dbj mb8795_init(sc);
637 1.1 dbj break;
638 1.1 dbj }
639 1.1 dbj break;
640 1.1 dbj
641 1.1 dbj #if defined(CCITT) && defined(LLC)
642 1.1 dbj case SIOCSIFCONF_X25:
643 1.1 dbj ifp->if_flags |= IFF_UP;
644 1.1 dbj ifa->ifa_rtrequest = cons_rtrequest; /* XXX */
645 1.1 dbj error = x25_llcglue(PRC_IFUP, ifa->ifa_addr);
646 1.1 dbj if (error == 0)
647 1.1 dbj mb8795_init(sc);
648 1.1 dbj break;
649 1.1 dbj #endif /* CCITT && LLC */
650 1.1 dbj
651 1.1 dbj case SIOCSIFFLAGS:
652 1.1 dbj if ((ifp->if_flags & IFF_UP) == 0 &&
653 1.1 dbj (ifp->if_flags & IFF_RUNNING) != 0) {
654 1.1 dbj /*
655 1.1 dbj * If interface is marked down and it is running, then
656 1.1 dbj * stop it.
657 1.1 dbj */
658 1.1 dbj mb8795_stop(sc);
659 1.1 dbj ifp->if_flags &= ~IFF_RUNNING;
660 1.1 dbj } else if ((ifp->if_flags & IFF_UP) != 0 &&
661 1.1 dbj (ifp->if_flags & IFF_RUNNING) == 0) {
662 1.1 dbj /*
663 1.1 dbj * If interface is marked up and it is stopped, then
664 1.1 dbj * start it.
665 1.1 dbj */
666 1.1 dbj mb8795_init(sc);
667 1.1 dbj } else {
668 1.1 dbj /*
669 1.1 dbj * Reset the interface to pick up changes in any other
670 1.1 dbj * flags that affect hardware registers.
671 1.1 dbj */
672 1.1 dbj /*mb8795_stop(sc);*/
673 1.1 dbj mb8795_init(sc);
674 1.1 dbj }
675 1.1 dbj #ifdef XE_DEBUG
676 1.1 dbj if (ifp->if_flags & IFF_DEBUG)
677 1.1 dbj sc->sc_debug = 1;
678 1.1 dbj else
679 1.1 dbj sc->sc_debug = 0;
680 1.1 dbj #endif
681 1.1 dbj break;
682 1.1 dbj
683 1.1 dbj case SIOCADDMULTI:
684 1.1 dbj case SIOCDELMULTI:
685 1.1 dbj error = (cmd == SIOCADDMULTI) ?
686 1.1 dbj ether_addmulti(ifr, &sc->sc_ethercom) :
687 1.1 dbj ether_delmulti(ifr, &sc->sc_ethercom);
688 1.1 dbj
689 1.1 dbj if (error == ENETRESET) {
690 1.1 dbj /*
691 1.1 dbj * Multicast list has changed; set the hardware filter
692 1.1 dbj * accordingly.
693 1.1 dbj */
694 1.1 dbj mb8795_reset(sc);
695 1.1 dbj error = 0;
696 1.1 dbj }
697 1.1 dbj break;
698 1.1 dbj
699 1.1 dbj #if 0
700 1.1 dbj case SIOCGIFMEDIA:
701 1.1 dbj case SIOCSIFMEDIA:
702 1.1 dbj error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd);
703 1.1 dbj break;
704 1.1 dbj #endif
705 1.1 dbj
706 1.1 dbj default:
707 1.1 dbj error = EINVAL;
708 1.1 dbj break;
709 1.1 dbj }
710 1.1 dbj
711 1.1 dbj splx(s);
712 1.1 dbj
713 1.1 dbj #if 0
714 1.1 dbj DPRINTF(("DEBUG: mb8795_ioctl(0x%lx) returning %d\n",
715 1.1 dbj cmd,error));
716 1.1 dbj #endif
717 1.1 dbj
718 1.1 dbj return (error);
719 1.1 dbj }
720 1.1 dbj
721 1.1 dbj /*
722 1.1 dbj * Setup output on interface.
723 1.1 dbj * Get another datagram to send off of the interface queue, and map it to the
724 1.1 dbj * interface before starting the output.
725 1.1 dbj * Called only at splimp or interrupt level.
726 1.1 dbj */
727 1.1 dbj void
728 1.1 dbj mb8795_start(ifp)
729 1.1 dbj struct ifnet *ifp;
730 1.1 dbj {
731 1.1 dbj int error;
732 1.1 dbj struct mb8795_softc *sc = ifp->if_softc;
733 1.1 dbj
734 1.1 dbj if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
735 1.1 dbj return;
736 1.1 dbj
737 1.1 dbj DPRINTF(("%s: mb8795_start()\n",sc->sc_dev.dv_xname));
738 1.1 dbj
739 1.1 dbj #if (defined(DIAGNOSTIC))
740 1.1 dbj {
741 1.1 dbj u_char txstat;
742 1.1 dbj txstat = bus_space_read_1(sc->sc_bst,sc->sc_bsh, XE_TXSTAT);
743 1.1 dbj if (!(txstat & XE_TXSTAT_READY)) {
744 1.6 dbj /* @@@ I used to panic here, but then it paniced once.
745 1.6 dbj * Let's see if I can just reset instead. [ dbj 980706.1900 ]
746 1.6 dbj */
747 1.6 dbj printf("%s: transmitter not ready\n", sc->sc_dev.dv_xname);
748 1.6 dbj mb8795_reset(sc);
749 1.6 dbj return;
750 1.1 dbj }
751 1.1 dbj }
752 1.1 dbj #endif
753 1.1 dbj
754 1.1 dbj #if 0
755 1.1 dbj return; /* @@@ Turn off xmit for debugging */
756 1.1 dbj #endif
757 1.1 dbj
758 1.1 dbj bus_space_write_1(sc->sc_bst,sc->sc_bsh, XE_TXSTAT, XE_TXSTAT_CLEAR);
759 1.1 dbj
760 1.1 dbj IF_DEQUEUE(&ifp->if_snd, sc->sc_tx_mb_head);
761 1.1 dbj if (sc->sc_tx_mb_head == 0) {
762 1.1 dbj printf("%s: No packet to start\n",
763 1.1 dbj sc->sc_dev.dv_xname);
764 1.1 dbj return;
765 1.1 dbj }
766 1.1 dbj
767 1.1 dbj ifp->if_timer = 5;
768 1.1 dbj
769 1.1 dbj /* The following is a next specific hack that should
770 1.1 dbj * probably be moved out of MI code.
771 1.1 dbj * This macro assumes it can move forward as needed
772 1.1 dbj * in the buffer. Perhaps it should zero the extra buffer.
773 1.1 dbj */
774 1.1 dbj #define REALIGN_DMABUF(s,l) \
775 1.1 dbj { (s) = ((u_char *)(((unsigned)(s)+DMA_BEGINALIGNMENT-1) \
776 1.1 dbj &~(DMA_BEGINALIGNMENT-1))); \
777 1.1 dbj (l) = ((u_char *)(((unsigned)((s)+(l))+ENDMA_ENDALIGNMENT-1) \
778 1.1 dbj &~(ENDMA_ENDALIGNMENT-1)))-(s);}
779 1.1 dbj
780 1.1 dbj #if 0
781 1.1 dbj error = bus_dmamap_load_mbuf(sc->sc_tx_dmat,
782 1.1 dbj sc->sc_tx_dmamap,
783 1.1 dbj sc->sc_tx_mb_head,
784 1.1 dbj BUS_DMA_NOWAIT);
785 1.1 dbj #else
786 1.1 dbj {
787 1.1 dbj u_char *buf = sc->sc_txbuf;
788 1.1 dbj int buflen = 0;
789 1.1 dbj struct mbuf *m = sc->sc_tx_mb_head;
790 1.1 dbj buflen = m->m_pkthdr.len;
791 1.1 dbj
792 1.1 dbj /* Fix runt packets, @@@ memory overrun */
793 1.1 dbj if (buflen < ETHERMIN+sizeof(struct ether_header)) {
794 1.1 dbj buflen = ETHERMIN+sizeof(struct ether_header);
795 1.1 dbj }
796 1.1 dbj
797 1.1 dbj buflen += 15;
798 1.1 dbj REALIGN_DMABUF(buf,buflen);
799 1.1 dbj if (buflen > 1520) {
800 1.1 dbj panic("%s: packet too long\n",sc->sc_dev.dv_xname);
801 1.1 dbj }
802 1.1 dbj
803 1.1 dbj {
804 1.1 dbj u_char *p = buf;
805 1.1 dbj for (m=sc->sc_tx_mb_head; m; m = m->m_next) {
806 1.1 dbj if (m->m_len == 0) continue;
807 1.1 dbj bcopy(mtod(m, u_char *), p, m->m_len);
808 1.1 dbj p += m->m_len;
809 1.1 dbj }
810 1.1 dbj }
811 1.1 dbj
812 1.1 dbj error = bus_dmamap_load(sc->sc_tx_dmat, sc->sc_tx_dmamap,
813 1.1 dbj buf,buflen,NULL,BUS_DMA_NOWAIT);
814 1.1 dbj }
815 1.1 dbj #endif
816 1.1 dbj if (error) {
817 1.1 dbj printf("%s: can't load mbuf chain, error = %d\n",
818 1.1 dbj sc->sc_dev.dv_xname, error);
819 1.1 dbj m_freem(sc->sc_tx_mb_head);
820 1.1 dbj sc->sc_tx_mb_head = NULL;
821 1.1 dbj return;
822 1.1 dbj }
823 1.1 dbj sc->sc_tx_loaded++;
824 1.1 dbj
825 1.1 dbj #ifdef DIAGNOSTIC
826 1.1 dbj if (sc->sc_tx_loaded != 1) {
827 1.1 dbj panic("%s: sc->sc_tx_loaded is %d",sc->sc_dev.dv_xname,
828 1.1 dbj sc->sc_tx_loaded);
829 1.1 dbj }
830 1.1 dbj #endif
831 1.1 dbj
832 1.1 dbj ifp->if_flags |= IFF_OACTIVE;
833 1.1 dbj
834 1.1 dbj bus_dmamap_sync(sc->sc_tx_dmat, sc->sc_tx_dmamap, 0,
835 1.1 dbj sc->sc_tx_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE);
836 1.1 dbj
837 1.1 dbj nextdma_start(sc->sc_tx_nd, DMACSR_WRITE);
838 1.1 dbj
839 1.1 dbj #if NBPFILTER > 0
840 1.1 dbj /*
841 1.1 dbj * Pass packet to bpf if there is a listener.
842 1.1 dbj */
843 1.1 dbj if (ifp->if_bpf)
844 1.1 dbj bpf_mtap(ifp->if_bpf, sc->sc_tx_mb_head);
845 1.1 dbj #endif
846 1.1 dbj
847 1.1 dbj }
848 1.1 dbj
849 1.1 dbj /****************************************************************/
850 1.1 dbj
851 1.1 dbj void
852 1.1 dbj mb8795_txdma_completed(map, arg)
853 1.1 dbj bus_dmamap_t map;
854 1.1 dbj void *arg;
855 1.1 dbj {
856 1.1 dbj struct mb8795_softc *sc = arg;
857 1.1 dbj struct ifnet *ifp = &sc->sc_ethercom.ec_if;
858 1.1 dbj
859 1.1 dbj DPRINTF(("%s: mb8795_txdma_completed()\n",sc->sc_dev.dv_xname));
860 1.1 dbj
861 1.1 dbj #ifdef DIAGNOSTIC
862 1.1 dbj if (!sc->sc_tx_loaded) {
863 1.1 dbj panic("%s: tx completed never loaded ",sc->sc_dev.dv_xname);
864 1.1 dbj }
865 1.1 dbj if (map != sc->sc_tx_dmamap) {
866 1.1 dbj panic("%s: unexpected tx completed map",sc->sc_dev.dv_xname);
867 1.1 dbj }
868 1.1 dbj
869 1.1 dbj #endif
870 1.1 dbj }
871 1.1 dbj
872 1.1 dbj void
873 1.1 dbj mb8795_txdma_shutdown(arg)
874 1.1 dbj void *arg;
875 1.1 dbj {
876 1.1 dbj struct mb8795_softc *sc = arg;
877 1.1 dbj struct ifnet *ifp = &sc->sc_ethercom.ec_if;
878 1.1 dbj
879 1.1 dbj DPRINTF(("%s: mb8795_txdma_shutdown()\n",sc->sc_dev.dv_xname));
880 1.1 dbj
881 1.1 dbj #ifdef DIAGNOSTIC
882 1.1 dbj if (!sc->sc_tx_loaded) {
883 1.1 dbj panic("%s: tx shutdown never loaded ",sc->sc_dev.dv_xname);
884 1.1 dbj }
885 1.1 dbj #endif
886 1.1 dbj
887 1.1 dbj {
888 1.1 dbj
889 1.1 dbj if (sc->sc_tx_loaded) {
890 1.1 dbj bus_dmamap_sync(sc->sc_tx_dmat, sc->sc_tx_dmamap,
891 1.1 dbj 0, sc->sc_tx_dmamap->dm_mapsize,
892 1.1 dbj BUS_DMASYNC_POSTWRITE);
893 1.1 dbj bus_dmamap_unload(sc->sc_tx_dmat, sc->sc_tx_dmamap);
894 1.1 dbj m_freem(sc->sc_tx_mb_head);
895 1.1 dbj sc->sc_tx_mb_head = NULL;
896 1.1 dbj
897 1.1 dbj sc->sc_tx_loaded--;
898 1.1 dbj }
899 1.1 dbj
900 1.1 dbj #ifdef DIAGNOSTIC
901 1.1 dbj if (sc->sc_tx_loaded != 0) {
902 1.1 dbj panic("%s: sc->sc_tx_loaded is %d",sc->sc_dev.dv_xname,
903 1.1 dbj sc->sc_tx_loaded);
904 1.1 dbj }
905 1.1 dbj #endif
906 1.1 dbj
907 1.1 dbj ifp->if_flags &= ~IFF_OACTIVE;
908 1.1 dbj
909 1.1 dbj ifp->if_timer = 0;
910 1.1 dbj
911 1.1 dbj if (ifp->if_snd.ifq_head != NULL) {
912 1.1 dbj mb8795_start(ifp);
913 1.1 dbj }
914 1.1 dbj
915 1.1 dbj }
916 1.1 dbj
917 1.1 dbj #if 0
918 1.1 dbj /* Enable ready interrupt */
919 1.1 dbj bus_space_write_1(sc->sc_bst,sc->sc_bsh, XE_TXMASK,
920 1.1 dbj bus_space_read_1(sc->sc_bst,sc->sc_bsh, XE_TXMASK)
921 1.1 dbj | XE_TXMASK_READYIE);
922 1.1 dbj #endif
923 1.1 dbj }
924 1.1 dbj
925 1.1 dbj
926 1.1 dbj void
927 1.1 dbj mb8795_rxdma_completed(map, arg)
928 1.1 dbj bus_dmamap_t map;
929 1.1 dbj void *arg;
930 1.1 dbj {
931 1.1 dbj struct mb8795_softc *sc = arg;
932 1.1 dbj
933 1.1 dbj sc->sc_rx_completed_idx++;
934 1.1 dbj sc->sc_rx_completed_idx %= MB8795_NRXBUFS;
935 1.1 dbj
936 1.1 dbj DPRINTF(("%s: mb8795_rxdma_completed(), sc->sc_rx_completed_idx = %d\n",
937 1.1 dbj sc->sc_dev.dv_xname, sc->sc_rx_completed_idx));
938 1.1 dbj
939 1.1 dbj #if (defined(DIAGNOSTIC))
940 1.1 dbj if (map != sc->sc_rx_dmamap[sc->sc_rx_completed_idx]) {
941 1.1 dbj panic("%s: Unexpected rx dmamap completed\n",
942 1.1 dbj sc->sc_dev.dv_xname);
943 1.1 dbj }
944 1.1 dbj #endif
945 1.1 dbj }
946 1.1 dbj
947 1.1 dbj void
948 1.1 dbj mb8795_rxdma_shutdown(arg)
949 1.1 dbj void *arg;
950 1.1 dbj {
951 1.1 dbj struct mb8795_softc *sc = arg;
952 1.1 dbj
953 1.1 dbj printf("%s: mb8795_rxdma_shutdown(), resetting the interface\n",
954 1.1 dbj sc->sc_dev.dv_xname);
955 1.1 dbj
956 1.1 dbj /* we might want to just reset the DMA here instead,
957 1.1 dbj * but this will do.
958 1.1 dbj */
959 1.1 dbj mb8795_init(sc);
960 1.1 dbj }
961 1.1 dbj
962 1.1 dbj
963 1.1 dbj /*
964 1.1 dbj * load a dmamap with a freshly allocated mbuf
965 1.1 dbj */
966 1.1 dbj struct mbuf *
967 1.1 dbj mb8795_rxdmamap_load(sc,map)
968 1.1 dbj struct mb8795_softc *sc;
969 1.1 dbj bus_dmamap_t map;
970 1.1 dbj {
971 1.1 dbj struct ifnet *ifp = &sc->sc_ethercom.ec_if;
972 1.1 dbj struct mbuf *m;
973 1.1 dbj int error;
974 1.1 dbj
975 1.1 dbj MGETHDR(m, M_DONTWAIT, MT_DATA);
976 1.1 dbj if (m) {
977 1.1 dbj MCLGET(m, M_DONTWAIT);
978 1.1 dbj if ((m->m_flags & M_EXT) == 0) {
979 1.1 dbj m_freem(m);
980 1.1 dbj m = NULL;
981 1.1 dbj } else {
982 1.1 dbj m->m_len = MCLBYTES;
983 1.1 dbj }
984 1.1 dbj }
985 1.1 dbj if (!m) {
986 1.1 dbj /* @@@ Handle this gracefully by reusing a scratch buffer
987 1.1 dbj * or something.
988 1.1 dbj */
989 1.1 dbj panic("Unable to get memory for incoming ethernet\n");
990 1.1 dbj }
991 1.1 dbj
992 1.1 dbj /* Align buffer, @@@ next specific.
993 1.1 dbj * perhaps should be using M_ALIGN here instead?
994 1.1 dbj * First we give us a little room to align with.
995 1.1 dbj */
996 1.1 dbj {
997 1.1 dbj u_char *buf = m->m_data;
998 1.1 dbj int buflen = m->m_len;
999 1.1 dbj buflen -= ENDMA_ENDALIGNMENT+DMA_BEGINALIGNMENT;
1000 1.1 dbj REALIGN_DMABUF(buf, buflen);
1001 1.1 dbj m->m_data = buf;
1002 1.1 dbj m->m_len = buflen;
1003 1.1 dbj }
1004 1.1 dbj
1005 1.1 dbj m->m_pkthdr.rcvif = ifp;
1006 1.1 dbj m->m_pkthdr.len = m->m_len;
1007 1.1 dbj
1008 1.1 dbj error = bus_dmamap_load_mbuf(sc->sc_rx_dmat,
1009 1.1 dbj map, m, BUS_DMA_NOWAIT);
1010 1.1 dbj
1011 1.1 dbj bus_dmamap_sync(sc->sc_rx_dmat, map, 0,
1012 1.1 dbj map->dm_mapsize, BUS_DMASYNC_PREREAD);
1013 1.1 dbj
1014 1.1 dbj if (error) {
1015 1.1 dbj DPRINTF(("DEBUG: m->m_data = 0x%08x, m->m_len = %d\n",
1016 1.1 dbj m->m_data, m->m_len));
1017 1.1 dbj DPRINTF(("DEBUG: MCLBYTES = %d, map->_dm_size = %d\n",
1018 1.1 dbj MCLBYTES, map->_dm_size));
1019 1.1 dbj
1020 1.1 dbj panic("%s: can't load rx mbuf chain, error = %d\n",
1021 1.1 dbj sc->sc_dev.dv_xname, error);
1022 1.1 dbj m_freem(m);
1023 1.1 dbj m = NULL;
1024 1.1 dbj }
1025 1.1 dbj
1026 1.1 dbj return(m);
1027 1.1 dbj }
1028 1.1 dbj
1029 1.1 dbj bus_dmamap_t
1030 1.1 dbj mb8795_rxdma_continue(arg)
1031 1.1 dbj void *arg;
1032 1.1 dbj {
1033 1.1 dbj struct mb8795_softc *sc = arg;
1034 1.1 dbj bus_dmamap_t map = NULL;
1035 1.1 dbj
1036 1.1 dbj /*
1037 1.1 dbj * Currently, starts dumping new packets if the buffers
1038 1.1 dbj * fill up. This should probably reclaim unhandled
1039 1.1 dbj * buffers instead so we drop older packets instead
1040 1.1 dbj * of newer ones.
1041 1.1 dbj */
1042 1.1 dbj if (((sc->sc_rx_loaded_idx+1)%MB8795_NRXBUFS) != sc->sc_rx_handled_idx) {
1043 1.1 dbj sc->sc_rx_loaded_idx++;
1044 1.1 dbj sc->sc_rx_loaded_idx %= MB8795_NRXBUFS;
1045 1.1 dbj map = sc->sc_rx_dmamap[sc->sc_rx_loaded_idx];
1046 1.1 dbj
1047 1.1 dbj DPRINTF(("%s: mb8795_rxdma_continue() sc->sc_rx_loaded_idx = %d\nn",
1048 1.1 dbj sc->sc_dev.dv_xname,sc->sc_rx_loaded_idx));
1049 1.1 dbj }
1050 1.1 dbj #if (defined(DIAGNOSTIC))
1051 1.1 dbj else {
1052 1.6 dbj printf("%s: out of receive DMA buffers\n",sc->sc_dev.dv_xname);
1053 1.1 dbj }
1054 1.1 dbj #endif
1055 1.1 dbj
1056 1.1 dbj return(map);
1057 1.1 dbj }
1058 1.1 dbj
1059 1.1 dbj bus_dmamap_t
1060 1.1 dbj mb8795_txdma_continue(arg)
1061 1.1 dbj void *arg;
1062 1.1 dbj {
1063 1.1 dbj struct mb8795_softc *sc = arg;
1064 1.1 dbj bus_dmamap_t map = sc->sc_tx_dmamap;
1065 1.1 dbj
1066 1.1 dbj DPRINTF(("%s: mb8795_txdma_continue()\n",sc->sc_dev.dv_xname));
1067 1.1 dbj
1068 1.1 dbj #ifdef DIAGNOSTIC
1069 1.1 dbj if (sc->sc_tx_loaded != 1) {
1070 1.1 dbj panic("%s: sc->sc_tx_loaded is %d",sc->sc_dev.dv_xname,
1071 1.1 dbj sc->sc_tx_loaded);
1072 1.1 dbj }
1073 1.1 dbj #endif
1074 1.1 dbj
1075 1.1 dbj return(map);
1076 1.1 dbj }
1077 1.1 dbj
1078 1.1 dbj
1079 1.1 dbj /****************************************************************/
1080 1.1 dbj #if 0
1081 1.1 dbj int
1082 1.1 dbj mb8795_mediachange(ifp)
1083 1.1 dbj struct ifnet *ifp;
1084 1.1 dbj {
1085 1.1 dbj struct mb8795_softc *sc = ifp->if_softc;
1086 1.1 dbj
1087 1.1 dbj if (sc->sc_mediachange)
1088 1.1 dbj return ((*sc->sc_mediachange)(sc));
1089 1.1 dbj return (EINVAL);
1090 1.1 dbj }
1091 1.1 dbj
1092 1.1 dbj void
1093 1.1 dbj mb8795_mediastatus(ifp, ifmr)
1094 1.1 dbj struct ifnet *ifp;
1095 1.1 dbj struct ifmediareq *ifmr;
1096 1.1 dbj {
1097 1.1 dbj struct mb8795_softc *sc = ifp->if_softc;
1098 1.1 dbj
1099 1.1 dbj if ((ifp->if_flags & IFF_UP) == 0)
1100 1.1 dbj return;
1101 1.1 dbj
1102 1.1 dbj ifmr->ifm_status = IFM_AVALID;
1103 1.1 dbj if (sc->sc_havecarrier)
1104 1.1 dbj ifmr->ifm_status |= IFM_ACTIVE;
1105 1.1 dbj
1106 1.1 dbj if (sc->sc_mediastatus)
1107 1.1 dbj (*sc->sc_mediastatus)(sc, ifmr);
1108 1.1 dbj }
1109 1.1 dbj #endif
1110 1.1 dbj /****************************************************************/
1111