nextdma.c revision 1.10
1 /* $NetBSD: nextdma.c,v 1.10 1999/01/27 06:08:29 dbj Exp $ */ 2 /* 3 * Copyright (c) 1998 Darrin B. Jewell 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Darrin B. Jewell 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/mbuf.h> 35 #include <sys/syslog.h> 36 #include <sys/socket.h> 37 #include <sys/device.h> 38 #include <sys/malloc.h> 39 #include <sys/ioctl.h> 40 #include <sys/errno.h> 41 42 #include <machine/autoconf.h> 43 #include <machine/cpu.h> 44 #include <machine/intr.h> 45 46 #include <m68k/cacheops.h> 47 48 #include <next68k/next68k/isr.h> 49 50 #define _GENERIC_BUS_DMA_PRIVATE 51 #include <machine/bus.h> 52 53 #include "nextdmareg.h" 54 #include "nextdmavar.h" 55 56 #if 1 57 #define ND_DEBUG 58 #endif 59 60 #if defined(ND_DEBUG) 61 int nextdma_debug = 0; 62 #define DPRINTF(x) if (nextdma_debug) printf x; 63 #else 64 #define DPRINTF(x) 65 #endif 66 67 /* @@@ for debugging */ 68 struct nextdma_config *debugernd; 69 struct nextdma_config *debugexnd; 70 71 int nextdma_intr __P((void *)); 72 void next_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 73 bus_size_t, int)); 74 int next_dma_continue __P((struct nextdma_config *)); 75 void next_dma_rotate __P((struct nextdma_config *)); 76 77 void next_dma_setup_cont_regs __P((struct nextdma_config *)); 78 void next_dma_setup_curr_regs __P((struct nextdma_config *)); 79 80 void next_dma_print __P((struct nextdma_config *)); 81 82 void 83 nextdma_config(nd) 84 struct nextdma_config *nd; 85 { 86 /* Initialize the dma_tag. As a hack, we currently 87 * put the dma tag in the structure itself. It shouldn't be there. 88 */ 89 90 { 91 bus_dma_tag_t t; 92 t = &nd->_nd_dmat; 93 t->_cookie = nd; 94 t->_get_tag = NULL; /* lose */ 95 t->_dmamap_create = _bus_dmamap_create; 96 t->_dmamap_destroy = _bus_dmamap_destroy; 97 t->_dmamap_load = _bus_dmamap_load_direct; 98 t->_dmamap_load_mbuf = _bus_dmamap_load_mbuf_direct; 99 t->_dmamap_load_uio = _bus_dmamap_load_uio_direct; 100 t->_dmamap_load_raw = _bus_dmamap_load_raw_direct; 101 t->_dmamap_unload = _bus_dmamap_unload; 102 t->_dmamap_sync = next_dmamap_sync; 103 104 t->_dmamem_alloc = _bus_dmamem_alloc; 105 t->_dmamem_free = _bus_dmamem_free; 106 t->_dmamem_map = _bus_dmamem_map; 107 t->_dmamem_unmap = _bus_dmamem_unmap; 108 t->_dmamem_mmap = _bus_dmamem_mmap; 109 110 nd->nd_dmat = t; 111 } 112 113 /* @@@ for debugging */ 114 if (nd->nd_intr == NEXT_I_ENETR_DMA) { 115 debugernd = nd; 116 } 117 if (nd->nd_intr == NEXT_I_ENETX_DMA) { 118 debugexnd = nd; 119 } 120 121 nextdma_init(nd); 122 123 isrlink_autovec(nextdma_intr, nd, NEXT_I_IPL(nd->nd_intr), 10); 124 INTR_ENABLE(nd->nd_intr); 125 } 126 127 void 128 nextdma_init(nd) 129 struct nextdma_config *nd; 130 { 131 DPRINTF(("DMA init ipl (%ld) intr(0x%b)\n", 132 NEXT_I_IPL(nd->nd_intr), NEXT_I_BIT(nd->nd_intr),NEXT_INTR_BITS)); 133 134 /* @@@ should probably check and free these maps */ 135 nd->_nd_map = NULL; 136 nd->_nd_idx = 0; 137 nd->_nd_map_cont = NULL; 138 nd->_nd_idx_cont = 0; 139 140 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_CSR, 0); 141 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_CSR, 142 DMACSR_INITBUF | DMACSR_CLRCOMPLETE | DMACSR_RESET); 143 144 next_dma_setup_curr_regs(nd); 145 next_dma_setup_cont_regs(nd); 146 147 #if 0 && defined(DIAGNOSTIC) 148 /* Today, my computer (mourning) appears to fail this test. 149 * yesterday, another NeXT (milo) didn't have this problem 150 * Darrin B. Jewell <jewell (at) mit.edu> Mon May 25 07:53:05 1998 151 */ 152 { 153 u_long state; 154 state = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_CSR); 155 state = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_CSR); 156 state &= (DMACSR_BUSEXC | DMACSR_COMPLETE | 157 DMACSR_SUPDATE | DMACSR_ENABLE); 158 159 if (state) { 160 next_dma_print(nd); 161 panic("DMA did not reset\n"); 162 } 163 } 164 #endif 165 } 166 167 168 void 169 nextdma_reset(nd) 170 struct nextdma_config *nd; 171 { 172 int s; 173 s = spldma(); /* @@@ should this be splimp()? */ 174 175 DPRINTF(("DMA reset\n")); 176 177 #if (defined(ND_DEBUG)) 178 if (nextdma_debug) next_dma_print(nd); 179 #endif 180 181 nextdma_init(nd); 182 splx(s); 183 } 184 185 /****************************************************************/ 186 187 /* If the next had multiple busses, this should probably 188 * go elsewhere, but it is here anyway */ 189 void 190 next_dmamap_sync(t, map, offset, len, ops) 191 bus_dma_tag_t t; 192 bus_dmamap_t map; 193 bus_addr_t offset; 194 bus_size_t len; 195 int ops; 196 { 197 /* flush/purge the cache. 198 * assumes pointers are aligned 199 * @@@ should probably be fixed to use offset and len args. 200 * should also optimize this to work on pages for larger regions? 201 */ 202 if (ops & BUS_DMASYNC_PREWRITE) { 203 int i; 204 for(i=0;i<map->dm_nsegs;i++) { 205 bus_addr_t p = map->dm_segs[i].ds_addr; 206 bus_addr_t e = p+map->dm_segs[i].ds_len; 207 while(p<e) { 208 DCFL(p); /* flush */ 209 p += 16; /* cache line length */ 210 } 211 } 212 } 213 214 if (ops & BUS_DMASYNC_POSTREAD) { 215 int i; 216 for(i=0;i<map->dm_nsegs;i++) { 217 bus_addr_t p = map->dm_segs[i].ds_addr; 218 bus_addr_t e = p+map->dm_segs[i].ds_len; 219 while(p<e) { 220 DCPL(p); /* purge */ 221 p += 16; /* cache line length */ 222 } 223 } 224 } 225 } 226 227 /****************************************************************/ 228 229 230 /* Call the completed and continue callbacks to try to fill 231 * in the dma continue buffers. 232 */ 233 void 234 next_dma_rotate(nd) 235 struct nextdma_config *nd; 236 { 237 238 DPRINTF(("DMA next_dma_rotate()\n")); 239 240 /* If we've reached the end of the current map, then inform 241 * that we've completed that map. 242 */ 243 if (nd->_nd_map && ((nd->_nd_idx+1) == nd->_nd_map->dm_nsegs)) { 244 if (nd->nd_completed_cb) 245 (*nd->nd_completed_cb)(nd->_nd_map, nd->nd_cb_arg); 246 } 247 248 /* Rotate the continue map into the current map */ 249 nd->_nd_map = nd->_nd_map_cont; 250 nd->_nd_idx = nd->_nd_idx_cont; 251 252 if ((!nd->_nd_map_cont) || 253 ((nd->_nd_map_cont) && 254 (++nd->_nd_idx_cont >= nd->_nd_map_cont->dm_nsegs))) { 255 if (nd->nd_continue_cb) { 256 nd->_nd_map_cont = (*nd->nd_continue_cb)(nd->nd_cb_arg); 257 } else { 258 nd->_nd_map_cont = 0; 259 } 260 nd->_nd_idx_cont = 0; 261 } 262 263 #ifdef DIAGNOSTIC 264 if (nd->_nd_map_cont) { 265 if (!DMA_BEGINALIGNED(nd->_nd_map_cont->dm_segs[nd->_nd_idx].ds_addr)) { 266 panic("DMA request unaligned at start\n"); 267 } 268 if (!DMA_ENDALIGNED(nd->_nd_map_cont->dm_segs[nd->_nd_idx].ds_addr + 269 nd->_nd_map_cont->dm_segs[nd->_nd_idx].ds_len)) { 270 panic("DMA request unaligned at end\n"); 271 } 272 } 273 #endif 274 275 } 276 277 void 278 next_dma_setup_cont_regs(nd) 279 struct nextdma_config *nd; 280 { 281 DPRINTF(("DMA next_dma_setup_regs()\n")); 282 283 if (nd->_nd_map_cont) { 284 285 if (nd->nd_intr == NEXT_I_ENETX_DMA) { 286 /* Ethernet transmit needs secret magic */ 287 288 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_START, 289 nd->_nd_map_cont->dm_segs[nd->_nd_idx_cont].ds_addr); 290 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_STOP, 291 ((nd->_nd_map_cont->dm_segs[nd->_nd_idx_cont].ds_addr + 292 nd->_nd_map_cont->dm_segs[nd->_nd_idx_cont].ds_len) 293 + 0x0) | 0x80000000); 294 } else { 295 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_START, 296 nd->_nd_map_cont->dm_segs[nd->_nd_idx_cont].ds_addr); 297 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_STOP, 298 nd->_nd_map_cont->dm_segs[nd->_nd_idx_cont].ds_addr + 299 nd->_nd_map_cont->dm_segs[nd->_nd_idx_cont].ds_len); 300 } 301 302 } else { 303 304 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_START, 0xdeadbeef); 305 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_STOP, 0xdeadbeef); 306 } 307 308 #if 1 /* 0xfeedbeef in these registers leads to instability. it will 309 * panic after a short while with 0xfeedbeef in the DD_START and DD_STOP 310 * registers. I suspect that an unexpected hardware restart 311 * is cycling the bogus values into the active registers. Until 312 * that is understood, we seed these with the same as DD_START and DD_STOP 313 */ 314 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_START, 315 bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_START)); 316 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_STOP, 317 bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_STOP)); 318 #else 319 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_START, 0xfeedbeef); 320 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_STOP, 0xfeedbeef); 321 #endif 322 323 } 324 325 void 326 next_dma_setup_curr_regs(nd) 327 struct nextdma_config *nd; 328 { 329 DPRINTF(("DMA next_dma_setup_curr_regs()\n")); 330 331 if (nd->nd_intr == NEXT_I_ENETX_DMA) { 332 /* Ethernet transmit needs secret magic */ 333 334 if (nd->_nd_map) { 335 336 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_NEXT_INITBUF, 337 nd->_nd_map->dm_segs[nd->_nd_idx].ds_addr); 338 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_LIMIT, 339 ((nd->_nd_map->dm_segs[nd->_nd_idx].ds_addr + 340 nd->_nd_map->dm_segs[nd->_nd_idx].ds_len) 341 + 0x0) | 0x80000000); 342 } else { 343 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_NEXT_INITBUF,0xdeadbeef); 344 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_LIMIT, 0xdeadbeef); 345 346 } 347 348 #if 1 /* See comment in next_dma_setup_cont_regs() above */ 349 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_NEXT, 350 bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_NEXT_INITBUF)); 351 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_LIMIT, 352 bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_LIMIT)); 353 #else 354 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_NEXT, 0xfeedbeef); 355 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_LIMIT, 0xfeedbeef); 356 #endif 357 358 } else { 359 360 if (nd->_nd_map) { 361 362 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_NEXT_INITBUF, 363 nd->_nd_map->dm_segs[nd->_nd_idx].ds_addr); 364 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_LIMIT, 365 nd->_nd_map->dm_segs[nd->_nd_idx].ds_addr + 366 nd->_nd_map->dm_segs[nd->_nd_idx].ds_len); 367 } else { 368 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_NEXT_INITBUF, 0xdeadbeef); 369 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_LIMIT, 0xdeadbeef); 370 371 } 372 373 #if 1 /* See comment in next_dma_setup_cont_regs() above */ 374 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_NEXT, 375 bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_NEXT_INITBUF)); 376 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_LIMIT, 377 bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_LIMIT)); 378 #else 379 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_NEXT, 0xfeedbeef); 380 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_LIMIT, 0xfeedbeef); 381 #endif 382 383 } 384 385 } 386 387 388 /* This routine is used for debugging */ 389 390 void 391 next_dma_print(nd) 392 struct nextdma_config *nd; 393 { 394 u_long dd_csr; 395 u_long dd_next; 396 u_long dd_next_initbuf; 397 u_long dd_limit; 398 u_long dd_start; 399 u_long dd_stop; 400 u_long dd_saved_next; 401 u_long dd_saved_limit; 402 u_long dd_saved_start; 403 u_long dd_saved_stop; 404 405 /* Read all of the registers before we print anything out, 406 * in case something changes 407 */ 408 dd_csr = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_CSR); 409 dd_next = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_NEXT); 410 dd_next_initbuf = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_NEXT_INITBUF); 411 dd_limit = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_LIMIT); 412 dd_start = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_START); 413 dd_stop = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_STOP); 414 dd_saved_next = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_NEXT); 415 dd_saved_limit = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_LIMIT); 416 dd_saved_start = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_START); 417 dd_saved_stop = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_STOP); 418 419 if (nd->_nd_map) { 420 printf("NDMAP: nd->_nd_map->dm_segs[%d].ds_addr = 0x%08lx\n", 421 nd->_nd_idx,nd->_nd_map->dm_segs[nd->_nd_idx].ds_addr); 422 printf("NDMAP: nd->_nd_map->dm_segs[%d].ds_len = %d\n", 423 nd->_nd_idx,nd->_nd_map->dm_segs[nd->_nd_idx].ds_len); 424 } else { 425 printf("NDMAP: nd->_nd_map = NULL\n"); 426 } 427 if (nd->_nd_map_cont) { 428 printf("NDMAP: nd->_nd_map_cont->dm_segs[%d].ds_addr = 0x%08lx\n", 429 nd->_nd_idx_cont,nd->_nd_map_cont->dm_segs[nd->_nd_idx_cont].ds_addr); 430 printf("NDMAP: nd->_nd_map_cont->dm_segs[%d].ds_len = %d\n", 431 nd->_nd_idx_cont,nd->_nd_map_cont->dm_segs[nd->_nd_idx_cont].ds_len); 432 } else { 433 printf("NDMAP: nd->_nd_map_cont = NULL\n"); 434 } 435 436 printf("NDMAP: dd->dd_csr = 0x%b\n", dd_csr, DMACSR_BITS); 437 printf("NDMAP: dd->dd_saved_next = 0x%08x\n", dd_saved_next); 438 printf("NDMAP: dd->dd_saved_limit = 0x%08x\n", dd_saved_limit); 439 printf("NDMAP: dd->dd_saved_start = 0x%08x\n", dd_saved_start); 440 printf("NDMAP: dd->dd_saved_stop = 0x%08x\n", dd_saved_stop); 441 printf("NDMAP: dd->dd_next = 0x%08x\n", dd_next); 442 printf("NDMAP: dd->dd_next_initbuf = 0x%08x\n", dd_next_initbuf); 443 printf("NDMAP: dd->dd_limit = 0x%08x\n", dd_limit); 444 printf("NDMAP: dd->dd_start = 0x%08x\n", dd_start); 445 printf("NDMAP: dd->dd_stop = 0x%08x\n", dd_stop); 446 447 printf("NDMAP: interrupt ipl (%ld) intr(0x%b)\n", 448 NEXT_I_IPL(nd->nd_intr), NEXT_I_BIT(nd->nd_intr),NEXT_INTR_BITS); 449 } 450 451 /****************************************************************/ 452 453 int 454 nextdma_intr(arg) 455 void *arg; 456 { 457 struct nextdma_config *nd = arg; 458 459 /* @@@ This is bogus, we can't be certain of arg's type 460 * unless the interrupt is for us 461 */ 462 463 if (!INTR_OCCURRED(nd->nd_intr)) return 0; 464 /* Handle dma interrupts */ 465 466 #ifdef DIAGNOSTIC 467 if (nd->nd_intr == NEXT_I_ENETR_DMA) { 468 if (debugernd != nd) { 469 panic("DMA incorrect handling of rx nd->nd_intr"); 470 } 471 } 472 if (nd->nd_intr == NEXT_I_ENETX_DMA) { 473 if (debugexnd != nd) { 474 panic("DMA incorrect handling of tx nd->nd_intr"); 475 } 476 } 477 #endif 478 479 DPRINTF(("DMA interrupt ipl (%ld) intr(0x%b)\n", 480 NEXT_I_IPL(nd->nd_intr), NEXT_I_BIT(nd->nd_intr),NEXT_INTR_BITS)); 481 482 #ifdef DIAGNOSTIC 483 if (!nd->_nd_map) { 484 next_dma_print(nd); 485 panic("DMA missing current map in interrupt!\n"); 486 } 487 #endif 488 489 { 490 int state = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_CSR); 491 492 #ifdef DIAGNOSTIC 493 if (!(state & DMACSR_COMPLETE)) { 494 next_dma_print(nd); 495 printf("DEBUG: state = 0x%b\n", state,DMACSR_BITS); 496 panic("DMA ipl (%ld) intr(0x%b), DMACSR_COMPLETE not set in intr\n", 497 NEXT_I_IPL(nd->nd_intr), NEXT_I_BIT(nd->nd_intr),NEXT_INTR_BITS); 498 } 499 #endif 500 501 #if 0 /* This bit gets set sometimes & I don't know why. */ 502 #ifdef DIAGNOSTIC 503 if (state & DMACSR_BUSEXC) { 504 next_dma_print(nd); 505 printf("DEBUG: state = 0x%b\n", state,DMACSR_BITS); 506 panic("DMA ipl (%ld) intr(0x%b), DMACSR_COMPLETE not set in intr\n", 507 NEXT_I_IPL(nd->nd_intr), NEXT_I_BIT(nd->nd_intr),NEXT_INTR_BITS); 508 } 509 #endif 510 #endif 511 512 /* Check to see if we are expecting dma to shut down */ 513 if (!nd->_nd_map_cont) { 514 515 #ifdef DIAGNOSTIC 516 if (state & (DMACSR_SUPDATE|DMACSR_ENABLE)) { 517 next_dma_print(nd); 518 panic("unexpected bits set in DMA state at shutdown (0x%b)\n", state,DMACSR_BITS); 519 } 520 #endif 521 522 #ifdef DIAGNOSTIC 523 #if 0 /* Sometimes the DMA registers have totally bogus values when read. 524 * Until that's understood, we skip this check 525 */ 526 527 /* Verify that the registers are laid out as expected */ 528 { 529 bus_addr_t next; 530 bus_addr_t limit; 531 bus_addr_t expected_limit; 532 expected_limit = 533 nd->_nd_map->dm_segs[nd->_nd_idx].ds_addr + 534 nd->_nd_map->dm_segs[nd->_nd_idx].ds_len; 535 536 if (nd->nd_intr == NEXT_I_ENETX_DMA) { 537 next = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_NEXT_INITBUF); 538 limit = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_LIMIT) & ~0x80000000; 539 } else { 540 next = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_NEXT); 541 limit = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_LIMIT); 542 } 543 544 if ((next != limit) || (limit != expected_limit)) { 545 next_dma_print(nd); 546 printf("DEBUG: state = 0x%b\n", state,DMACSR_BITS); 547 panic("unexpected DMA limit at shutdown 0x%08x, 0x%08x, 0x%08x", 548 next,limit,expected_limit); 549 } 550 } 551 #endif 552 #endif 553 554 if ((nd->_nd_idx+1) == nd->_nd_map->dm_nsegs) { 555 if (nd->nd_completed_cb) 556 (*nd->nd_completed_cb)(nd->_nd_map, nd->nd_cb_arg); 557 } 558 nd->_nd_map = 0; 559 nd->_nd_idx = 0; 560 561 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_CSR, 562 DMACSR_CLRCOMPLETE | DMACSR_RESET); 563 564 DPRINTF(("DMA: a normal and expected shutdown occurred\n")); 565 if (nd->nd_shutdown_cb) (*nd->nd_shutdown_cb)(nd->nd_cb_arg); 566 567 return(1); 568 } 569 570 #if 0 571 #ifdef DIAGNOSTIC 572 if (!(state & DMACSR_SUPDATE)) { 573 next_dma_print(nd); 574 printf("DEBUG: state = 0x%b\n", state,DMACSR_BITS); 575 panic("SUPDATE not set with continuing DMA"); 576 } 577 #endif 578 #endif 579 580 /* Check that the buffer we are interrupted for is the one we expect. 581 * Shorten the buffer if the dma completed with a short buffer 582 */ 583 { 584 bus_addr_t next; 585 bus_addr_t limit; 586 bus_addr_t expected_next; 587 bus_addr_t expected_limit; 588 589 expected_next = nd->_nd_map->dm_segs[nd->_nd_idx].ds_addr; 590 expected_limit = expected_next + nd->_nd_map->dm_segs[nd->_nd_idx].ds_len; 591 592 #if 0 /* for some unknown reason, somtimes DD_SAVED_NEXT has value from 593 * nd->_nd_map and sometimes it has value from nd->_nd_map_cont. 594 * Somtimes, it has a completely different unknown value. 595 * Until that's understood, we won't sanity check the expected_next value. 596 */ 597 next = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_NEXT); 598 #else 599 next = expected_next; 600 #endif 601 limit = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_LIMIT); 602 603 if (nd->nd_intr == NEXT_I_ENETX_DMA) { 604 limit &= ~0x80000000; 605 } 606 607 if ((limit-next < 0) || 608 (limit-next >= expected_limit-expected_next)) { 609 #ifdef DIAGNOSTIC 610 #if 0 /* Sometimes, (under load I think) even DD_SAVED_LIMIT has 611 * a bogus value. Until that's understood, we don't panic 612 * here. 613 */ 614 next_dma_print(nd); 615 printf("DEBUG: state = 0x%b\n", state,DMACSR_BITS); 616 panic("Unexpected saved registers values."); 617 #endif 618 #endif 619 } else { 620 /* Set the length of the segment to match actual length. 621 * @@@ is it okay to resize dma segments here? 622 * i should probably ask jason about this. 623 */ 624 nd->_nd_map->dm_segs[nd->_nd_idx].ds_len = limit-next; 625 expected_limit = expected_next + nd->_nd_map->dm_segs[nd->_nd_idx].ds_len; 626 } 627 628 #if 0 /* these checks are turned off until the above mentioned weirdness is fixed. */ 629 #ifdef DIAGNOSTIC 630 if (next != expected_next) { 631 next_dma_print(nd); 632 printf("DEBUG: state = 0x%b\n", state,DMACSR_BITS); 633 panic("unexpected DMA next buffer in interrupt (found 0x%08x, expected 0x%08x)", 634 next,expected_next); 635 } 636 if (limit != expected_limit) { 637 next_dma_print(nd); 638 printf("DEBUG: state = 0x%b\n", state,DMACSR_BITS); 639 panic("unexpected DMA limit buffer in interrupt (found 0x%08x, expected 0x%08x)", 640 limit,expected_limit); 641 } 642 #endif 643 #endif 644 } 645 646 next_dma_rotate(nd); 647 next_dma_setup_cont_regs(nd); 648 649 if (!(state & DMACSR_ENABLE)) { 650 651 DPRINTF(("Unexpected DMA shutdown, restarting\n")); 652 653 if (nd->_nd_map_cont) { 654 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_CSR, 655 DMACSR_SETSUPDATE | DMACSR_SETENABLE | nd->_nd_dmadir); 656 } else { 657 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_CSR, 658 DMACSR_SETENABLE | nd->_nd_dmadir); 659 } 660 661 } else { 662 663 if (nd->_nd_map_cont) { 664 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_CSR, 665 DMACSR_SETSUPDATE | DMACSR_CLRCOMPLETE | nd->_nd_dmadir); 666 } else { 667 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_CSR, 668 DMACSR_CLRCOMPLETE | nd->_nd_dmadir); 669 } 670 } 671 672 } 673 674 DPRINTF(("DMA exiting interrupt ipl (%ld) intr(0x%b)\n", 675 NEXT_I_IPL(nd->nd_intr), NEXT_I_BIT(nd->nd_intr),NEXT_INTR_BITS)); 676 677 return(1); 678 } 679 680 /* 681 * Check to see if dma has finished for a channel */ 682 int 683 nextdma_finished(nd) 684 struct nextdma_config *nd; 685 { 686 int r; 687 int s; 688 s = spldma(); /* @@@ should this be splimp()? */ 689 r = (nd->_nd_map == NULL) && (nd->_nd_map_cont == NULL); 690 splx(s); 691 return(r); 692 } 693 694 void 695 nextdma_start(nd, dmadir) 696 struct nextdma_config *nd; 697 u_long dmadir; /* DMACSR_READ or DMACSR_WRITE */ 698 { 699 700 #ifdef DIAGNOSTIC 701 if (!nextdma_finished(nd)) { 702 panic("DMA trying to start before previous finished on intr(0x%b)\n", 703 NEXT_I_BIT(nd->nd_intr),NEXT_INTR_BITS); 704 } 705 #endif 706 707 DPRINTF(("DMA start (%ld) intr(0x%b)\n", 708 NEXT_I_IPL(nd->nd_intr), NEXT_I_BIT(nd->nd_intr),NEXT_INTR_BITS)); 709 710 #ifdef DIAGNOSTIC 711 if (nd->_nd_map) { 712 next_dma_print(nd); 713 panic("DMA: nextdma_start() with non null map\n"); 714 } 715 if (nd->_nd_map_cont) { 716 next_dma_print(nd); 717 panic("DMA: nextdma_start() with non null continue map\n"); 718 } 719 #endif 720 721 #ifdef DIAGNOSTIC 722 if ((dmadir != DMACSR_READ) && (dmadir != DMACSR_WRITE)) { 723 panic("DMA: nextdma_start(), dmadir arg must be DMACSR_READ or DMACSR_WRITE\n"); 724 } 725 #endif 726 727 nd->_nd_dmadir = dmadir; 728 729 /* preload both the current and the continue maps */ 730 next_dma_rotate(nd); 731 732 #ifdef DIAGNOSTIC 733 if (!nd->_nd_map_cont) { 734 panic("No map available in nextdma_start()"); 735 } 736 #endif 737 738 next_dma_rotate(nd); 739 740 DPRINTF(("DMA initiating DMA %s of %d segments on intr(0x%b)\n", 741 (nd->_nd_dmadir == DMACSR_READ ? "read" : "write"), nd->_nd_map->dm_nsegs, 742 NEXT_I_BIT(nd->nd_intr),NEXT_INTR_BITS)); 743 744 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_CSR, 0); 745 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_CSR, 746 DMACSR_INITBUF | DMACSR_RESET | nd->_nd_dmadir); 747 748 next_dma_setup_curr_regs(nd); 749 next_dma_setup_cont_regs(nd); 750 751 #if (defined(ND_DEBUG)) 752 if (nextdma_debug) next_dma_print(nd); 753 #endif 754 755 if (nd->_nd_map_cont) { 756 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_CSR, 757 DMACSR_SETSUPDATE | DMACSR_SETENABLE | nd->_nd_dmadir); 758 } else { 759 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_CSR, 760 DMACSR_SETENABLE | nd->_nd_dmadir); 761 } 762 763 } 764
Indexes created Thu Sep 25 16:09:42 GMT 2025