nextdma.c revision 1.2
1 /* $NetBSD: nextdma.c,v 1.2 1998/07/01 22:14:44 dbj Exp $ */ 2 /* 3 * Copyright (c) 1998 Darrin B. Jewell 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Darrin B. Jewell 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/mbuf.h> 35 #include <sys/syslog.h> 36 #include <sys/socket.h> 37 #include <sys/device.h> 38 #include <sys/malloc.h> 39 #include <sys/ioctl.h> 40 #include <sys/errno.h> 41 42 #include <machine/autoconf.h> 43 #include <machine/cpu.h> 44 #include <machine/intr.h> 45 46 #include <next68k/next68k/isr.h> 47 48 #define _GENERIC_BUS_DMA_PRIVATE 49 #include <machine/bus.h> 50 51 #include "nextdmareg.h" 52 #include "nextdmavar.h" 53 54 #if 0 55 #define ND_DEBUG 56 #endif 57 58 #if defined(ND_DEBUG) 59 #define DPRINTF(x) printf x; 60 #else 61 #define DPRINTF(x) 62 #endif 63 64 /* @@@ for debugging */ 65 struct nextdma_config *debugernd; 66 struct nextdma_config *debugexnd; 67 68 int nextdma_intr __P((void *)); 69 void next_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 70 bus_size_t, int)); 71 int next_dma_continue __P((struct nextdma_config *)); 72 void next_dma_rotate __P((struct nextdma_config *)); 73 74 void next_dma_setup_cont_regs __P((struct nextdma_config *)); 75 void next_dma_setup_curr_regs __P((struct nextdma_config *)); 76 77 void next_dma_print __P((struct nextdma_config *)); 78 79 void 80 nextdma_config(nd) 81 struct nextdma_config *nd; 82 { 83 /* Initialize the dma_tag. As a hack, we currently 84 * put the dma tag in the structure itself. It shouldn't be there. 85 */ 86 87 { 88 bus_dma_tag_t t; 89 t = &nd->_nd_dmat; 90 t->_cookie = nd; 91 t->_get_tag = NULL; /* lose */ 92 t->_dmamap_create = _bus_dmamap_create; 93 t->_dmamap_destroy = _bus_dmamap_destroy; 94 t->_dmamap_load = _bus_dmamap_load_direct; 95 t->_dmamap_load_mbuf = _bus_dmamap_load_mbuf_direct; 96 t->_dmamap_load_uio = _bus_dmamap_load_uio_direct; 97 t->_dmamap_load_raw = _bus_dmamap_load_raw_direct; 98 t->_dmamap_unload = _bus_dmamap_unload; 99 t->_dmamap_sync = next_dmamap_sync; 100 101 t->_dmamem_alloc = _bus_dmamem_alloc; 102 t->_dmamem_free = _bus_dmamem_free; 103 t->_dmamem_map = _bus_dmamem_map; 104 t->_dmamem_unmap = _bus_dmamem_unmap; 105 t->_dmamem_mmap = _bus_dmamem_mmap; 106 107 nd->nd_dmat = t; 108 } 109 110 /* @@@ for debugging */ 111 if (nd->nd_intr == NEXT_I_ENETR_DMA) { 112 debugernd = nd; 113 } 114 if (nd->nd_intr == NEXT_I_ENETX_DMA) { 115 debugexnd = nd; 116 } 117 118 nextdma_init(nd); 119 120 isrlink_autovec(nextdma_intr, nd, NEXT_I_IPL(nd->nd_intr), 10); 121 INTR_ENABLE(nd->nd_intr); 122 } 123 124 void 125 nextdma_init(nd) 126 struct nextdma_config *nd; 127 { 128 DPRINTF(("DMA init ipl (%ld) intr(0x%b)\n", 129 NEXT_I_IPL(nd->nd_intr), NEXT_I_BIT(nd->nd_intr),NEXT_INTR_BITS)); 130 131 /* @@@ should probably check and free these maps */ 132 nd->_nd_map = NULL; 133 nd->_nd_idx = 0; 134 nd->_nd_map_cont = NULL; 135 nd->_nd_idx_cont = 0; 136 137 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_CSR, 0); 138 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_CSR, 139 DMACSR_INITBUF | DMACSR_CLRCOMPLETE | DMACSR_RESET); 140 141 next_dma_setup_curr_regs(nd); 142 next_dma_setup_cont_regs(nd); 143 144 #if 0 && defined(DIAGNOSTIC) 145 /* Today, my computer (mourning) appears to fail this test. 146 * yesterday, another NeXT (milo) didn't have this problem 147 * Darrin B. Jewell <jewell (at) mit.edu> Mon May 25 07:53:05 1998 148 */ 149 { 150 u_long state; 151 state = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_CSR); 152 state = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_CSR); 153 state &= (DMACSR_BUSEXC | DMACSR_COMPLETE | 154 DMACSR_SUPDATE | DMACSR_ENABLE); 155 156 if (state) { 157 next_dma_print(nd); 158 panic("DMA did not reset\n"); 159 } 160 } 161 #endif 162 } 163 164 void 165 nextdma_reset(nd) 166 struct nextdma_config *nd; 167 { 168 int s; 169 s = spldma(); /* @@@ should this be splimp()? */ 170 nextdma_init(nd); 171 splx(s); 172 } 173 174 /****************************************************************/ 175 176 /* If the next had multiple busses, this should probably 177 * go elsewhere, but it is here anyway */ 178 void 179 next_dmamap_sync(t, map, offset, len, ops) 180 bus_dma_tag_t t; 181 bus_dmamap_t map; 182 bus_addr_t offset; 183 bus_size_t len; 184 int ops; 185 { 186 /* flush/purge the cache. 187 * assumes pointers are aligned 188 * should probably be fixed to use offset and len 189 */ 190 if (ops & BUS_DMASYNC_PREWRITE) { 191 int i; 192 for(i=0;i<map->dm_nsegs;i++) { 193 bus_addr_t p = map->dm_segs[i].ds_addr; 194 bus_addr_t e = p+map->dm_segs[i].ds_len; 195 while(p<e) { 196 DCFL(p); /* flush */ 197 p += 16; /* cache line length */ 198 } 199 } 200 } 201 202 if (ops & BUS_DMASYNC_POSTREAD) { 203 int i; 204 for(i=0;i<map->dm_nsegs;i++) { 205 bus_addr_t p = map->dm_segs[i].ds_addr; 206 bus_addr_t e = p+map->dm_segs[i].ds_len; 207 while(p<e) { 208 DCPL(p); /* purge */ 209 p += 16; /* cache line length */ 210 } 211 } 212 } 213 } 214 215 /****************************************************************/ 216 217 218 /* Call the completed and continue callbacks to try to fill 219 * in the dma continue buffers. 220 */ 221 void 222 next_dma_rotate(nd) 223 struct nextdma_config *nd; 224 { 225 226 DPRINTF(("DMA next_dma_rotate()\n")); 227 228 /* If we've reached the end of the current map, then inform 229 * that we've completed that map. 230 */ 231 if (nd->_nd_map && ((nd->_nd_idx+1) == nd->_nd_map->dm_nsegs)) { 232 if (nd->nd_completed_cb) 233 (*nd->nd_completed_cb)(nd->_nd_map, nd->nd_cb_arg); 234 } 235 236 /* Rotate the continue map into the current map */ 237 nd->_nd_map = nd->_nd_map_cont; 238 nd->_nd_idx = nd->_nd_idx_cont; 239 240 if ((!nd->_nd_map_cont) || 241 ((nd->_nd_map_cont) && 242 (++nd->_nd_idx_cont >= nd->_nd_map_cont->dm_nsegs))) { 243 if (nd->nd_continue_cb) { 244 nd->_nd_map_cont = (*nd->nd_continue_cb)(nd->nd_cb_arg); 245 } else { 246 nd->_nd_map_cont = 0; 247 } 248 nd->_nd_idx_cont = 0; 249 } 250 } 251 252 void 253 next_dma_setup_cont_regs(nd) 254 struct nextdma_config *nd; 255 { 256 DPRINTF(("DMA next_dma_setup_regs()\n")); 257 258 if (nd->_nd_map_cont) { 259 260 if (nd->nd_intr == NEXT_I_ENETX_DMA) { 261 /* Ethernet transmit needs secret magic */ 262 263 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_START, 264 nd->_nd_map_cont->dm_segs[nd->_nd_idx_cont].ds_addr); 265 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_STOP, 266 ((nd->_nd_map_cont->dm_segs[nd->_nd_idx_cont].ds_addr + 267 nd->_nd_map_cont->dm_segs[nd->_nd_idx_cont].ds_len) 268 + 0x0) | 0x80000000); 269 } else { 270 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_START, 271 nd->_nd_map_cont->dm_segs[nd->_nd_idx_cont].ds_addr); 272 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_STOP, 273 nd->_nd_map_cont->dm_segs[nd->_nd_idx_cont].ds_addr + 274 nd->_nd_map_cont->dm_segs[nd->_nd_idx_cont].ds_len); 275 } 276 277 } else { 278 279 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_START,0); 280 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_STOP, 0); 281 } 282 283 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_START, 284 bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_START)); 285 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_STOP, 286 bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_STOP)); 287 288 } 289 290 void 291 next_dma_setup_curr_regs(nd) 292 struct nextdma_config *nd; 293 { 294 DPRINTF(("DMA next_dma_setup_curr_regs()\n")); 295 296 if (nd->nd_intr == NEXT_I_ENETX_DMA) { 297 /* Ethernet transmit needs secret magic */ 298 299 if (nd->_nd_map) { 300 301 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_NEXT_INITBUF, 302 nd->_nd_map->dm_segs[nd->_nd_idx].ds_addr); 303 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_LIMIT, 304 ((nd->_nd_map->dm_segs[nd->_nd_idx].ds_addr + 305 nd->_nd_map->dm_segs[nd->_nd_idx].ds_len) 306 + 0x0) | 0x80000000); 307 } else { 308 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_NEXT_INITBUF,0); 309 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_LIMIT, 0); 310 311 } 312 313 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_NEXT, 314 bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_NEXT_INITBUF)); 315 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_LIMIT, 316 bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_LIMIT)); 317 318 } else { 319 320 if (nd->_nd_map) { 321 322 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_NEXT, 323 nd->_nd_map->dm_segs[nd->_nd_idx].ds_addr); 324 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_LIMIT, 325 nd->_nd_map->dm_segs[nd->_nd_idx].ds_addr + 326 nd->_nd_map->dm_segs[nd->_nd_idx].ds_len); 327 } else { 328 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_NEXT,0); 329 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_LIMIT, 0); 330 331 } 332 333 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_NEXT, 334 bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_NEXT)); 335 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_LIMIT, 336 bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_LIMIT)); 337 338 } 339 340 } 341 342 343 /* This routine is used for debugging */ 344 345 void 346 next_dma_print(nd) 347 struct nextdma_config *nd; 348 { 349 u_long dd_csr; 350 u_long dd_next; 351 u_long dd_next_initbuf; 352 u_long dd_limit; 353 u_long dd_start; 354 u_long dd_stop; 355 u_long dd_saved_next; 356 u_long dd_saved_limit; 357 u_long dd_saved_start; 358 u_long dd_saved_stop; 359 360 /* Read all of the registers before we print anything out, 361 * in case something changes 362 */ 363 dd_csr = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_CSR); 364 dd_next = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_NEXT); 365 dd_next_initbuf = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_NEXT_INITBUF); 366 dd_limit = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_LIMIT); 367 dd_start = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_START); 368 dd_stop = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_STOP); 369 dd_saved_next = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_NEXT); 370 dd_saved_limit = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_LIMIT); 371 dd_saved_start = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_START); 372 dd_saved_stop = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_STOP); 373 374 if (nd->_nd_map) { 375 printf("NDMAP: nd->_nd_map->dm_segs[%d].ds_addr = 0x%08lx\n", 376 nd->_nd_idx,nd->_nd_map->dm_segs[nd->_nd_idx].ds_addr); 377 printf("NDMAP: nd->_nd_map->dm_segs[%d].ds_len = %d\n", 378 nd->_nd_idx,nd->_nd_map->dm_segs[nd->_nd_idx].ds_len); 379 } else { 380 printf("NDMAP: nd->_nd_map = NULL\n"); 381 } 382 if (nd->_nd_map_cont) { 383 printf("NDMAP: nd->_nd_map_cont->dm_segs[%d].ds_addr = 0x%08lx\n", 384 nd->_nd_idx_cont,nd->_nd_map_cont->dm_segs[nd->_nd_idx_cont].ds_addr); 385 printf("NDMAP: nd->_nd_map_cont->dm_segs[%d].ds_len = %d\n", 386 nd->_nd_idx_cont,nd->_nd_map_cont->dm_segs[nd->_nd_idx_cont].ds_len); 387 } else { 388 printf("NDMAP: nd->_nd_map_cont = NULL\n"); 389 } 390 391 printf("NDMAP: dd->dd_csr = 0x%b\n", dd_csr, DMACSR_BITS); 392 printf("NDMAP: dd->dd_saved_next = 0x%08x\n", dd_saved_next); 393 printf("NDMAP: dd->dd_saved_limit = 0x%08x\n", dd_saved_limit); 394 printf("NDMAP: dd->dd_saved_start = 0x%08x\n", dd_saved_start); 395 printf("NDMAP: dd->dd_saved_stop = 0x%08x\n", dd_saved_stop); 396 printf("NDMAP: dd->dd_next = 0x%08x\n", dd_next); 397 printf("NDMAP: dd->dd_next_initbuf = 0x%08x\n", dd_next_initbuf); 398 printf("NDMAP: dd->dd_limit = 0x%08x\n", dd_limit); 399 printf("NDMAP: dd->dd_start = 0x%08x\n", dd_start); 400 printf("NDMAP: dd->dd_stop = 0x%08x\n", dd_stop); 401 402 printf("NDMAP: interrupt ipl (%ld) intr(0x%b)\n", 403 NEXT_I_IPL(nd->nd_intr), NEXT_I_BIT(nd->nd_intr),NEXT_INTR_BITS); 404 } 405 406 /****************************************************************/ 407 408 int 409 nextdma_intr(arg) 410 void *arg; 411 { 412 struct nextdma_config *nd = arg; 413 414 /* @@@ This is bogus, we can't be certain of arg's type 415 * unless the interrupt is for us 416 */ 417 418 if (!INTR_OCCURRED(nd->nd_intr)) return 0; 419 /* Handle dma interrupts */ 420 421 #ifdef DIAGNOSTIC 422 if (nd->nd_intr == NEXT_I_ENETR_DMA) { 423 if (debugernd != nd) { 424 panic("DMA incorrect handling of rx nd->nd_intr"); 425 } 426 } 427 if (nd->nd_intr == NEXT_I_ENETX_DMA) { 428 if (debugexnd != nd) { 429 panic("DMA incorrect handling of tx nd->nd_intr"); 430 } 431 } 432 #endif 433 434 DPRINTF(("DMA interrupt ipl (%ld) intr(0x%b)\n", 435 NEXT_I_IPL(nd->nd_intr), NEXT_I_BIT(nd->nd_intr),NEXT_INTR_BITS)); 436 437 { 438 int state = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_CSR); 439 440 state &= (DMACSR_BUSEXC | DMACSR_COMPLETE | 441 DMACSR_SUPDATE | DMACSR_ENABLE); 442 443 if (state & DMACSR_BUSEXC) { 444 #if 0 /* This bit seems to get set periodically and I don't know why */ 445 next_dma_print(nd); 446 panic("Bus exception in DMA ipl (%ld) intr(0x%b)\n", 447 NEXT_I_IPL(nd->nd_intr), NEXT_I_BIT(nd->nd_intr),NEXT_INTR_BITS); 448 #endif 449 } 450 451 #ifdef DIAGNOSTIC 452 if (!(state & DMACSR_COMPLETE)) { 453 next_dma_print(nd); 454 #if 0 /* This bit doesn't seem to get set every once in a while, 455 * and I don't know why. Let's try treating it as a spurious 456 * interrupt. ie. report it and ignore the interrupt. 457 */ 458 printf("DEBUG: state = 0x%b\n", state,DMACSR_BITS); 459 panic("DMA ipl (%ld) intr(0x%b), DMACSR_COMPLETE not set in intr\n", 460 NEXT_I_IPL(nd->nd_intr), NEXT_I_BIT(nd->nd_intr),NEXT_INTR_BITS); 461 #else 462 printf("DMA ipl (%ld) intr(0x%b), DMACSR_COMPLETE not set in intr\n", 463 NEXT_I_IPL(nd->nd_intr), NEXT_I_BIT(nd->nd_intr),NEXT_INTR_BITS); 464 return(1); 465 #endif 466 } 467 #endif 468 469 /* Set the length of the segment to match actual length. 470 * @@@ is it okay to resize dma segments here? 471 * i should probably ask jason about this. 472 */ 473 if (nd->_nd_map) { 474 475 bus_addr_t next; 476 bus_addr_t limit; 477 478 #if 0 479 if (state & DMACSR_ENABLE) { 480 next = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_NEXT); 481 } else { 482 next = nd->_nd_map->dm_segs[nd->_nd_idx].ds_addr; 483 } 484 #else 485 next = nd->_nd_map->dm_segs[nd->_nd_idx].ds_addr; 486 #endif 487 limit = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_LIMIT); 488 489 if (nd->nd_intr == NEXT_I_ENETX_DMA) { 490 limit &= ~0x80000000; 491 } 492 493 #ifdef DIAGNOSTIC 494 if (next != nd->_nd_map->dm_segs[nd->_nd_idx].ds_addr) { 495 next_dma_print(nd); 496 printf("DEBUG: state = 0x%b\n", state,DMACSR_BITS); 497 498 panic("DMA ipl (%ld) intr(0x%b), unexpected completed address\n", 499 NEXT_I_IPL(nd->nd_intr), NEXT_I_BIT(nd->nd_intr),NEXT_INTR_BITS); 500 } 501 #endif 502 503 /* @@@ I observed a case where DMACSR_ENABLE wasn't set and 504 * DD_SAVED_LIMIT didn't contain the expected limit value. This 505 * should be tested, fixed, and removed. */ 506 507 if (((limit-next) > nd->_nd_map->dm_segs[nd->_nd_idx].ds_len) 508 || (limit-next < 0)) { 509 #if 0 510 next_dma_print(nd); 511 printf("DEBUG: state = 0x%b\n", state,DMACSR_BITS); 512 panic("DMA packlen: next = 0x%08x limit = 0x%08x\n",next,limit); 513 #else 514 DPRINTF(("DMA packlen: next = 0x%08x limit = 0x%08x",next,limit)); 515 #endif 516 517 } else { 518 nd->_nd_map->dm_segs[nd->_nd_idx].ds_len = limit - next; 519 } 520 } 521 522 523 if ((state & DMACSR_ENABLE) == 0) { 524 525 /* Non chaining interrupts shutdown immediately */ 526 if (!nd->nd_chaining_flag) { 527 nd->_nd_map = nd->_nd_map_cont; 528 nd->_nd_idx = nd->_nd_idx_cont; 529 nd->_nd_map_cont = 0; 530 nd->_nd_idx_cont = 0; 531 } 532 533 /* Call the completed callback for the last packet */ 534 if (nd->_nd_map && ((nd->_nd_idx+1) == nd->_nd_map->dm_nsegs)) { 535 if (nd->nd_completed_cb) 536 (*nd->nd_completed_cb)(nd->_nd_map, nd->nd_cb_arg); 537 } 538 nd->_nd_map = 0; 539 nd->_nd_idx = 0; 540 541 if (nd->_nd_map_cont) { 542 DPRINTF(("DMA ipl (%ld) intr(0x%b), restarting\n", 543 NEXT_I_IPL(nd->nd_intr), NEXT_I_BIT(nd->nd_intr),NEXT_INTR_BITS)); 544 545 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_CSR, 546 DMACSR_SETSUPDATE | DMACSR_SETENABLE); 547 548 } else { 549 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_CSR, 550 DMACSR_CLRCOMPLETE | DMACSR_RESET); 551 DPRINTF(("DMA: enable not set w/o continue map, shutting down dma\n")); 552 if (nd->nd_shutdown_cb) (*nd->nd_shutdown_cb)(nd->nd_cb_arg); 553 } 554 555 } else { 556 next_dma_rotate(nd); 557 next_dma_setup_cont_regs(nd); 558 559 if (nd->_nd_map_cont) { 560 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_CSR, 561 DMACSR_SETSUPDATE | DMACSR_CLRCOMPLETE); 562 } else { 563 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_CSR, 564 DMACSR_CLRCOMPLETE); 565 } 566 567 } 568 569 } 570 571 DPRINTF(("DMA exiting interrupt ipl (%ld) intr(0x%b)\n", 572 NEXT_I_IPL(nd->nd_intr), NEXT_I_BIT(nd->nd_intr),NEXT_INTR_BITS)); 573 574 return(1); 575 } 576 577 /* 578 * Check to see if dma has finished for a channel */ 579 int 580 nextdma_finished(nd) 581 struct nextdma_config *nd; 582 { 583 int r; 584 int s; 585 s = spldma(); /* @@@ should this be splimp()? */ 586 r = (nd->_nd_map == NULL) && (nd->_nd_map_cont == NULL); 587 splx(s); 588 return(r); 589 } 590 591 void 592 nextdma_start(nd, dmadir) 593 struct nextdma_config *nd; 594 u_long dmadir; /* DMACSR_READ or DMACSR_WRITE */ 595 { 596 597 #ifdef DIAGNOSTIC 598 if (!nextdma_finished(nd)) { 599 panic("DMA trying to start before previous finished on intr(0x%b)\n", 600 NEXT_I_BIT(nd->nd_intr),NEXT_INTR_BITS); 601 } 602 #endif 603 604 605 DPRINTF(("DMA start (%ld) intr(0x%b)\n", 606 NEXT_I_IPL(nd->nd_intr), NEXT_I_BIT(nd->nd_intr),NEXT_INTR_BITS)); 607 608 #ifdef DIAGNOSTIC 609 if (nd->_nd_map) { 610 next_dma_print(nd); 611 panic("DMA: nextdma_start() with non null map\n"); 612 } 613 if (nd->_nd_map_cont) { 614 next_dma_print(nd); 615 panic("DMA: nextdma_start() with non null continue map\n"); 616 } 617 #endif 618 619 next_dma_rotate(nd); 620 621 #ifdef DIAGNOSTIC 622 if (!nd->_nd_map_cont) { 623 panic("No map available in nextdma_start()"); 624 } 625 if (!DMA_BEGINALIGNED(nd->_nd_map_cont->dm_segs[nd->_nd_idx].ds_addr)) { 626 panic("unaligned begin dma at start\n"); 627 } 628 if (!DMA_ENDALIGNED(nd->_nd_map_cont->dm_segs[nd->_nd_idx].ds_addr + 629 nd->_nd_map_cont->dm_segs[nd->_nd_idx].ds_len)) { 630 panic("unaligned end dma at start\n"); 631 } 632 #endif 633 634 DPRINTF(("DMA initiating DMA %s of %d segments on intr(0x%b)\n", 635 (dmadir == DMACSR_READ ? "read" : "write"), nd->_nd_map_cont->dm_nsegs, 636 NEXT_I_BIT(nd->nd_intr),NEXT_INTR_BITS)); 637 638 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_CSR, 0); 639 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_CSR, 640 DMACSR_INITBUF | DMACSR_RESET | dmadir); 641 642 next_dma_setup_cont_regs(nd); 643 644 /* When starting DMA, we must put the continue map 645 * into the current register. We reset the nd->_nd_map 646 * pointer here to avoid duplicated completed callbacks 647 * for the first buffer. 648 */ 649 nd->_nd_map = nd->_nd_map_cont; 650 nd->_nd_idx = nd->_nd_idx_cont; 651 next_dma_setup_curr_regs(nd); 652 nd->_nd_map = 0; 653 nd->_nd_idx = 0; 654 655 if (nd->nd_chaining_flag) { 656 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_CSR, 657 DMACSR_SETSUPDATE | DMACSR_SETENABLE); 658 } else { 659 bus_space_write_4(nd->nd_bst, nd->nd_bsh, DD_CSR, 660 DMACSR_SETENABLE); 661 } 662 663 } 664
Indexes created Thu Oct 02 01:09:59 GMT 2025