zs.c revision 1.1
1 /* $NetBSD: zs.c,v 1.1 1998/06/09 07:53:05 dbj Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves. 45 */ 46 47 /* This was snarfed from the netbsd sparc/dev/zs.c at version 1.56 48 * and then updated to reflect changes in 1.59 49 * by Darrin B Jewell <jewell (at) mit.edu> Mon Mar 30 20:24:46 1998 50 */ 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/conf.h> 55 #include <sys/device.h> 56 #include <sys/file.h> 57 #include <sys/ioctl.h> 58 #include <sys/kernel.h> 59 #include <sys/proc.h> 60 #include <sys/tty.h> 61 #include <sys/time.h> 62 #include <sys/syslog.h> 63 64 #include <machine/autoconf.h> 65 #include <machine/cpu.h> 66 #include <machine/psl.h> 67 68 #include <dev/cons.h> 69 70 #include <dev/ic/z8530reg.h> 71 #include <machine/z8530var.h> 72 73 #include <next68k/next68k/isr.h> 74 75 #include "zsc.h" /* NZSC */ 76 77 #if (NZSC < 0) 78 #error "No serial controllers?" 79 #endif 80 81 /* 82 * Some warts needed by z8530tty.c - 83 * The default parity REALLY needs to be the same as the PROM uses, 84 * or you can not see messages done with printf during boot-up... 85 */ 86 int zs_def_cflag = (CREAD | CS8 | HUPCL); 87 int zs_major = 12; 88 89 /* 90 * The NeXT provides a 3.686400 MHz clock to the ZS chips. 91 */ 92 #define PCLK (57600*4*16) /* PCLK pin input clock rate */ 93 94 #define ZS_DELAY() delay(2) 95 96 /* The layout of this is hardware-dependent (padding, order). */ 97 struct zschan { 98 volatile u_char zc_csr; /* ctrl,status, and indirect access */ 99 u_char zc_xxx0; 100 volatile u_char zc_data; /* data */ 101 u_char zc_xxx1; 102 }; 103 104 static char *zsaddr[NZSC]; 105 106 /* Flags from cninit() */ 107 static int zs_hwflags[NZSC][2]; 108 109 /* Default speed for each channel */ 110 static int zs_defspeed[NZSC][2] = { 111 { 9600, /* ttya */ 112 9600 }, /* ttyb */ 113 }; 114 115 static u_char zs_init_reg[16] = { 116 0, /* 0: CMD (reset, etc.) */ 117 0, /* 1: No interrupts yet. */ 118 0x18 + NEXT_I_IPL(NEXT_I_SCC), /* 2: IVECT */ 119 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 120 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 121 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 122 0, /* 6: TXSYNC/SYNCLO */ 123 0, /* 7: RXSYNC/SYNCHI */ 124 0, /* 8: alias for data port */ 125 ZSWR9_MASTER_IE, 126 0, /*10: Misc. TX/RX control bits */ 127 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 128 14, /*12: BAUDLO (default=9600) */ 129 0, /*13: BAUDHI (default=9600) */ 130 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 131 ZSWR15_BREAK_IE | ZSWR15_DCD_IE, 132 }; 133 134 static struct zschan * 135 zs_get_chan_addr __P((int zsc_unit, int channel)); 136 137 static struct zschan * 138 zs_get_chan_addr(zs_unit, channel) 139 int zs_unit, channel; 140 { 141 char *addr; 142 struct zschan *zc; 143 144 if (zs_unit >= NZSC) 145 return (NULL); 146 addr = zsaddr[zs_unit]; 147 if (addr == NULL) 148 return (NULL); 149 if (channel == 0) { 150 /* handle the fact the ports are intertwined. */ 151 zc = (struct zschan *)(addr+1); 152 } else { 153 zc = (struct zschan *)(addr); 154 } 155 return (zc); 156 } 157 158 159 /**************************************************************** 160 * Autoconfig 161 ****************************************************************/ 162 163 /* Definition of the driver for autoconfig. */ 164 static int zs_match __P((struct device *, struct cfdata *, void *)); 165 static void zs_attach __P((struct device *, struct device *, void *)); 166 static int zs_print __P((void *, const char *name)); 167 168 extern int zs_getc __P((void *arg)); 169 extern void zs_putc __P((void *arg, int c)); 170 171 struct cfattach zsc_ca = { 172 sizeof(struct zsc_softc), zs_match, zs_attach 173 }; 174 175 extern struct cfdriver zsc_cd; 176 177 /* Interrupt handlers. */ 178 static int zshard __P((void *)); 179 static int zssoft __P((void *)); 180 181 static int zs_get_speed __P((struct zs_chanstate *)); 182 183 184 /* 185 * Is the zs chip present? 186 */ 187 static int 188 zs_match(parent, cf, aux) 189 struct device *parent; 190 struct cfdata *cf; 191 void *aux; 192 { 193 return(1); 194 } 195 196 /* 197 * Attach a found zs. 198 * 199 * USE ROM PROPERTIES port-a-ignore-cd AND port-b-ignore-cd FOR 200 * SOFT CARRIER, AND keyboard PROPERTY FOR KEYBOARD/MOUSE? 201 */ 202 static void 203 zs_attach(parent, self, aux) 204 struct device *parent; 205 struct device *self; 206 void *aux; 207 { 208 209 struct zsc_softc *zsc = (void *) self; 210 struct zsc_attach_args zsc_args; 211 volatile struct zschan *zc; 212 struct zs_chanstate *cs; 213 int s, zs_unit, channel; 214 215 zs_unit = zsc->zsc_dev.dv_unit; 216 217 if (zsaddr[zs_unit] == NULL) 218 panic("zs_attach: zs%d not mapped\n", zs_unit); 219 220 /* 221 * Initialize software state for each channel. 222 */ 223 for (channel = 0; channel < 2; channel++) { 224 zsc_args.channel = channel; 225 zsc_args.hwflags = zs_hwflags[zs_unit][channel]; 226 cs = &zsc->zsc_cs_store[channel]; 227 zsc->zsc_cs[channel] = cs; 228 229 cs->cs_channel = channel; 230 cs->cs_private = NULL; 231 cs->cs_ops = &zsops_null; 232 cs->cs_brg_clk = PCLK / 16; 233 234 zc = zs_get_chan_addr(zs_unit, channel); 235 cs->cs_reg_csr = &zc->zc_csr; 236 cs->cs_reg_data = &zc->zc_data; 237 238 bcopy(zs_init_reg, cs->cs_creg, 16); 239 bcopy(zs_init_reg, cs->cs_preg, 16); 240 241 /* XXX: Get these from the PROM properties! */ 242 /* XXX: See the mvme167 code. Better. */ 243 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) 244 cs->cs_defspeed = zs_get_speed(cs); 245 else 246 cs->cs_defspeed = zs_defspeed[zs_unit][channel]; 247 cs->cs_defcflag = zs_def_cflag; 248 249 /* Make these correspond to cs_defcflag (-crtscts) */ 250 cs->cs_rr0_dcd = ZSRR0_DCD; 251 cs->cs_rr0_cts = 0; 252 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 253 cs->cs_wr5_rts = 0; 254 255 /* 256 * Clear the master interrupt enable. 257 * The INTENA is common to both channels, 258 * so just do it on the A channel. 259 */ 260 if (channel == 0) { 261 zs_write_reg(cs, 9, 0); 262 } 263 264 /* 265 * Look for a child driver for this channel. 266 * The child attach will setup the hardware. 267 */ 268 if (!config_found(self, (void *)&zsc_args, zs_print)) { 269 /* No sub-driver. Just reset it. */ 270 u_char reset = (channel == 0) ? 271 ZSWR9_A_RESET : ZSWR9_B_RESET; 272 s = splzs(); 273 zs_write_reg(cs, 9, reset); 274 splx(s); 275 } 276 } 277 278 isrlink_autovec(zshard, NULL, NEXT_I_IPL(NEXT_I_SCC), 0); 279 INTR_ENABLE(NEXT_I_SCC); 280 281 { 282 int sir; 283 sir = allocate_sir(zssoft, zsc); 284 if (sir != SIR_SERIAL) { 285 panic("Unexpected zssoft sir"); 286 } 287 } 288 289 /* 290 * Set the master interrupt enable and interrupt vector. 291 * (common to both channels, do it on A) 292 */ 293 cs = zsc->zsc_cs[0]; 294 s = splhigh(); 295 /* interrupt vector */ 296 zs_write_reg(cs, 2, zs_init_reg[2]); 297 /* master interrupt control (enable) */ 298 zs_write_reg(cs, 9, zs_init_reg[9]); 299 splx(s); 300 301 } 302 303 static int 304 zs_print(aux, name) 305 void *aux; 306 const char *name; 307 { 308 struct zsc_attach_args *args = aux; 309 310 if (name != NULL) 311 printf("%s: ", name); 312 313 if (args->channel != -1) 314 printf(" channel %d", args->channel); 315 316 return (UNCONF); 317 } 318 319 static volatile int zssoftpending; 320 321 /* 322 * Our ZS chips all share a common, autovectored interrupt, 323 * so we have to look at all of them on each interrupt. 324 */ 325 static int 326 zshard(arg) 327 void *arg; 328 { 329 register struct zsc_softc *zsc; 330 register int unit, rr3, rval, softreq; 331 if (!INTR_OCCURRED(NEXT_I_SCC)) return 0; 332 333 rval = softreq = 0; 334 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 335 zsc = zsc_cd.cd_devs[unit]; 336 if (zsc == NULL) 337 continue; 338 rr3 = zsc_intr_hard(zsc); 339 /* Count up the interrupts. */ 340 if (rr3) { 341 rval |= rr3; 342 zsc->zsc_intrcnt.ev_count++; 343 } 344 softreq |= zsc->zsc_cs[0]->cs_softreq; 345 softreq |= zsc->zsc_cs[1]->cs_softreq; 346 } 347 348 /* We are at splzs here, so no need to lock. */ 349 if (softreq && (zssoftpending == 0)) { 350 zssoftpending = 1; 351 setsoftserial(); 352 } 353 return(1); 354 } 355 356 /* 357 * Similar scheme as for zshard (look at all of them) 358 */ 359 static int 360 zssoft(arg) 361 void *arg; 362 { 363 register struct zsc_softc *zsc; 364 register int s, unit; 365 366 /* This is not the only ISR on this IPL. */ 367 if (zssoftpending == 0) 368 return (0); 369 370 /* 371 * The soft intr. bit will be set by zshard only if 372 * the variable zssoftpending is zero. The order of 373 * these next two statements prevents our clearing 374 * the soft intr bit just after zshard has set it. 375 */ 376 /* ienab_bic(IE_ZSSOFT); */ 377 zssoftpending = 0; 378 379 /* Make sure we call the tty layer at spltty. */ 380 s = spltty(); 381 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 382 zsc = zsc_cd.cd_devs[unit]; 383 if (zsc == NULL) 384 continue; 385 (void)zsc_intr_soft(zsc); 386 } 387 splx(s); 388 return (1); 389 } 390 391 392 /* 393 * Compute the current baud rate given a ZS channel. 394 */ 395 static int 396 zs_get_speed(cs) 397 struct zs_chanstate *cs; 398 { 399 int tconst; 400 401 tconst = zs_read_reg(cs, 12); 402 tconst |= zs_read_reg(cs, 13) << 8; 403 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 404 } 405 406 /* 407 * MD functions for setting the baud rate and control modes. 408 */ 409 int 410 zs_set_speed(cs, bps) 411 struct zs_chanstate *cs; 412 int bps; /* bits per second */ 413 { 414 int tconst, real_bps; 415 416 if (bps == 0) 417 return (0); 418 419 #ifdef DIAGNOSTIC 420 if (cs->cs_brg_clk == 0) 421 panic("zs_set_speed"); 422 #endif 423 424 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 425 if (tconst < 0) 426 return (EINVAL); 427 428 /* Convert back to make sure we can do it. */ 429 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 430 431 /* XXX - Allow some tolerance here? */ 432 if (real_bps != bps) 433 return (EINVAL); 434 435 cs->cs_preg[12] = tconst; 436 cs->cs_preg[13] = tconst >> 8; 437 438 /* Caller will stuff the pending registers. */ 439 return (0); 440 } 441 442 int 443 zs_set_modes(cs, cflag) 444 struct zs_chanstate *cs; 445 int cflag; /* bits per second */ 446 { 447 int s; 448 449 /* 450 * Output hardware flow control on the chip is horrendous: 451 * if carrier detect drops, the receiver is disabled, and if 452 * CTS drops, the transmitter is stoped IN MID CHARACTER! 453 * Therefore, NEVER set the HFC bit, and instead use the 454 * status interrupt to detect CTS changes. 455 */ 456 s = splzs(); 457 if ((cflag & (CLOCAL | MDMBUF)) != 0) 458 cs->cs_rr0_dcd = 0; 459 else 460 cs->cs_rr0_dcd = ZSRR0_DCD; 461 if ((cflag & CRTSCTS) != 0) { 462 cs->cs_wr5_dtr = ZSWR5_DTR; 463 cs->cs_wr5_rts = ZSWR5_RTS; 464 cs->cs_rr0_cts = ZSRR0_CTS; 465 } else if ((cflag & CDTRCTS) != 0) { 466 cs->cs_wr5_dtr = 0; 467 cs->cs_wr5_rts = ZSWR5_DTR; 468 cs->cs_rr0_cts = ZSRR0_CTS; 469 } else if ((cflag & MDMBUF) != 0) { 470 cs->cs_wr5_dtr = 0; 471 cs->cs_wr5_rts = ZSWR5_DTR; 472 cs->cs_rr0_cts = ZSRR0_DCD; 473 } else { 474 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 475 cs->cs_wr5_rts = 0; 476 cs->cs_rr0_cts = 0; 477 } 478 splx(s); 479 480 /* Caller will stuff the pending registers. */ 481 return (0); 482 } 483 484 /* 485 * Read or write the chip with suitable delays. 486 */ 487 488 u_char 489 zs_read_reg(cs, reg) 490 struct zs_chanstate *cs; 491 u_char reg; 492 { 493 u_char val; 494 495 *cs->cs_reg_csr = reg; 496 ZS_DELAY(); 497 val = *cs->cs_reg_csr; 498 ZS_DELAY(); 499 return (val); 500 } 501 502 void 503 zs_write_reg(cs, reg, val) 504 struct zs_chanstate *cs; 505 u_char reg, val; 506 { 507 *cs->cs_reg_csr = reg; 508 ZS_DELAY(); 509 *cs->cs_reg_csr = val; 510 ZS_DELAY(); 511 } 512 513 u_char 514 zs_read_csr(cs) 515 struct zs_chanstate *cs; 516 { 517 register u_char val; 518 519 val = *cs->cs_reg_csr; 520 ZS_DELAY(); 521 return (val); 522 } 523 524 void zs_write_csr(cs, val) 525 struct zs_chanstate *cs; 526 u_char val; 527 { 528 *cs->cs_reg_csr = val; 529 ZS_DELAY(); 530 } 531 532 u_char zs_read_data(cs) 533 struct zs_chanstate *cs; 534 { 535 register u_char val; 536 537 val = *cs->cs_reg_data; 538 ZS_DELAY(); 539 return (val); 540 } 541 542 void zs_write_data(cs, val) 543 struct zs_chanstate *cs; 544 u_char val; 545 { 546 *cs->cs_reg_data = val; 547 ZS_DELAY(); 548 } 549 550 /**************************************************************** 551 * Console support functions (Sun specific!) 552 * Note: this code is allowed to know about the layout of 553 * the chip registers, and uses that to keep things simple. 554 * XXX - I think I like the mvme167 code better. -gwr 555 ****************************************************************/ 556 557 extern void Debugger __P((void)); 558 void *zs_conschan; 559 int zs_consunit = 0; 560 561 /* 562 * Handle user request to enter kernel debugger. 563 */ 564 void 565 zs_abort(cs) 566 struct zs_chanstate *cs; 567 { 568 register volatile struct zschan *zc = zs_conschan; 569 int rr0; 570 571 /* Wait for end of break to avoid PROM abort. */ 572 /* XXX - Limit the wait? */ 573 do { 574 rr0 = zc->zc_csr; 575 ZS_DELAY(); 576 } while (rr0 & ZSRR0_BREAK); 577 578 #if defined(KGDB) 579 zskgdb(cs); 580 #elif defined(DDB) 581 next68k_isr_printcounts(); 582 Debugger(); 583 #else 584 printf("stopping on keyboard abort\n"); 585 callrom(); 586 #endif 587 } 588 589 /* 590 * Polled input char. 591 */ 592 int 593 zs_getc(arg) 594 void *arg; 595 { 596 register volatile struct zschan *zc = arg; 597 register int s, c, rr0; 598 599 s = splhigh(); 600 /* Wait for a character to arrive. */ 601 do { 602 rr0 = zc->zc_csr; 603 ZS_DELAY(); 604 } while ((rr0 & ZSRR0_RX_READY) == 0); 605 606 c = zc->zc_data; 607 ZS_DELAY(); 608 splx(s); 609 610 /* 611 * This is used by the kd driver to read scan codes, 612 * so don't translate '\r' ==> '\n' here... 613 */ 614 return (c); 615 } 616 617 /* 618 * Polled output char. 619 */ 620 void 621 zs_putc(arg, c) 622 void *arg; 623 int c; 624 { 625 register volatile struct zschan *zc = arg; 626 register int s, rr0; 627 628 s = splhigh(); 629 /* Wait for transmitter to become ready. */ 630 do { 631 rr0 = zc->zc_csr; 632 ZS_DELAY(); 633 } while ((rr0 & ZSRR0_TX_READY) == 0); 634 635 636 zc->zc_data = c; 637 ZS_DELAY(); 638 639 splx(s); 640 } 641 642 /*****************************************************************/ 643 644 void zscninit __P((struct consdev *)); 645 int zscngetc __P((dev_t)); 646 void zscnputc __P((dev_t, int)); 647 void zscnprobe __P((struct consdev *)); 648 extern int zsopen __P(( dev_t dev, int flags, int mode, struct proc *p)); 649 650 void 651 zscnprobe(cp) 652 struct consdev * cp; 653 { 654 int maj; 655 for (maj = 0; maj < nchrdev; maj++) { 656 if (cdevsw[maj].d_open == zsopen) { 657 break; 658 } 659 } 660 if (maj != nchrdev) { 661 cp->cn_pri = CN_NORMAL; /* Lower than CN_INTERNAL */ 662 zs_major = maj; 663 zs_consunit = 0; 664 zsaddr[0] = (void *)IIOV(NEXT_P_SCC); 665 cp->cn_dev = makedev(maj, zs_consunit); 666 zs_conschan = zs_get_chan_addr(0, zs_consunit); 667 } else { 668 cp->cn_pri = CN_DEAD; 669 } 670 } 671 672 673 void 674 zscninit(cn) 675 struct consdev *cn; 676 { 677 zs_hwflags[0][zs_consunit] = ZS_HWFLAG_CONSOLE; 678 679 { 680 struct zs_chanstate xcs; 681 struct zs_chanstate *cs; 682 volatile struct zschan *zc; 683 int tconst, s; 684 685 /* Setup temporary chanstate. */ 686 bzero((caddr_t)&xcs, sizeof(xcs)); 687 cs = &xcs; 688 zc = zs_conschan; 689 cs->cs_reg_csr = &zc->zc_csr; 690 cs->cs_reg_data = &zc->zc_data; 691 cs->cs_channel = zs_consunit; 692 cs->cs_brg_clk = PCLK/16; 693 694 bcopy(zs_init_reg, cs->cs_preg, 16); 695 cs->cs_preg[5] |= ZSWR5_DTR | ZSWR5_RTS; 696 cs->cs_preg[15] = ZSWR15_BREAK_IE; 697 698 tconst = BPS_TO_TCONST(cs->cs_brg_clk, 699 zs_defspeed[0][zs_consunit]); 700 cs->cs_preg[12] = tconst; 701 cs->cs_preg[13] = tconst >> 8; 702 /* can't use zs_set_speed as we haven't set up the 703 * signal sources, and it's not worth it for now 704 */ 705 706 cs->cs_preg[9] &= ~ZSWR9_MASTER_IE; 707 /* no interrupts until later, after attach. */ 708 709 s = splhigh(); 710 zs_loadchannelregs(cs); 711 splx(s); 712 } 713 714 printf("\nNetBSD/next68k console\n"); 715 } 716 717 /* 718 * Polled console input putchar. 719 */ 720 int 721 zscngetc(dev) 722 dev_t dev; 723 { 724 return (zs_getc(zs_conschan)); 725 } 726 727 /* 728 * Polled console output putchar. 729 */ 730 void 731 zscnputc(dev, c) 732 dev_t dev; 733 int c; 734 { 735 zs_putc(zs_conschan, c); 736 } 737 738 /*****************************************************************/ 739
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