zs.c revision 1.12
1 /* $NetBSD: zs.c,v 1.12 2000/03/06 04:14:15 deberg Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves. 45 */ 46 47 /* This was snarfed from the netbsd sparc/dev/zs.c at version 1.56 48 * and then updated to reflect changes in 1.59 49 * by Darrin B Jewell <jewell (at) mit.edu> Mon Mar 30 20:24:46 1998 50 */ 51 52 #include "opt_ddb.h" 53 #include "opt_serial.h" 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/conf.h> 58 #include <sys/device.h> 59 #include <sys/file.h> 60 #include <sys/ioctl.h> 61 #include <sys/kernel.h> 62 #include <sys/proc.h> 63 #include <sys/tty.h> 64 #include <sys/time.h> 65 #include <sys/syslog.h> 66 67 #include <machine/autoconf.h> 68 #include <machine/cpu.h> 69 #include <machine/psl.h> 70 71 #include <dev/cons.h> 72 73 #include <dev/ic/z8530reg.h> 74 #include <machine/z8530var.h> 75 76 #include <next68k/next68k/isr.h> 77 #include <next68k/dev/zs_cons.h> 78 79 #include "zsc.h" /* NZSC */ 80 81 #if (NZSC < 0) 82 #error "No serial controllers?" 83 #endif 84 85 /* 86 * Some warts needed by z8530tty.c - 87 * The default parity REALLY needs to be the same as the PROM uses, 88 * or you can not see messages done with printf during boot-up... 89 */ 90 int zs_def_cflag = (CREAD | CS8 | HUPCL); 91 int zs_major = 12; 92 93 /* 94 * The NeXT provides a 3.686400 MHz clock to the ZS chips. 95 */ 96 #if 1 97 #define PCLK (9600 * 384) /* PCLK pin input clock rate */ 98 #else 99 #define PCLK 10000000 100 #endif 101 102 #define ZS_DELAY() delay(2) 103 104 /* The layout of this is hardware-dependent (padding, order). */ 105 struct zschan { 106 volatile u_char zc_csr; /* ctrl,status, and indirect access */ 107 u_char zc_xxx0; 108 volatile u_char zc_data; /* data */ 109 u_char zc_xxx1; 110 }; 111 112 static char *zsaddr[NZSC]; 113 114 /* Flags from cninit() */ 115 static int zs_hwflags[NZSC][2]; 116 117 /* Default speed for each channel */ 118 static int zs_defspeed[NZSC][2] = { 119 { 9600, /* ttya */ 120 9600 }, /* ttyb */ 121 }; 122 123 static u_char zs_init_reg[16] = { 124 0, /* 0: CMD (reset, etc.) */ 125 0, /* 1: No interrupts yet. */ 126 0x18 + NEXT_I_IPL(NEXT_I_SCC), /* 2: IVECT */ 127 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 128 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 129 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 130 0, /* 6: TXSYNC/SYNCLO */ 131 0, /* 7: RXSYNC/SYNCHI */ 132 0, /* 8: alias for data port */ 133 ZSWR9_MASTER_IE, 134 0, /*10: Misc. TX/RX control bits */ 135 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 136 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */ 137 0, /*13: BAUDHI (default=9600) */ 138 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 139 ZSWR15_BREAK_IE, 140 }; 141 142 struct zschan * 143 zs_get_chan_addr(zs_unit, channel) 144 int zs_unit, channel; 145 { 146 char *addr; 147 struct zschan *zc; 148 149 if (zs_unit >= NZSC) 150 return (NULL); 151 addr = zsaddr[zs_unit]; 152 if (addr == NULL) 153 return (NULL); 154 if (channel == 0) { 155 /* handle the fact the ports are intertwined. */ 156 zc = (struct zschan *)(addr+1); 157 } else { 158 zc = (struct zschan *)(addr); 159 } 160 return (zc); 161 } 162 163 164 /**************************************************************** 165 * Autoconfig 166 ****************************************************************/ 167 168 /* Definition of the driver for autoconfig. */ 169 static int zs_match __P((struct device *, struct cfdata *, void *)); 170 static void zs_attach __P((struct device *, struct device *, void *)); 171 static int zs_print __P((void *, const char *name)); 172 173 extern int zs_getc __P((void *arg)); 174 extern void zs_putc __P((void *arg, int c)); 175 176 struct cfattach zsc_ca = { 177 sizeof(struct zsc_softc), zs_match, zs_attach 178 }; 179 180 extern struct cfdriver zsc_cd; 181 182 /* Interrupt handlers. */ 183 static int zshard __P((void *)); 184 static int zssoft __P((void *)); 185 186 static int zs_get_speed __P((struct zs_chanstate *)); 187 188 189 /* 190 * Is the zs chip present? 191 */ 192 static int 193 zs_match(parent, cf, aux) 194 struct device *parent; 195 struct cfdata *cf; 196 void *aux; 197 { 198 return(1); 199 } 200 201 /* 202 * Attach a found zs. 203 * 204 * USE ROM PROPERTIES port-a-ignore-cd AND port-b-ignore-cd FOR 205 * SOFT CARRIER, AND keyboard PROPERTY FOR KEYBOARD/MOUSE? 206 */ 207 static void 208 zs_attach(parent, self, aux) 209 struct device *parent; 210 struct device *self; 211 void *aux; 212 { 213 struct zsc_softc *zsc = (void *) self; 214 struct zsc_attach_args zsc_args; 215 volatile struct zschan *zc; 216 struct zs_chanstate *cs; 217 int s, zs_unit, channel; 218 219 printf("\n"); 220 221 zs_unit = zsc->zsc_dev.dv_unit; 222 223 if (zsaddr[zs_unit] == NULL) 224 panic("zs_attach: zs%d not mapped\n", zs_unit); 225 226 /* 227 * Initialize software state for each channel. 228 */ 229 for (channel = 0; channel < 2; channel++) { 230 zsc_args.channel = channel; 231 zsc_args.hwflags = zs_hwflags[zs_unit][channel]; 232 cs = &zsc->zsc_cs_store[channel]; 233 zsc->zsc_cs[channel] = cs; 234 235 cs->cs_channel = channel; 236 cs->cs_private = NULL; 237 cs->cs_ops = &zsops_null; 238 cs->cs_brg_clk = PCLK / 16; 239 240 zc = zs_get_chan_addr(zs_unit, channel); 241 cs->cs_reg_csr = &zc->zc_csr; 242 cs->cs_reg_data = &zc->zc_data; 243 244 bcopy(zs_init_reg, cs->cs_creg, 16); 245 bcopy(zs_init_reg, cs->cs_preg, 16); 246 247 /* XXX: Get these from the PROM properties! */ 248 /* XXX: See the mvme167 code. Better. */ 249 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) 250 cs->cs_defspeed = zs_get_speed(cs); 251 else 252 cs->cs_defspeed = zs_defspeed[zs_unit][channel]; 253 cs->cs_defcflag = zs_def_cflag; 254 255 /* Make these correspond to cs_defcflag (-crtscts) */ 256 cs->cs_rr0_dcd = ZSRR0_DCD; 257 cs->cs_rr0_cts = 0; 258 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 259 cs->cs_wr5_rts = 0; 260 261 /* 262 * Clear the master interrupt enable. 263 * The INTENA is common to both channels, 264 * so just do it on the A channel. 265 */ 266 if (channel == 0) { 267 zs_write_reg(cs, 9, 0); 268 } 269 270 /* 271 * Look for a child driver for this channel. 272 * The child attach will setup the hardware. 273 */ 274 if (!config_found(self, (void *)&zsc_args, zs_print)) { 275 /* No sub-driver. Just reset it. */ 276 u_char reset = (channel == 0) ? 277 ZSWR9_A_RESET : ZSWR9_B_RESET; 278 s = splzs(); 279 zs_write_reg(cs, 9, reset); 280 splx(s); 281 } 282 } 283 284 isrlink_autovec(zshard, NULL, NEXT_I_IPL(NEXT_I_SCC), 0); 285 INTR_ENABLE(NEXT_I_SCC); 286 287 { 288 int sir; 289 sir = allocate_sir(zssoft, zsc); 290 if (sir != SIR_SERIAL) { 291 panic("Unexpected zssoft sir"); 292 } 293 } 294 295 /* 296 * Set the master interrupt enable and interrupt vector. 297 * (common to both channels, do it on A) 298 */ 299 cs = zsc->zsc_cs[0]; 300 s = splhigh(); 301 /* interrupt vector */ 302 zs_write_reg(cs, 2, zs_init_reg[2]); 303 /* master interrupt control (enable) */ 304 zs_write_reg(cs, 9, zs_init_reg[9]); 305 splx(s); 306 } 307 308 static int 309 zs_print(aux, name) 310 void *aux; 311 const char *name; 312 { 313 struct zsc_attach_args *args = aux; 314 315 if (name != NULL) 316 printf("%s: ", name); 317 318 if (args->channel != -1) 319 printf(" channel %d", args->channel); 320 321 return (UNCONF); 322 } 323 324 static volatile int zssoftpending; 325 326 /* 327 * Our ZS chips all share a common, autovectored interrupt, 328 * so we have to look at all of them on each interrupt. 329 */ 330 static int 331 zshard(arg) 332 void *arg; 333 { 334 register struct zsc_softc *zsc; 335 register int unit, rr3, rval, softreq; 336 if (!INTR_OCCURRED(NEXT_I_SCC)) return 0; 337 338 rval = softreq = 0; 339 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 340 zsc = zsc_cd.cd_devs[unit]; 341 if (zsc == NULL) 342 continue; 343 rr3 = zsc_intr_hard(zsc); 344 /* Count up the interrupts. */ 345 if (rr3) { 346 rval |= rr3; 347 zsc->zsc_intrcnt.ev_count++; 348 } 349 softreq |= zsc->zsc_cs[0]->cs_softreq; 350 softreq |= zsc->zsc_cs[1]->cs_softreq; 351 } 352 353 /* We are at splzs here, so no need to lock. */ 354 if (softreq && (zssoftpending == 0)) { 355 zssoftpending = 1; 356 setsoftserial(); 357 } 358 return(1); 359 } 360 361 /* 362 * Similar scheme as for zshard (look at all of them) 363 */ 364 static int 365 zssoft(arg) 366 void *arg; 367 { 368 register struct zsc_softc *zsc; 369 register int s, unit; 370 371 /* This is not the only ISR on this IPL. */ 372 if (zssoftpending == 0) 373 return (0); 374 375 /* 376 * The soft intr. bit will be set by zshard only if 377 * the variable zssoftpending is zero. The order of 378 * these next two statements prevents our clearing 379 * the soft intr bit just after zshard has set it. 380 */ 381 /* ienab_bic(IE_ZSSOFT); */ 382 zssoftpending = 0; 383 384 /* Make sure we call the tty layer at spltty. */ 385 s = spltty(); 386 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 387 zsc = zsc_cd.cd_devs[unit]; 388 if (zsc == NULL) 389 continue; 390 (void)zsc_intr_soft(zsc); 391 } 392 splx(s); 393 return (1); 394 } 395 396 397 /* 398 * Compute the current baud rate given a ZS channel. 399 */ 400 static int 401 zs_get_speed(cs) 402 struct zs_chanstate *cs; 403 { 404 int tconst; 405 406 tconst = zs_read_reg(cs, 12); 407 tconst |= zs_read_reg(cs, 13) << 8; 408 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 409 } 410 411 /* 412 * MD functions for setting the baud rate and control modes. 413 */ 414 int 415 zs_set_speed(cs, bps) 416 struct zs_chanstate *cs; 417 int bps; /* bits per second */ 418 { 419 int tconst, real_bps; 420 421 if (bps == 0) 422 return (0); 423 424 #ifdef DIAGNOSTIC 425 if (cs->cs_brg_clk == 0) 426 panic("zs_set_speed"); 427 #endif 428 429 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 430 if (tconst < 0) 431 return (EINVAL); 432 433 /* Convert back to make sure we can do it. */ 434 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 435 436 /* XXX - Allow some tolerance here? */ 437 if (real_bps != bps) 438 return (EINVAL); 439 440 cs->cs_preg[12] = tconst; 441 cs->cs_preg[13] = tconst >> 8; 442 443 /* Caller will stuff the pending registers. */ 444 return (0); 445 } 446 447 int 448 zs_set_modes(cs, cflag) 449 struct zs_chanstate *cs; 450 int cflag; /* bits per second */ 451 { 452 int s; 453 454 /* 455 * Output hardware flow control on the chip is horrendous: 456 * if carrier detect drops, the receiver is disabled, and if 457 * CTS drops, the transmitter is stoped IN MID CHARACTER! 458 * Therefore, NEVER set the HFC bit, and instead use the 459 * status interrupt to detect CTS changes. 460 */ 461 s = splzs(); 462 cs->cs_rr0_pps = 0; 463 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 464 cs->cs_rr0_dcd = 0; 465 if ((cflag & MDMBUF) == 0) 466 cs->cs_rr0_pps = ZSRR0_DCD; 467 } else 468 cs->cs_rr0_dcd = ZSRR0_DCD; 469 if ((cflag & CRTSCTS) != 0) { 470 cs->cs_wr5_dtr = ZSWR5_DTR; 471 cs->cs_wr5_rts = ZSWR5_RTS; 472 cs->cs_rr0_cts = ZSRR0_CTS; 473 } else if ((cflag & CDTRCTS) != 0) { 474 cs->cs_wr5_dtr = 0; 475 cs->cs_wr5_rts = ZSWR5_DTR; 476 cs->cs_rr0_cts = ZSRR0_CTS; 477 } else if ((cflag & MDMBUF) != 0) { 478 cs->cs_wr5_dtr = 0; 479 cs->cs_wr5_rts = ZSWR5_DTR; 480 cs->cs_rr0_cts = ZSRR0_DCD; 481 } else { 482 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 483 cs->cs_wr5_rts = 0; 484 cs->cs_rr0_cts = 0; 485 } 486 splx(s); 487 488 /* Caller will stuff the pending registers. */ 489 return (0); 490 } 491 492 /* 493 * Read or write the chip with suitable delays. 494 */ 495 496 u_char 497 zs_read_reg(cs, reg) 498 struct zs_chanstate *cs; 499 u_char reg; 500 { 501 u_char val; 502 503 *cs->cs_reg_csr = reg; 504 ZS_DELAY(); 505 val = *cs->cs_reg_csr; 506 ZS_DELAY(); 507 return (val); 508 } 509 510 void 511 zs_write_reg(cs, reg, val) 512 struct zs_chanstate *cs; 513 u_char reg, val; 514 { 515 *cs->cs_reg_csr = reg; 516 ZS_DELAY(); 517 *cs->cs_reg_csr = val; 518 ZS_DELAY(); 519 } 520 521 u_char 522 zs_read_csr(cs) 523 struct zs_chanstate *cs; 524 { 525 register u_char val; 526 527 val = *cs->cs_reg_csr; 528 ZS_DELAY(); 529 return (val); 530 } 531 532 void zs_write_csr(cs, val) 533 struct zs_chanstate *cs; 534 u_char val; 535 { 536 *cs->cs_reg_csr = val; 537 ZS_DELAY(); 538 } 539 540 u_char zs_read_data(cs) 541 struct zs_chanstate *cs; 542 { 543 register u_char val; 544 545 val = *cs->cs_reg_data; 546 ZS_DELAY(); 547 return (val); 548 } 549 550 void zs_write_data(cs, val) 551 struct zs_chanstate *cs; 552 u_char val; 553 { 554 *cs->cs_reg_data = val; 555 ZS_DELAY(); 556 } 557 558 /**************************************************************** 559 * Console support functions (Sun specific!) 560 * Note: this code is allowed to know about the layout of 561 * the chip registers, and uses that to keep things simple. 562 * XXX - I think I like the mvme167 code better. -gwr 563 ****************************************************************/ 564 565 extern void Debugger __P((void)); 566 void *zs_conschan; 567 int zs_consunit = 0; 568 569 /* 570 * Handle user request to enter kernel debugger. 571 */ 572 void 573 zs_abort(cs) 574 struct zs_chanstate *cs; 575 { 576 #if defined(ZS_CONSOLE_ABORT) 577 register volatile struct zschan *zc = zs_conschan; 578 int rr0; 579 580 /* Wait for end of break to avoid PROM abort. */ 581 /* XXX - Limit the wait? */ 582 do { 583 rr0 = zc->zc_csr; 584 ZS_DELAY(); 585 } while (rr0 & ZSRR0_BREAK); 586 587 #if defined(KGDB) 588 zskgdb(cs); 589 #elif defined(DDB) 590 Debugger(); 591 #else 592 /* XXX eventually, drop into next rom monitor here */ 593 printf("stopping on keyboard abort not supported without DDB or KGDB\n"); 594 #endif 595 #else /* !ZS_CONSOLE_ABORT */ 596 return; 597 #endif 598 } 599 600 /* 601 * Polled input char. 602 */ 603 int 604 zs_getc(arg) 605 void *arg; 606 { 607 register volatile struct zschan *zc = arg; 608 register int s, c, rr0; 609 610 s = splhigh(); 611 /* Wait for a character to arrive. */ 612 do { 613 rr0 = zc->zc_csr; 614 ZS_DELAY(); 615 } while ((rr0 & ZSRR0_RX_READY) == 0); 616 617 c = zc->zc_data; 618 ZS_DELAY(); 619 splx(s); 620 621 /* 622 * This is used by the kd driver to read scan codes, 623 * so don't translate '\r' ==> '\n' here... 624 */ 625 return (c); 626 } 627 628 /* 629 * Polled output char. 630 */ 631 void 632 zs_putc(arg, c) 633 void *arg; 634 int c; 635 { 636 register volatile struct zschan *zc = arg; 637 register int s, rr0; 638 639 s = splhigh(); 640 /* Wait for transmitter to become ready. */ 641 do { 642 rr0 = zc->zc_csr; 643 ZS_DELAY(); 644 } while ((rr0 & ZSRR0_TX_READY) == 0); 645 646 647 zc->zc_data = c; 648 ZS_DELAY(); 649 650 splx(s); 651 } 652 653 /*****************************************************************/ 654 655 void zscninit __P((struct consdev *)); 656 int zscngetc __P((dev_t)); 657 void zscnputc __P((dev_t, int)); 658 void zscnprobe __P((struct consdev *)); 659 extern int zsopen __P(( dev_t dev, int flags, int mode, struct proc *p)); 660 661 void 662 zscnprobe(cp) 663 struct consdev * cp; 664 { 665 int maj; 666 for (maj = 0; maj < nchrdev; maj++) { 667 if (cdevsw[maj].d_open == zsopen) { 668 break; 669 } 670 } 671 if (maj != nchrdev) { 672 #ifdef SERCONSOLE 673 cp->cn_pri = CN_REMOTE; 674 #else 675 cp->cn_pri = CN_NORMAL; /* Lower than CN_INTERNAL */ 676 #endif 677 zs_major = maj; 678 zs_consunit = 0; 679 zsaddr[0] = (void *)IIOV(NEXT_P_SCC); 680 cp->cn_dev = makedev(maj, zs_consunit); 681 zs_conschan = zs_get_chan_addr(0, zs_consunit); 682 } else { 683 cp->cn_pri = CN_DEAD; 684 } 685 } 686 687 688 void 689 zscninit(cn) 690 struct consdev *cn; 691 { 692 zs_hwflags[0][zs_consunit] = ZS_HWFLAG_CONSOLE; 693 694 { 695 struct zs_chanstate xcs; 696 struct zs_chanstate *cs; 697 volatile struct zschan *zc; 698 int tconst, s; 699 700 /* Setup temporary chanstate. */ 701 bzero((caddr_t)&xcs, sizeof(xcs)); 702 cs = &xcs; 703 zc = zs_conschan; 704 cs->cs_reg_csr = &zc->zc_csr; 705 cs->cs_reg_data = &zc->zc_data; 706 cs->cs_channel = zs_consunit; 707 cs->cs_brg_clk = PCLK / 16; 708 709 bcopy(zs_init_reg, cs->cs_preg, 16); 710 cs->cs_preg[5] |= ZSWR5_DTR | ZSWR5_RTS; 711 cs->cs_preg[15] = ZSWR15_BREAK_IE; 712 713 tconst = BPS_TO_TCONST(cs->cs_brg_clk, 714 zs_defspeed[0][zs_consunit]); 715 cs->cs_preg[12] = tconst; 716 cs->cs_preg[13] = tconst >> 8; 717 /* can't use zs_set_speed as we haven't set up the 718 * signal sources, and it's not worth it for now 719 */ 720 721 cs->cs_preg[9] &= ~ZSWR9_MASTER_IE; 722 /* no interrupts until later, after attach. */ 723 724 s = splhigh(); 725 zs_loadchannelregs(cs); 726 splx(s); 727 } 728 729 printf("\nNetBSD/next68k console\n"); 730 } 731 732 /* 733 * Polled console input putchar. 734 */ 735 int 736 zscngetc(dev) 737 dev_t dev; 738 { 739 return (zs_getc(zs_conschan)); 740 } 741 742 /* 743 * Polled console output putchar. 744 */ 745 void 746 zscnputc(dev, c) 747 dev_t dev; 748 int c; 749 { 750 zs_putc(zs_conschan, c); 751 } 752 753 /*****************************************************************/ 754
Indexes created Fri Sep 26 20:09:58 GMT 2025