zs.c revision 1.13
1 /* $NetBSD: zs.c,v 1.13 2001/04/05 05:35:12 dbj Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves. 45 */ 46 47 /* This was snarfed from the netbsd sparc/dev/zs.c at version 1.56 48 * and then updated to reflect changes in 1.59 49 * by Darrin B Jewell <jewell (at) mit.edu> Mon Mar 30 20:24:46 1998 50 */ 51 52 #include "opt_ddb.h" 53 #include "opt_serial.h" 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/conf.h> 58 #include <sys/device.h> 59 #include <sys/file.h> 60 #include <sys/ioctl.h> 61 #include <sys/kernel.h> 62 #include <sys/proc.h> 63 #include <sys/tty.h> 64 #include <sys/time.h> 65 #include <sys/syslog.h> 66 67 #include <machine/autoconf.h> 68 #include <machine/cpu.h> 69 #include <machine/psl.h> 70 71 #include <dev/cons.h> 72 73 #include <dev/ic/z8530reg.h> 74 #include <machine/z8530var.h> 75 76 #include <next68k/next68k/isr.h> 77 #include <next68k/dev/zs_cons.h> 78 79 #include "zsc.h" /* NZSC */ 80 81 #if (NZSC < 0) 82 #error "No serial controllers?" 83 #endif 84 85 /* 86 * Some warts needed by z8530tty.c - 87 * The default parity REALLY needs to be the same as the PROM uses, 88 * or you can not see messages done with printf during boot-up... 89 */ 90 int zs_def_cflag = (CREAD | CS8 | HUPCL); 91 int zs_major = 12; 92 93 /* 94 * The NeXT provides a 3.686400 MHz clock to the ZS chips. 95 */ 96 #if 1 97 #define PCLK (9600 * 384) /* PCLK pin input clock rate */ 98 #else 99 #define PCLK 10000000 100 #endif 101 102 #define ZS_DELAY() delay(2) 103 104 /* The layout of this is hardware-dependent (padding, order). */ 105 struct zschan { 106 volatile u_char zc_csr; /* ctrl,status, and indirect access */ 107 u_char zc_xxx0; 108 volatile u_char zc_data; /* data */ 109 u_char zc_xxx1; 110 }; 111 112 static char *zsaddr[NZSC]; 113 114 /* Flags from cninit() */ 115 static int zs_hwflags[NZSC][2]; 116 117 /* Default speed for each channel */ 118 static int zs_defspeed[NZSC][2] = { 119 { 9600, /* ttya */ 120 9600 }, /* ttyb */ 121 }; 122 123 static u_char zs_init_reg[16] = { 124 0, /* 0: CMD (reset, etc.) */ 125 0, /* 1: No interrupts yet. */ 126 0x18 + NEXT_I_IPL(NEXT_I_SCC), /* 2: IVECT */ 127 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 128 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 129 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 130 0, /* 6: TXSYNC/SYNCLO */ 131 0, /* 7: RXSYNC/SYNCHI */ 132 0, /* 8: alias for data port */ 133 ZSWR9_MASTER_IE, 134 0, /*10: Misc. TX/RX control bits */ 135 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 136 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */ 137 0, /*13: BAUDHI (default=9600) */ 138 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 139 ZSWR15_BREAK_IE, 140 }; 141 142 struct zschan * 143 zs_get_chan_addr(zs_unit, channel) 144 int zs_unit, channel; 145 { 146 char *addr; 147 struct zschan *zc; 148 149 if (zs_unit >= NZSC) 150 return (NULL); 151 addr = zsaddr[zs_unit]; 152 if (addr == NULL) 153 return (NULL); 154 if (channel == 0) { 155 /* handle the fact the ports are intertwined. */ 156 zc = (struct zschan *)(addr+1); 157 } else { 158 zc = (struct zschan *)(addr); 159 } 160 return (zc); 161 } 162 163 164 /**************************************************************** 165 * Autoconfig 166 ****************************************************************/ 167 168 /* Definition of the driver for autoconfig. */ 169 static int zs_match __P((struct device *, struct cfdata *, void *)); 170 static void zs_attach __P((struct device *, struct device *, void *)); 171 static int zs_print __P((void *, const char *name)); 172 173 extern int zs_getc __P((void *arg)); 174 extern void zs_putc __P((void *arg, int c)); 175 176 struct cfattach zsc_ca = { 177 sizeof(struct zsc_softc), zs_match, zs_attach 178 }; 179 180 extern struct cfdriver zsc_cd; 181 182 /* Interrupt handlers. */ 183 static int zshard __P((void *)); 184 static int zssoft __P((void *)); 185 186 static int zs_get_speed __P((struct zs_chanstate *)); 187 188 189 /* 190 * Is the zs chip present? 191 */ 192 static int 193 zs_match(parent, cf, aux) 194 struct device *parent; 195 struct cfdata *cf; 196 void *aux; 197 { 198 return(1); 199 } 200 201 /* 202 * Attach a found zs. 203 * 204 * USE ROM PROPERTIES port-a-ignore-cd AND port-b-ignore-cd FOR 205 * SOFT CARRIER, AND keyboard PROPERTY FOR KEYBOARD/MOUSE? 206 */ 207 static void 208 zs_attach(parent, self, aux) 209 struct device *parent; 210 struct device *self; 211 void *aux; 212 { 213 struct zsc_softc *zsc = (void *) self; 214 struct zsc_attach_args zsc_args; 215 volatile struct zschan *zc; 216 struct zs_chanstate *cs; 217 int s, zs_unit, channel; 218 219 printf("\n"); 220 221 zs_unit = zsc->zsc_dev.dv_unit; 222 223 if (zs_unit == 0) { 224 zsaddr[0] = (void *)IIOV(NEXT_P_SCC); 225 } 226 227 if (zsaddr[zs_unit] == NULL) 228 panic("zs_attach: zs%d not mapped\n", zs_unit); 229 230 /* 231 * Initialize software state for each channel. 232 */ 233 for (channel = 0; channel < 2; channel++) { 234 zsc_args.channel = channel; 235 zsc_args.hwflags = zs_hwflags[zs_unit][channel]; 236 cs = &zsc->zsc_cs_store[channel]; 237 zsc->zsc_cs[channel] = cs; 238 239 cs->cs_channel = channel; 240 cs->cs_private = NULL; 241 cs->cs_ops = &zsops_null; 242 cs->cs_brg_clk = PCLK / 16; 243 244 zc = zs_get_chan_addr(zs_unit, channel); 245 cs->cs_reg_csr = &zc->zc_csr; 246 cs->cs_reg_data = &zc->zc_data; 247 248 bcopy(zs_init_reg, cs->cs_creg, 16); 249 bcopy(zs_init_reg, cs->cs_preg, 16); 250 251 /* XXX: Get these from the PROM properties! */ 252 /* XXX: See the mvme167 code. Better. */ 253 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) 254 cs->cs_defspeed = zs_get_speed(cs); 255 else 256 cs->cs_defspeed = zs_defspeed[zs_unit][channel]; 257 cs->cs_defcflag = zs_def_cflag; 258 259 /* Make these correspond to cs_defcflag (-crtscts) */ 260 cs->cs_rr0_dcd = ZSRR0_DCD; 261 cs->cs_rr0_cts = 0; 262 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 263 cs->cs_wr5_rts = 0; 264 265 /* 266 * Clear the master interrupt enable. 267 * The INTENA is common to both channels, 268 * so just do it on the A channel. 269 */ 270 if (channel == 0) { 271 zs_write_reg(cs, 9, 0); 272 } 273 274 /* 275 * Look for a child driver for this channel. 276 * The child attach will setup the hardware. 277 */ 278 if (!config_found(self, (void *)&zsc_args, zs_print)) { 279 /* No sub-driver. Just reset it. */ 280 u_char reset = (channel == 0) ? 281 ZSWR9_A_RESET : ZSWR9_B_RESET; 282 s = splzs(); 283 zs_write_reg(cs, 9, reset); 284 splx(s); 285 } 286 } 287 288 isrlink_autovec(zshard, NULL, NEXT_I_IPL(NEXT_I_SCC), 0); 289 INTR_ENABLE(NEXT_I_SCC); 290 291 { 292 int sir; 293 sir = allocate_sir(zssoft, zsc); 294 if (sir != SIR_SERIAL) { 295 panic("Unexpected zssoft sir"); 296 } 297 } 298 299 /* 300 * Set the master interrupt enable and interrupt vector. 301 * (common to both channels, do it on A) 302 */ 303 cs = zsc->zsc_cs[0]; 304 s = splhigh(); 305 /* interrupt vector */ 306 zs_write_reg(cs, 2, zs_init_reg[2]); 307 /* master interrupt control (enable) */ 308 zs_write_reg(cs, 9, zs_init_reg[9]); 309 splx(s); 310 } 311 312 static int 313 zs_print(aux, name) 314 void *aux; 315 const char *name; 316 { 317 struct zsc_attach_args *args = aux; 318 319 if (name != NULL) 320 printf("%s: ", name); 321 322 if (args->channel != -1) 323 printf(" channel %d", args->channel); 324 325 return (UNCONF); 326 } 327 328 static volatile int zssoftpending; 329 330 /* 331 * Our ZS chips all share a common, autovectored interrupt, 332 * so we have to look at all of them on each interrupt. 333 */ 334 static int 335 zshard(arg) 336 void *arg; 337 { 338 register struct zsc_softc *zsc; 339 register int unit, rr3, rval, softreq; 340 if (!INTR_OCCURRED(NEXT_I_SCC)) return 0; 341 342 rval = softreq = 0; 343 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 344 zsc = zsc_cd.cd_devs[unit]; 345 if (zsc == NULL) 346 continue; 347 rr3 = zsc_intr_hard(zsc); 348 /* Count up the interrupts. */ 349 if (rr3) { 350 rval |= rr3; 351 zsc->zsc_intrcnt.ev_count++; 352 } 353 softreq |= zsc->zsc_cs[0]->cs_softreq; 354 softreq |= zsc->zsc_cs[1]->cs_softreq; 355 } 356 357 /* We are at splzs here, so no need to lock. */ 358 if (softreq && (zssoftpending == 0)) { 359 zssoftpending = 1; 360 setsoftserial(); 361 } 362 return(1); 363 } 364 365 /* 366 * Similar scheme as for zshard (look at all of them) 367 */ 368 static int 369 zssoft(arg) 370 void *arg; 371 { 372 register struct zsc_softc *zsc; 373 register int s, unit; 374 375 /* This is not the only ISR on this IPL. */ 376 if (zssoftpending == 0) 377 return (0); 378 379 /* 380 * The soft intr. bit will be set by zshard only if 381 * the variable zssoftpending is zero. The order of 382 * these next two statements prevents our clearing 383 * the soft intr bit just after zshard has set it. 384 */ 385 /* ienab_bic(IE_ZSSOFT); */ 386 zssoftpending = 0; 387 388 /* Make sure we call the tty layer at spltty. */ 389 s = spltty(); 390 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 391 zsc = zsc_cd.cd_devs[unit]; 392 if (zsc == NULL) 393 continue; 394 (void)zsc_intr_soft(zsc); 395 } 396 splx(s); 397 return (1); 398 } 399 400 401 /* 402 * Compute the current baud rate given a ZS channel. 403 */ 404 static int 405 zs_get_speed(cs) 406 struct zs_chanstate *cs; 407 { 408 int tconst; 409 410 tconst = zs_read_reg(cs, 12); 411 tconst |= zs_read_reg(cs, 13) << 8; 412 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 413 } 414 415 /* 416 * MD functions for setting the baud rate and control modes. 417 */ 418 int 419 zs_set_speed(cs, bps) 420 struct zs_chanstate *cs; 421 int bps; /* bits per second */ 422 { 423 int tconst, real_bps; 424 425 if (bps == 0) 426 return (0); 427 428 #ifdef DIAGNOSTIC 429 if (cs->cs_brg_clk == 0) 430 panic("zs_set_speed"); 431 #endif 432 433 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 434 if (tconst < 0) 435 return (EINVAL); 436 437 /* Convert back to make sure we can do it. */ 438 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 439 440 /* XXX - Allow some tolerance here? */ 441 if (real_bps != bps) 442 return (EINVAL); 443 444 cs->cs_preg[12] = tconst; 445 cs->cs_preg[13] = tconst >> 8; 446 447 /* Caller will stuff the pending registers. */ 448 return (0); 449 } 450 451 int 452 zs_set_modes(cs, cflag) 453 struct zs_chanstate *cs; 454 int cflag; /* bits per second */ 455 { 456 int s; 457 458 /* 459 * Output hardware flow control on the chip is horrendous: 460 * if carrier detect drops, the receiver is disabled, and if 461 * CTS drops, the transmitter is stoped IN MID CHARACTER! 462 * Therefore, NEVER set the HFC bit, and instead use the 463 * status interrupt to detect CTS changes. 464 */ 465 s = splzs(); 466 cs->cs_rr0_pps = 0; 467 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 468 cs->cs_rr0_dcd = 0; 469 if ((cflag & MDMBUF) == 0) 470 cs->cs_rr0_pps = ZSRR0_DCD; 471 } else 472 cs->cs_rr0_dcd = ZSRR0_DCD; 473 if ((cflag & CRTSCTS) != 0) { 474 cs->cs_wr5_dtr = ZSWR5_DTR; 475 cs->cs_wr5_rts = ZSWR5_RTS; 476 cs->cs_rr0_cts = ZSRR0_CTS; 477 } else if ((cflag & CDTRCTS) != 0) { 478 cs->cs_wr5_dtr = 0; 479 cs->cs_wr5_rts = ZSWR5_DTR; 480 cs->cs_rr0_cts = ZSRR0_CTS; 481 } else if ((cflag & MDMBUF) != 0) { 482 cs->cs_wr5_dtr = 0; 483 cs->cs_wr5_rts = ZSWR5_DTR; 484 cs->cs_rr0_cts = ZSRR0_DCD; 485 } else { 486 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 487 cs->cs_wr5_rts = 0; 488 cs->cs_rr0_cts = 0; 489 } 490 splx(s); 491 492 /* Caller will stuff the pending registers. */ 493 return (0); 494 } 495 496 /* 497 * Read or write the chip with suitable delays. 498 */ 499 500 u_char 501 zs_read_reg(cs, reg) 502 struct zs_chanstate *cs; 503 u_char reg; 504 { 505 u_char val; 506 507 *cs->cs_reg_csr = reg; 508 ZS_DELAY(); 509 val = *cs->cs_reg_csr; 510 ZS_DELAY(); 511 return (val); 512 } 513 514 void 515 zs_write_reg(cs, reg, val) 516 struct zs_chanstate *cs; 517 u_char reg, val; 518 { 519 *cs->cs_reg_csr = reg; 520 ZS_DELAY(); 521 *cs->cs_reg_csr = val; 522 ZS_DELAY(); 523 } 524 525 u_char 526 zs_read_csr(cs) 527 struct zs_chanstate *cs; 528 { 529 register u_char val; 530 531 val = *cs->cs_reg_csr; 532 ZS_DELAY(); 533 return (val); 534 } 535 536 void zs_write_csr(cs, val) 537 struct zs_chanstate *cs; 538 u_char val; 539 { 540 *cs->cs_reg_csr = val; 541 ZS_DELAY(); 542 } 543 544 u_char zs_read_data(cs) 545 struct zs_chanstate *cs; 546 { 547 register u_char val; 548 549 val = *cs->cs_reg_data; 550 ZS_DELAY(); 551 return (val); 552 } 553 554 void zs_write_data(cs, val) 555 struct zs_chanstate *cs; 556 u_char val; 557 { 558 *cs->cs_reg_data = val; 559 ZS_DELAY(); 560 } 561 562 /**************************************************************** 563 * Console support functions (Sun specific!) 564 * Note: this code is allowed to know about the layout of 565 * the chip registers, and uses that to keep things simple. 566 * XXX - I think I like the mvme167 code better. -gwr 567 ****************************************************************/ 568 569 extern void Debugger __P((void)); 570 void *zs_conschan; 571 int zs_consunit = 0; 572 573 /* 574 * Handle user request to enter kernel debugger. 575 */ 576 void 577 zs_abort(cs) 578 struct zs_chanstate *cs; 579 { 580 #if defined(ZS_CONSOLE_ABORT) 581 register volatile struct zschan *zc = zs_conschan; 582 int rr0; 583 584 /* Wait for end of break to avoid PROM abort. */ 585 /* XXX - Limit the wait? */ 586 do { 587 rr0 = zc->zc_csr; 588 ZS_DELAY(); 589 } while (rr0 & ZSRR0_BREAK); 590 591 #if defined(KGDB) 592 zskgdb(cs); 593 #elif defined(DDB) 594 Debugger(); 595 #else 596 /* XXX eventually, drop into next rom monitor here */ 597 printf("stopping on keyboard abort not supported without DDB or KGDB\n"); 598 #endif 599 #else /* !ZS_CONSOLE_ABORT */ 600 return; 601 #endif 602 } 603 604 /* 605 * Polled input char. 606 */ 607 int 608 zs_getc(arg) 609 void *arg; 610 { 611 register volatile struct zschan *zc = arg; 612 register int s, c, rr0; 613 614 s = splhigh(); 615 /* Wait for a character to arrive. */ 616 do { 617 rr0 = zc->zc_csr; 618 ZS_DELAY(); 619 } while ((rr0 & ZSRR0_RX_READY) == 0); 620 621 c = zc->zc_data; 622 ZS_DELAY(); 623 splx(s); 624 625 /* 626 * This is used by the kd driver to read scan codes, 627 * so don't translate '\r' ==> '\n' here... 628 */ 629 return (c); 630 } 631 632 /* 633 * Polled output char. 634 */ 635 void 636 zs_putc(arg, c) 637 void *arg; 638 int c; 639 { 640 register volatile struct zschan *zc = arg; 641 register int s, rr0; 642 643 s = splhigh(); 644 /* Wait for transmitter to become ready. */ 645 do { 646 rr0 = zc->zc_csr; 647 ZS_DELAY(); 648 } while ((rr0 & ZSRR0_TX_READY) == 0); 649 650 651 zc->zc_data = c; 652 ZS_DELAY(); 653 654 splx(s); 655 } 656 657 /*****************************************************************/ 658 659 void zscninit __P((struct consdev *)); 660 int zscngetc __P((dev_t)); 661 void zscnputc __P((dev_t, int)); 662 void zscnprobe __P((struct consdev *)); 663 extern int zsopen __P(( dev_t dev, int flags, int mode, struct proc *p)); 664 665 void 666 zscnprobe(cp) 667 struct consdev * cp; 668 { 669 int maj; 670 for (maj = 0; maj < nchrdev; maj++) { 671 if (cdevsw[maj].d_open == zsopen) { 672 break; 673 } 674 } 675 if (maj != nchrdev) { 676 #ifdef SERCONSOLE 677 cp->cn_pri = CN_REMOTE; 678 #else 679 cp->cn_pri = CN_NORMAL; /* Lower than CN_INTERNAL */ 680 #endif 681 zs_major = maj; 682 zs_consunit = 0; 683 zsaddr[0] = (void *)IIOV(NEXT_P_SCC); 684 cp->cn_dev = makedev(maj, zs_consunit); 685 zs_conschan = zs_get_chan_addr(0, zs_consunit); 686 } else { 687 cp->cn_pri = CN_DEAD; 688 } 689 } 690 691 692 void 693 zscninit(cn) 694 struct consdev *cn; 695 { 696 zs_hwflags[0][zs_consunit] = ZS_HWFLAG_CONSOLE; 697 698 { 699 struct zs_chanstate xcs; 700 struct zs_chanstate *cs; 701 volatile struct zschan *zc; 702 int tconst, s; 703 704 /* Setup temporary chanstate. */ 705 bzero((caddr_t)&xcs, sizeof(xcs)); 706 cs = &xcs; 707 zc = zs_conschan; 708 cs->cs_reg_csr = &zc->zc_csr; 709 cs->cs_reg_data = &zc->zc_data; 710 cs->cs_channel = zs_consunit; 711 cs->cs_brg_clk = PCLK / 16; 712 713 bcopy(zs_init_reg, cs->cs_preg, 16); 714 cs->cs_preg[5] |= ZSWR5_DTR | ZSWR5_RTS; 715 cs->cs_preg[15] = ZSWR15_BREAK_IE; 716 717 tconst = BPS_TO_TCONST(cs->cs_brg_clk, 718 zs_defspeed[0][zs_consunit]); 719 cs->cs_preg[12] = tconst; 720 cs->cs_preg[13] = tconst >> 8; 721 /* can't use zs_set_speed as we haven't set up the 722 * signal sources, and it's not worth it for now 723 */ 724 725 cs->cs_preg[9] &= ~ZSWR9_MASTER_IE; 726 /* no interrupts until later, after attach. */ 727 728 s = splhigh(); 729 zs_loadchannelregs(cs); 730 splx(s); 731 } 732 733 printf("\nNetBSD/next68k console\n"); 734 } 735 736 /* 737 * Polled console input putchar. 738 */ 739 int 740 zscngetc(dev) 741 dev_t dev; 742 { 743 return (zs_getc(zs_conschan)); 744 } 745 746 /* 747 * Polled console output putchar. 748 */ 749 void 750 zscnputc(dev, c) 751 dev_t dev; 752 int c; 753 { 754 zs_putc(zs_conschan, c); 755 } 756 757 /*****************************************************************/ 758
Indexes created Fri Oct 03 02:09:57 GMT 2025