zs.c revision 1.16
1 /* $NetBSD: zs.c,v 1.16 2002/09/06 13:18:43 gehenna Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves. 45 */ 46 47 /* This was snarfed from the netbsd sparc/dev/zs.c at version 1.56 48 * and then updated to reflect changes in 1.59 49 * by Darrin B Jewell <jewell (at) mit.edu> Mon Mar 30 20:24:46 1998 50 */ 51 52 #include "opt_ddb.h" 53 #include "opt_kgdb.h" 54 #include "opt_serial.h" 55 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/conf.h> 59 #include <sys/device.h> 60 #include <sys/file.h> 61 #include <sys/ioctl.h> 62 #include <sys/kernel.h> 63 #include <sys/proc.h> 64 #include <sys/tty.h> 65 #include <sys/time.h> 66 #include <sys/syslog.h> 67 68 #include <machine/autoconf.h> 69 #include <machine/cpu.h> 70 #include <machine/psl.h> 71 72 #include <dev/cons.h> 73 74 #include <dev/ic/z8530reg.h> 75 #include <machine/z8530var.h> 76 77 #include <next68k/next68k/isr.h> 78 #include <next68k/dev/zs_cons.h> 79 80 #include "zsc.h" /* NZSC */ 81 82 #if (NZSC < 0) 83 #error "No serial controllers?" 84 #endif 85 86 /* 87 * Some warts needed by z8530tty.c - 88 * The default parity REALLY needs to be the same as the PROM uses, 89 * or you can not see messages done with printf during boot-up... 90 */ 91 int zs_def_cflag = (CREAD | CS8 | HUPCL); 92 93 /* 94 * The NeXT provides a 3.686400 MHz clock to the ZS chips. 95 */ 96 #define PCLK (9600 * 384) /* PCLK pin input clock rate */ 97 98 #define ZS_DELAY() delay(2) 99 100 /* The layout of this is hardware-dependent (padding, order). */ 101 struct zschan { 102 volatile u_char zc_csr; /* ctrl,status, and indirect access */ 103 u_char zc_xxx0; 104 volatile u_char zc_data; /* data */ 105 u_char zc_xxx1; 106 }; 107 108 static char *zsaddr[NZSC]; 109 110 /* Flags from cninit() */ 111 static int zs_hwflags[NZSC][2]; 112 113 /* Default speed for each channel */ 114 static int zs_defspeed[NZSC][2] = { 115 { 9600, /* ttya */ 116 9600 }, /* ttyb */ 117 }; 118 119 static u_char zs_init_reg[16] = { 120 0, /* 0: CMD (reset, etc.) */ 121 0, /* 1: No interrupts yet. */ 122 0x18 + NEXT_I_IPL(NEXT_I_SCC), /* 2: IVECT */ 123 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 124 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 125 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 126 0, /* 6: TXSYNC/SYNCLO */ 127 0, /* 7: RXSYNC/SYNCHI */ 128 0, /* 8: alias for data port */ 129 ZSWR9_MASTER_IE, 130 0, /*10: Misc. TX/RX control bits */ 131 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 132 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */ 133 0, /*13: BAUDHI (default=9600) */ 134 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 135 ZSWR15_BREAK_IE, 136 }; 137 138 struct zschan * 139 zs_get_chan_addr(zs_unit, channel) 140 int zs_unit, channel; 141 { 142 char *addr; 143 struct zschan *zc; 144 145 if (zs_unit >= NZSC) 146 return (NULL); 147 addr = zsaddr[zs_unit]; 148 if (addr == NULL) 149 return (NULL); 150 if (channel == 0) { 151 /* handle the fact the ports are intertwined. */ 152 zc = (struct zschan *)(addr+1); 153 } else { 154 zc = (struct zschan *)(addr); 155 } 156 return (zc); 157 } 158 159 160 /**************************************************************** 161 * Autoconfig 162 ****************************************************************/ 163 164 /* Definition of the driver for autoconfig. */ 165 static int zs_match __P((struct device *, struct cfdata *, void *)); 166 static void zs_attach __P((struct device *, struct device *, void *)); 167 static int zs_print __P((void *, const char *name)); 168 169 extern int zs_getc __P((void *arg)); 170 extern void zs_putc __P((void *arg, int c)); 171 172 struct cfattach zsc_ca = { 173 sizeof(struct zsc_softc), zs_match, zs_attach 174 }; 175 176 extern struct cfdriver zsc_cd; 177 178 /* Interrupt handlers. */ 179 static int zshard __P((void *)); 180 static void zssoft __P((void *)); 181 182 static int zs_get_speed __P((struct zs_chanstate *)); 183 184 185 /* 186 * Is the zs chip present? 187 */ 188 static int 189 zs_match(parent, cf, aux) 190 struct device *parent; 191 struct cfdata *cf; 192 void *aux; 193 { 194 return(1); 195 } 196 197 /* 198 * Attach a found zs. 199 * 200 * USE ROM PROPERTIES port-a-ignore-cd AND port-b-ignore-cd FOR 201 * SOFT CARRIER, AND keyboard PROPERTY FOR KEYBOARD/MOUSE? 202 */ 203 static void 204 zs_attach(parent, self, aux) 205 struct device *parent; 206 struct device *self; 207 void *aux; 208 { 209 struct zsc_softc *zsc = (void *) self; 210 struct zsc_attach_args zsc_args; 211 volatile struct zschan *zc; 212 struct zs_chanstate *cs; 213 int s, zs_unit, channel; 214 215 printf("\n"); 216 217 zs_unit = zsc->zsc_dev.dv_unit; 218 219 if (zs_unit == 0) { 220 zsaddr[0] = (void *)IIOV(NEXT_P_SCC); 221 } 222 223 if (zsaddr[zs_unit] == NULL) 224 panic("zs_attach: zs%d not mapped\n", zs_unit); 225 226 /* 227 * Initialize software state for each channel. 228 */ 229 for (channel = 0; channel < 2; channel++) { 230 zsc_args.channel = channel; 231 zsc_args.hwflags = zs_hwflags[zs_unit][channel]; 232 cs = &zsc->zsc_cs_store[channel]; 233 zsc->zsc_cs[channel] = cs; 234 235 cs->cs_channel = channel; 236 cs->cs_private = NULL; 237 cs->cs_ops = &zsops_null; 238 cs->cs_brg_clk = PCLK / 16; 239 240 zc = zs_get_chan_addr(zs_unit, channel); 241 cs->cs_reg_csr = &zc->zc_csr; 242 cs->cs_reg_data = &zc->zc_data; 243 244 bcopy(zs_init_reg, cs->cs_creg, 16); 245 bcopy(zs_init_reg, cs->cs_preg, 16); 246 247 /* XXX: Get these from the PROM properties! */ 248 /* XXX: See the mvme167 code. Better. */ 249 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) 250 cs->cs_defspeed = zs_get_speed(cs); 251 else 252 cs->cs_defspeed = zs_defspeed[zs_unit][channel]; 253 cs->cs_defcflag = zs_def_cflag; 254 255 /* Make these correspond to cs_defcflag (-crtscts) */ 256 cs->cs_rr0_dcd = ZSRR0_DCD; 257 cs->cs_rr0_cts = 0; 258 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 259 cs->cs_wr5_rts = 0; 260 261 /* 262 * Clear the master interrupt enable. 263 * The INTENA is common to both channels, 264 * so just do it on the A channel. 265 */ 266 if (channel == 0) { 267 zs_write_reg(cs, 9, 0); 268 } 269 270 /* 271 * Look for a child driver for this channel. 272 * The child attach will setup the hardware. 273 */ 274 if (!config_found(self, (void *)&zsc_args, zs_print)) { 275 /* No sub-driver. Just reset it. */ 276 u_char reset = (channel == 0) ? 277 ZSWR9_A_RESET : ZSWR9_B_RESET; 278 s = splzs(); 279 zs_write_reg(cs, 9, reset); 280 splx(s); 281 } 282 } 283 284 isrlink_autovec(zshard, NULL, NEXT_I_IPL(NEXT_I_SCC), 0); 285 INTR_ENABLE(NEXT_I_SCC); 286 287 { 288 int sir; 289 sir = allocate_sir(zssoft, zsc); 290 if (sir != SIR_SERIAL) { 291 panic("Unexpected zssoft sir"); 292 } 293 } 294 295 /* 296 * Set the master interrupt enable and interrupt vector. 297 * (common to both channels, do it on A) 298 */ 299 cs = zsc->zsc_cs[0]; 300 s = splhigh(); 301 /* interrupt vector */ 302 zs_write_reg(cs, 2, zs_init_reg[2]); 303 /* master interrupt control (enable) */ 304 zs_write_reg(cs, 9, zs_init_reg[9]); 305 splx(s); 306 } 307 308 static int 309 zs_print(aux, name) 310 void *aux; 311 const char *name; 312 { 313 struct zsc_attach_args *args = aux; 314 315 if (name != NULL) 316 printf("%s: ", name); 317 318 if (args->channel != -1) 319 printf(" channel %d", args->channel); 320 321 return (UNCONF); 322 } 323 324 static volatile int zssoftpending; 325 326 /* 327 * Our ZS chips all share a common, autovectored interrupt, 328 * so we have to look at all of them on each interrupt. 329 */ 330 static int 331 zshard(arg) 332 void *arg; 333 { 334 register struct zsc_softc *zsc; 335 register int unit, rr3, rval, softreq; 336 if (!INTR_OCCURRED(NEXT_I_SCC)) return 0; 337 338 rval = softreq = 0; 339 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 340 zsc = zsc_cd.cd_devs[unit]; 341 if (zsc == NULL) 342 continue; 343 rr3 = zsc_intr_hard(zsc); 344 /* Count up the interrupts. */ 345 if (rr3) { 346 rval |= rr3; 347 zsc->zsc_intrcnt.ev_count++; 348 } 349 softreq |= zsc->zsc_cs[0]->cs_softreq; 350 softreq |= zsc->zsc_cs[1]->cs_softreq; 351 } 352 353 /* We are at splzs here, so no need to lock. */ 354 if (softreq && (zssoftpending == 0)) { 355 zssoftpending = 1; 356 setsoftserial(); 357 } 358 return(1); 359 } 360 361 /* 362 * Similar scheme as for zshard (look at all of them) 363 */ 364 static void 365 zssoft(arg) 366 void *arg; 367 { 368 register struct zsc_softc *zsc; 369 register int s, unit; 370 371 /* This is not the only ISR on this IPL. */ 372 if (zssoftpending == 0) 373 panic("zssoft not pending"); 374 375 /* 376 * The soft intr. bit will be set by zshard only if 377 * the variable zssoftpending is zero. The order of 378 * these next two statements prevents our clearing 379 * the soft intr bit just after zshard has set it. 380 */ 381 /* ienab_bic(IE_ZSSOFT); */ 382 zssoftpending = 0; 383 384 /* Make sure we call the tty layer at spltty. */ 385 s = spltty(); 386 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 387 zsc = zsc_cd.cd_devs[unit]; 388 if (zsc == NULL) 389 continue; 390 (void)zsc_intr_soft(zsc); 391 } 392 splx(s); 393 } 394 395 396 /* 397 * Compute the current baud rate given a ZS channel. 398 */ 399 static int 400 zs_get_speed(cs) 401 struct zs_chanstate *cs; 402 { 403 int tconst; 404 405 tconst = zs_read_reg(cs, 12); 406 tconst |= zs_read_reg(cs, 13) << 8; 407 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 408 } 409 410 /* 411 * MD functions for setting the baud rate and control modes. 412 */ 413 int 414 zs_set_speed(cs, bps) 415 struct zs_chanstate *cs; 416 int bps; /* bits per second */ 417 { 418 int tconst, real_bps; 419 420 if (bps == 0) 421 return (0); 422 423 #ifdef DIAGNOSTIC 424 if (cs->cs_brg_clk == 0) 425 panic("zs_set_speed"); 426 #endif 427 428 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 429 if (tconst < 0) 430 return (EINVAL); 431 432 /* Convert back to make sure we can do it. */ 433 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 434 435 /* XXX - Allow some tolerance here? */ 436 if (real_bps != bps) 437 return (EINVAL); 438 439 cs->cs_preg[12] = tconst; 440 cs->cs_preg[13] = tconst >> 8; 441 442 /* Caller will stuff the pending registers. */ 443 return (0); 444 } 445 446 int 447 zs_set_modes(cs, cflag) 448 struct zs_chanstate *cs; 449 int cflag; /* bits per second */ 450 { 451 int s; 452 453 /* 454 * Output hardware flow control on the chip is horrendous: 455 * if carrier detect drops, the receiver is disabled, and if 456 * CTS drops, the transmitter is stoped IN MID CHARACTER! 457 * Therefore, NEVER set the HFC bit, and instead use the 458 * status interrupt to detect CTS changes. 459 */ 460 s = splzs(); 461 cs->cs_rr0_pps = 0; 462 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 463 cs->cs_rr0_dcd = 0; 464 if ((cflag & MDMBUF) == 0) 465 cs->cs_rr0_pps = ZSRR0_DCD; 466 } else 467 cs->cs_rr0_dcd = ZSRR0_DCD; 468 if ((cflag & CRTSCTS) != 0) { 469 cs->cs_wr5_dtr = ZSWR5_DTR; 470 cs->cs_wr5_rts = ZSWR5_RTS; 471 cs->cs_rr0_cts = ZSRR0_CTS; 472 } else if ((cflag & CDTRCTS) != 0) { 473 cs->cs_wr5_dtr = 0; 474 cs->cs_wr5_rts = ZSWR5_DTR; 475 cs->cs_rr0_cts = ZSRR0_CTS; 476 } else if ((cflag & MDMBUF) != 0) { 477 cs->cs_wr5_dtr = 0; 478 cs->cs_wr5_rts = ZSWR5_DTR; 479 cs->cs_rr0_cts = ZSRR0_DCD; 480 } else { 481 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 482 cs->cs_wr5_rts = 0; 483 cs->cs_rr0_cts = 0; 484 } 485 splx(s); 486 487 /* Caller will stuff the pending registers. */ 488 return (0); 489 } 490 491 /* 492 * Read or write the chip with suitable delays. 493 */ 494 495 u_char 496 zs_read_reg(cs, reg) 497 struct zs_chanstate *cs; 498 u_char reg; 499 { 500 u_char val; 501 502 *cs->cs_reg_csr = reg; 503 ZS_DELAY(); 504 val = *cs->cs_reg_csr; 505 ZS_DELAY(); 506 return (val); 507 } 508 509 void 510 zs_write_reg(cs, reg, val) 511 struct zs_chanstate *cs; 512 u_char reg, val; 513 { 514 *cs->cs_reg_csr = reg; 515 ZS_DELAY(); 516 *cs->cs_reg_csr = val; 517 ZS_DELAY(); 518 } 519 520 u_char 521 zs_read_csr(cs) 522 struct zs_chanstate *cs; 523 { 524 register u_char val; 525 526 val = *cs->cs_reg_csr; 527 ZS_DELAY(); 528 return (val); 529 } 530 531 void zs_write_csr(cs, val) 532 struct zs_chanstate *cs; 533 u_char val; 534 { 535 *cs->cs_reg_csr = val; 536 ZS_DELAY(); 537 } 538 539 u_char zs_read_data(cs) 540 struct zs_chanstate *cs; 541 { 542 register u_char val; 543 544 val = *cs->cs_reg_data; 545 ZS_DELAY(); 546 return (val); 547 } 548 549 void zs_write_data(cs, val) 550 struct zs_chanstate *cs; 551 u_char val; 552 { 553 *cs->cs_reg_data = val; 554 ZS_DELAY(); 555 } 556 557 /**************************************************************** 558 * Console support functions (Sun specific!) 559 * Note: this code is allowed to know about the layout of 560 * the chip registers, and uses that to keep things simple. 561 * XXX - I think I like the mvme167 code better. -gwr 562 ****************************************************************/ 563 564 extern void Debugger __P((void)); 565 void *zs_conschan; 566 int zs_consunit = 0; 567 568 /* 569 * Handle user request to enter kernel debugger. 570 */ 571 void 572 zs_abort(cs) 573 struct zs_chanstate *cs; 574 { 575 #if defined(ZS_CONSOLE_ABORT) 576 register volatile struct zschan *zc = zs_conschan; 577 int rr0; 578 579 /* Wait for end of break to avoid PROM abort. */ 580 /* XXX - Limit the wait? */ 581 do { 582 rr0 = zc->zc_csr; 583 ZS_DELAY(); 584 } while (rr0 & ZSRR0_BREAK); 585 586 #if defined(KGDB) 587 zskgdb(cs); 588 #elif defined(DDB) 589 Debugger(); 590 #else 591 /* XXX eventually, drop into next rom monitor here */ 592 printf("stopping on keyboard abort not supported without DDB or KGDB\n"); 593 #endif 594 #else /* !ZS_CONSOLE_ABORT */ 595 return; 596 #endif 597 } 598 599 /* 600 * Polled input char. 601 */ 602 int 603 zs_getc(arg) 604 void *arg; 605 { 606 register volatile struct zschan *zc = arg; 607 register int s, c, rr0; 608 609 s = splhigh(); 610 /* Wait for a character to arrive. */ 611 do { 612 rr0 = zc->zc_csr; 613 ZS_DELAY(); 614 } while ((rr0 & ZSRR0_RX_READY) == 0); 615 616 c = zc->zc_data; 617 ZS_DELAY(); 618 splx(s); 619 620 /* 621 * This is used by the kd driver to read scan codes, 622 * so don't translate '\r' ==> '\n' here... 623 */ 624 return (c); 625 } 626 627 /* 628 * Polled output char. 629 */ 630 void 631 zs_putc(arg, c) 632 void *arg; 633 int c; 634 { 635 register volatile struct zschan *zc = arg; 636 register int s, rr0; 637 638 s = splhigh(); 639 /* Wait for transmitter to become ready. */ 640 do { 641 rr0 = zc->zc_csr; 642 ZS_DELAY(); 643 } while ((rr0 & ZSRR0_TX_READY) == 0); 644 645 646 zc->zc_data = c; 647 ZS_DELAY(); 648 649 splx(s); 650 } 651 652 /*****************************************************************/ 653 654 void zscninit __P((struct consdev *)); 655 int zscngetc __P((dev_t)); 656 void zscnputc __P((dev_t, int)); 657 void zscnprobe __P((struct consdev *)); 658 659 void 660 zscnprobe(cp) 661 struct consdev * cp; 662 { 663 extern const struct cdevsw zstty_cdevsw; 664 int maj; 665 maj = cdevsw_lookup_major(&zstty_cdevsw); 666 if (maj != -1) { 667 #ifdef SERCONSOLE 668 cp->cn_pri = CN_REMOTE; 669 #else 670 cp->cn_pri = CN_NORMAL; /* Lower than CN_INTERNAL */ 671 #endif 672 zs_consunit = 0; 673 zsaddr[0] = (void *)IIOV(NEXT_P_SCC); 674 cp->cn_dev = makedev(maj, zs_consunit); 675 zs_conschan = zs_get_chan_addr(0, zs_consunit); 676 } else { 677 cp->cn_pri = CN_DEAD; 678 } 679 } 680 681 682 void 683 zscninit(cn) 684 struct consdev *cn; 685 { 686 zs_hwflags[0][zs_consunit] = ZS_HWFLAG_CONSOLE; 687 688 { 689 struct zs_chanstate xcs; 690 struct zs_chanstate *cs; 691 volatile struct zschan *zc; 692 int tconst, s; 693 694 /* Setup temporary chanstate. */ 695 bzero((caddr_t)&xcs, sizeof(xcs)); 696 cs = &xcs; 697 zc = zs_conschan; 698 cs->cs_reg_csr = &zc->zc_csr; 699 cs->cs_reg_data = &zc->zc_data; 700 cs->cs_channel = zs_consunit; 701 cs->cs_brg_clk = PCLK / 16; 702 703 bcopy(zs_init_reg, cs->cs_preg, 16); 704 cs->cs_preg[5] |= ZSWR5_DTR | ZSWR5_RTS; 705 cs->cs_preg[15] = ZSWR15_BREAK_IE; 706 707 tconst = BPS_TO_TCONST(cs->cs_brg_clk, 708 zs_defspeed[0][zs_consunit]); 709 cs->cs_preg[12] = tconst; 710 cs->cs_preg[13] = tconst >> 8; 711 /* can't use zs_set_speed as we haven't set up the 712 * signal sources, and it's not worth it for now 713 */ 714 715 cs->cs_preg[9] &= ~ZSWR9_MASTER_IE; 716 /* no interrupts until later, after attach. */ 717 718 s = splhigh(); 719 zs_loadchannelregs(cs); 720 splx(s); 721 } 722 723 printf("\nNetBSD/next68k console\n"); 724 } 725 726 /* 727 * Polled console input putchar. 728 */ 729 int 730 zscngetc(dev) 731 dev_t dev; 732 { 733 return (zs_getc(zs_conschan)); 734 } 735 736 /* 737 * Polled console output putchar. 738 */ 739 void 740 zscnputc(dev, c) 741 dev_t dev; 742 int c; 743 { 744 zs_putc(zs_conschan, c); 745 } 746 747 /*****************************************************************/ 748
Indexes created Fri Sep 26 20:09:58 GMT 2025