zs.c revision 1.17
1 /* $NetBSD: zs.c,v 1.17 2002/09/11 01:46:33 mycroft Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves. 45 */ 46 47 /* This was snarfed from the netbsd sparc/dev/zs.c at version 1.56 48 * and then updated to reflect changes in 1.59 49 * by Darrin B Jewell <jewell (at) mit.edu> Mon Mar 30 20:24:46 1998 50 */ 51 52 #include "opt_ddb.h" 53 #include "opt_kgdb.h" 54 #include "opt_serial.h" 55 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/conf.h> 59 #include <sys/device.h> 60 #include <sys/file.h> 61 #include <sys/ioctl.h> 62 #include <sys/kernel.h> 63 #include <sys/proc.h> 64 #include <sys/tty.h> 65 #include <sys/time.h> 66 #include <sys/syslog.h> 67 68 #include <machine/autoconf.h> 69 #include <machine/cpu.h> 70 #include <machine/psl.h> 71 72 #include <dev/cons.h> 73 74 #include <dev/ic/z8530reg.h> 75 #include <machine/z8530var.h> 76 77 #include <next68k/next68k/isr.h> 78 79 #include <next68k/dev/intiovar.h> 80 #include <next68k/dev/zs_cons.h> 81 82 #include "zsc.h" /* NZSC */ 83 84 #if (NZSC < 0) 85 #error "No serial controllers?" 86 #endif 87 88 /* 89 * Some warts needed by z8530tty.c - 90 * The default parity REALLY needs to be the same as the PROM uses, 91 * or you can not see messages done with printf during boot-up... 92 */ 93 int zs_def_cflag = (CREAD | CS8 | HUPCL); 94 95 /* 96 * The NeXT provides a 3.686400 MHz clock to the ZS chips. 97 */ 98 #define PCLK (9600 * 384) /* PCLK pin input clock rate */ 99 100 #define ZS_DELAY() delay(2) 101 102 /* The layout of this is hardware-dependent (padding, order). */ 103 struct zschan { 104 volatile u_char zc_csr; /* ctrl,status, and indirect access */ 105 u_char zc_xxx0; 106 volatile u_char zc_data; /* data */ 107 u_char zc_xxx1; 108 }; 109 110 static char *zsaddr[NZSC]; 111 112 /* Flags from cninit() */ 113 static int zs_hwflags[NZSC][2]; 114 115 /* Default speed for each channel */ 116 static int zs_defspeed[NZSC][2] = { 117 { 9600, /* ttya */ 118 9600 }, /* ttyb */ 119 }; 120 121 static u_char zs_init_reg[16] = { 122 0, /* 0: CMD (reset, etc.) */ 123 0, /* 1: No interrupts yet. */ 124 0x18 + NEXT_I_IPL(NEXT_I_SCC), /* 2: IVECT */ 125 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 126 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 127 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 128 0, /* 6: TXSYNC/SYNCLO */ 129 0, /* 7: RXSYNC/SYNCHI */ 130 0, /* 8: alias for data port */ 131 ZSWR9_MASTER_IE, 132 0, /*10: Misc. TX/RX control bits */ 133 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 134 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */ 135 0, /*13: BAUDHI (default=9600) */ 136 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 137 ZSWR15_BREAK_IE, 138 }; 139 140 struct zschan * 141 zs_get_chan_addr(zs_unit, channel) 142 int zs_unit, channel; 143 { 144 char *addr; 145 struct zschan *zc; 146 147 if (zs_unit >= NZSC) 148 return (NULL); 149 addr = zsaddr[zs_unit]; 150 if (addr == NULL) 151 return (NULL); 152 if (channel == 0) { 153 /* handle the fact the ports are intertwined. */ 154 zc = (struct zschan *)(addr+1); 155 } else { 156 zc = (struct zschan *)(addr); 157 } 158 return (zc); 159 } 160 161 162 /**************************************************************** 163 * Autoconfig 164 ****************************************************************/ 165 166 /* Definition of the driver for autoconfig. */ 167 static int zs_match __P((struct device *, struct cfdata *, void *)); 168 static void zs_attach __P((struct device *, struct device *, void *)); 169 static int zs_print __P((void *, const char *name)); 170 171 extern int zs_getc __P((void *arg)); 172 extern void zs_putc __P((void *arg, int c)); 173 174 struct cfattach zsc_ca = { 175 sizeof(struct zsc_softc), zs_match, zs_attach 176 }; 177 178 extern struct cfdriver zsc_cd; 179 180 /* Interrupt handlers. */ 181 static int zshard __P((void *)); 182 static void zssoft __P((void *)); 183 184 static int zs_get_speed __P((struct zs_chanstate *)); 185 186 187 /* 188 * Is the zs chip present? 189 */ 190 static int 191 zs_match(parent, cf, aux) 192 struct device *parent; 193 struct cfdata *cf; 194 void *aux; 195 { 196 struct intio_attach_args *ia = (struct intio_attach_args *)aux; 197 198 if (zsaddr[cf->cf_unit] == NULL) 199 return(0); 200 201 ia->ia_addr = (void *)zsaddr[cf->cf_unit]; 202 203 return(1); 204 } 205 206 /* 207 * Attach a found zs. 208 * 209 * USE ROM PROPERTIES port-a-ignore-cd AND port-b-ignore-cd FOR 210 * SOFT CARRIER, AND keyboard PROPERTY FOR KEYBOARD/MOUSE? 211 */ 212 static void 213 zs_attach(parent, self, aux) 214 struct device *parent; 215 struct device *self; 216 void *aux; 217 { 218 struct zsc_softc *zsc = (void *) self; 219 struct zsc_attach_args zsc_args; 220 volatile struct zschan *zc; 221 struct zs_chanstate *cs; 222 int s, zs_unit, channel; 223 224 printf("\n"); 225 226 zs_unit = zsc->zsc_dev.dv_unit; 227 228 if (zs_unit == 0) { 229 zsaddr[0] = (void *)IIOV(NEXT_P_SCC); 230 } 231 232 if (zsaddr[zs_unit] == NULL) 233 panic("zs_attach: zs%d not mapped\n", zs_unit); 234 235 /* 236 * Initialize software state for each channel. 237 */ 238 for (channel = 0; channel < 2; channel++) { 239 zsc_args.channel = channel; 240 zsc_args.hwflags = zs_hwflags[zs_unit][channel]; 241 cs = &zsc->zsc_cs_store[channel]; 242 zsc->zsc_cs[channel] = cs; 243 244 cs->cs_channel = channel; 245 cs->cs_private = NULL; 246 cs->cs_ops = &zsops_null; 247 cs->cs_brg_clk = PCLK / 16; 248 249 zc = zs_get_chan_addr(zs_unit, channel); 250 cs->cs_reg_csr = &zc->zc_csr; 251 cs->cs_reg_data = &zc->zc_data; 252 253 bcopy(zs_init_reg, cs->cs_creg, 16); 254 bcopy(zs_init_reg, cs->cs_preg, 16); 255 256 /* XXX: Get these from the PROM properties! */ 257 /* XXX: See the mvme167 code. Better. */ 258 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) 259 cs->cs_defspeed = zs_get_speed(cs); 260 else 261 cs->cs_defspeed = zs_defspeed[zs_unit][channel]; 262 cs->cs_defcflag = zs_def_cflag; 263 264 /* Make these correspond to cs_defcflag (-crtscts) */ 265 cs->cs_rr0_dcd = ZSRR0_DCD; 266 cs->cs_rr0_cts = 0; 267 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 268 cs->cs_wr5_rts = 0; 269 270 /* 271 * Clear the master interrupt enable. 272 * The INTENA is common to both channels, 273 * so just do it on the A channel. 274 */ 275 if (channel == 0) { 276 zs_write_reg(cs, 9, 0); 277 } 278 279 /* 280 * Look for a child driver for this channel. 281 * The child attach will setup the hardware. 282 */ 283 if (!config_found(self, (void *)&zsc_args, zs_print)) { 284 /* No sub-driver. Just reset it. */ 285 u_char reset = (channel == 0) ? 286 ZSWR9_A_RESET : ZSWR9_B_RESET; 287 s = splzs(); 288 zs_write_reg(cs, 9, reset); 289 splx(s); 290 } 291 } 292 293 isrlink_autovec(zshard, NULL, NEXT_I_IPL(NEXT_I_SCC), 0, NULL); 294 INTR_ENABLE(NEXT_I_SCC); 295 296 { 297 int sir; 298 sir = allocate_sir(zssoft, zsc); 299 if (sir != SIR_SERIAL) { 300 panic("Unexpected zssoft sir"); 301 } 302 } 303 304 /* 305 * Set the master interrupt enable and interrupt vector. 306 * (common to both channels, do it on A) 307 */ 308 cs = zsc->zsc_cs[0]; 309 s = splhigh(); 310 /* interrupt vector */ 311 zs_write_reg(cs, 2, zs_init_reg[2]); 312 /* master interrupt control (enable) */ 313 zs_write_reg(cs, 9, zs_init_reg[9]); 314 splx(s); 315 } 316 317 static int 318 zs_print(aux, name) 319 void *aux; 320 const char *name; 321 { 322 struct zsc_attach_args *args = aux; 323 324 if (name != NULL) 325 printf("%s: ", name); 326 327 if (args->channel != -1) 328 printf(" channel %d", args->channel); 329 330 return (UNCONF); 331 } 332 333 static volatile int zssoftpending; 334 335 /* 336 * Our ZS chips all share a common, autovectored interrupt, 337 * so we have to look at all of them on each interrupt. 338 */ 339 static int 340 zshard(arg) 341 void *arg; 342 { 343 register struct zsc_softc *zsc; 344 register int unit, rr3, rval, softreq; 345 if (!INTR_OCCURRED(NEXT_I_SCC)) return 0; 346 347 rval = softreq = 0; 348 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 349 zsc = zsc_cd.cd_devs[unit]; 350 if (zsc == NULL) 351 continue; 352 rr3 = zsc_intr_hard(zsc); 353 /* Count up the interrupts. */ 354 if (rr3) { 355 rval |= rr3; 356 zsc->zsc_intrcnt.ev_count++; 357 } 358 softreq |= zsc->zsc_cs[0]->cs_softreq; 359 softreq |= zsc->zsc_cs[1]->cs_softreq; 360 } 361 362 /* We are at splzs here, so no need to lock. */ 363 if (softreq && (zssoftpending == 0)) { 364 zssoftpending = 1; 365 setsoftserial(); 366 } 367 return(1); 368 } 369 370 /* 371 * Similar scheme as for zshard (look at all of them) 372 */ 373 static void 374 zssoft(arg) 375 void *arg; 376 { 377 register struct zsc_softc *zsc; 378 register int s, unit; 379 380 /* This is not the only ISR on this IPL. */ 381 if (zssoftpending == 0) 382 panic("zssoft not pending"); 383 384 /* 385 * The soft intr. bit will be set by zshard only if 386 * the variable zssoftpending is zero. The order of 387 * these next two statements prevents our clearing 388 * the soft intr bit just after zshard has set it. 389 */ 390 /* ienab_bic(IE_ZSSOFT); */ 391 zssoftpending = 0; 392 393 /* Make sure we call the tty layer at spltty. */ 394 s = spltty(); 395 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 396 zsc = zsc_cd.cd_devs[unit]; 397 if (zsc == NULL) 398 continue; 399 (void)zsc_intr_soft(zsc); 400 } 401 splx(s); 402 } 403 404 405 /* 406 * Compute the current baud rate given a ZS channel. 407 */ 408 static int 409 zs_get_speed(cs) 410 struct zs_chanstate *cs; 411 { 412 int tconst; 413 414 tconst = zs_read_reg(cs, 12); 415 tconst |= zs_read_reg(cs, 13) << 8; 416 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 417 } 418 419 /* 420 * MD functions for setting the baud rate and control modes. 421 */ 422 int 423 zs_set_speed(cs, bps) 424 struct zs_chanstate *cs; 425 int bps; /* bits per second */ 426 { 427 int tconst, real_bps; 428 429 if (bps == 0) 430 return (0); 431 432 #ifdef DIAGNOSTIC 433 if (cs->cs_brg_clk == 0) 434 panic("zs_set_speed"); 435 #endif 436 437 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 438 if (tconst < 0) 439 return (EINVAL); 440 441 /* Convert back to make sure we can do it. */ 442 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 443 444 /* XXX - Allow some tolerance here? */ 445 if (real_bps != bps) 446 return (EINVAL); 447 448 cs->cs_preg[12] = tconst; 449 cs->cs_preg[13] = tconst >> 8; 450 451 /* Caller will stuff the pending registers. */ 452 return (0); 453 } 454 455 int 456 zs_set_modes(cs, cflag) 457 struct zs_chanstate *cs; 458 int cflag; /* bits per second */ 459 { 460 int s; 461 462 /* 463 * Output hardware flow control on the chip is horrendous: 464 * if carrier detect drops, the receiver is disabled, and if 465 * CTS drops, the transmitter is stoped IN MID CHARACTER! 466 * Therefore, NEVER set the HFC bit, and instead use the 467 * status interrupt to detect CTS changes. 468 */ 469 s = splzs(); 470 cs->cs_rr0_pps = 0; 471 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 472 cs->cs_rr0_dcd = 0; 473 if ((cflag & MDMBUF) == 0) 474 cs->cs_rr0_pps = ZSRR0_DCD; 475 } else 476 cs->cs_rr0_dcd = ZSRR0_DCD; 477 if ((cflag & CRTSCTS) != 0) { 478 cs->cs_wr5_dtr = ZSWR5_DTR; 479 cs->cs_wr5_rts = ZSWR5_RTS; 480 cs->cs_rr0_cts = ZSRR0_CTS; 481 } else if ((cflag & CDTRCTS) != 0) { 482 cs->cs_wr5_dtr = 0; 483 cs->cs_wr5_rts = ZSWR5_DTR; 484 cs->cs_rr0_cts = ZSRR0_CTS; 485 } else if ((cflag & MDMBUF) != 0) { 486 cs->cs_wr5_dtr = 0; 487 cs->cs_wr5_rts = ZSWR5_DTR; 488 cs->cs_rr0_cts = ZSRR0_DCD; 489 } else { 490 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 491 cs->cs_wr5_rts = 0; 492 cs->cs_rr0_cts = 0; 493 } 494 splx(s); 495 496 /* Caller will stuff the pending registers. */ 497 return (0); 498 } 499 500 /* 501 * Read or write the chip with suitable delays. 502 */ 503 504 u_char 505 zs_read_reg(cs, reg) 506 struct zs_chanstate *cs; 507 u_char reg; 508 { 509 u_char val; 510 511 *cs->cs_reg_csr = reg; 512 ZS_DELAY(); 513 val = *cs->cs_reg_csr; 514 ZS_DELAY(); 515 return (val); 516 } 517 518 void 519 zs_write_reg(cs, reg, val) 520 struct zs_chanstate *cs; 521 u_char reg, val; 522 { 523 *cs->cs_reg_csr = reg; 524 ZS_DELAY(); 525 *cs->cs_reg_csr = val; 526 ZS_DELAY(); 527 } 528 529 u_char 530 zs_read_csr(cs) 531 struct zs_chanstate *cs; 532 { 533 register u_char val; 534 535 val = *cs->cs_reg_csr; 536 ZS_DELAY(); 537 return (val); 538 } 539 540 void zs_write_csr(cs, val) 541 struct zs_chanstate *cs; 542 u_char val; 543 { 544 *cs->cs_reg_csr = val; 545 ZS_DELAY(); 546 } 547 548 u_char zs_read_data(cs) 549 struct zs_chanstate *cs; 550 { 551 register u_char val; 552 553 val = *cs->cs_reg_data; 554 ZS_DELAY(); 555 return (val); 556 } 557 558 void zs_write_data(cs, val) 559 struct zs_chanstate *cs; 560 u_char val; 561 { 562 *cs->cs_reg_data = val; 563 ZS_DELAY(); 564 } 565 566 /**************************************************************** 567 * Console support functions (Sun specific!) 568 * Note: this code is allowed to know about the layout of 569 * the chip registers, and uses that to keep things simple. 570 * XXX - I think I like the mvme167 code better. -gwr 571 ****************************************************************/ 572 573 extern void Debugger __P((void)); 574 void *zs_conschan; 575 int zs_consunit = 0; 576 577 /* 578 * Handle user request to enter kernel debugger. 579 */ 580 void 581 zs_abort(cs) 582 struct zs_chanstate *cs; 583 { 584 #if defined(ZS_CONSOLE_ABORT) 585 register volatile struct zschan *zc = zs_conschan; 586 int rr0; 587 588 /* Wait for end of break to avoid PROM abort. */ 589 /* XXX - Limit the wait? */ 590 do { 591 rr0 = zc->zc_csr; 592 ZS_DELAY(); 593 } while (rr0 & ZSRR0_BREAK); 594 595 #if defined(KGDB) 596 zskgdb(cs); 597 #elif defined(DDB) 598 Debugger(); 599 #else 600 /* XXX eventually, drop into next rom monitor here */ 601 printf("stopping on keyboard abort not supported without DDB or KGDB\n"); 602 #endif 603 #else /* !ZS_CONSOLE_ABORT */ 604 return; 605 #endif 606 } 607 608 /* 609 * Polled input char. 610 */ 611 int 612 zs_getc(arg) 613 void *arg; 614 { 615 register volatile struct zschan *zc = arg; 616 register int s, c, rr0; 617 618 s = splhigh(); 619 /* Wait for a character to arrive. */ 620 do { 621 rr0 = zc->zc_csr; 622 ZS_DELAY(); 623 } while ((rr0 & ZSRR0_RX_READY) == 0); 624 625 c = zc->zc_data; 626 ZS_DELAY(); 627 splx(s); 628 629 /* 630 * This is used by the kd driver to read scan codes, 631 * so don't translate '\r' ==> '\n' here... 632 */ 633 return (c); 634 } 635 636 /* 637 * Polled output char. 638 */ 639 void 640 zs_putc(arg, c) 641 void *arg; 642 int c; 643 { 644 register volatile struct zschan *zc = arg; 645 register int s, rr0; 646 647 s = splhigh(); 648 /* Wait for transmitter to become ready. */ 649 do { 650 rr0 = zc->zc_csr; 651 ZS_DELAY(); 652 } while ((rr0 & ZSRR0_TX_READY) == 0); 653 654 655 zc->zc_data = c; 656 ZS_DELAY(); 657 658 splx(s); 659 } 660 661 /*****************************************************************/ 662 663 void zscninit __P((struct consdev *)); 664 int zscngetc __P((dev_t)); 665 void zscnputc __P((dev_t, int)); 666 void zscnprobe __P((struct consdev *)); 667 668 void 669 zscnprobe(cp) 670 struct consdev * cp; 671 { 672 extern const struct cdevsw zstty_cdevsw; 673 int maj; 674 maj = cdevsw_lookup_major(&zstty_cdevsw); 675 if (maj != -1) { 676 #ifdef SERCONSOLE 677 cp->cn_pri = CN_REMOTE; 678 #else 679 cp->cn_pri = CN_NORMAL; /* Lower than CN_INTERNAL */ 680 #endif 681 zs_consunit = 0; 682 zsaddr[0] = (void *)IIOV(NEXT_P_SCC); 683 cp->cn_dev = makedev(maj, zs_consunit); 684 zs_conschan = zs_get_chan_addr(0, zs_consunit); 685 } else { 686 cp->cn_pri = CN_DEAD; 687 } 688 } 689 690 691 void 692 zscninit(cn) 693 struct consdev *cn; 694 { 695 zs_hwflags[0][zs_consunit] = ZS_HWFLAG_CONSOLE; 696 697 { 698 struct zs_chanstate xcs; 699 struct zs_chanstate *cs; 700 volatile struct zschan *zc; 701 int tconst, s; 702 703 /* Setup temporary chanstate. */ 704 bzero((caddr_t)&xcs, sizeof(xcs)); 705 cs = &xcs; 706 zc = zs_conschan; 707 cs->cs_reg_csr = &zc->zc_csr; 708 cs->cs_reg_data = &zc->zc_data; 709 cs->cs_channel = zs_consunit; 710 cs->cs_brg_clk = PCLK / 16; 711 712 bcopy(zs_init_reg, cs->cs_preg, 16); 713 cs->cs_preg[5] |= ZSWR5_DTR | ZSWR5_RTS; 714 cs->cs_preg[15] = ZSWR15_BREAK_IE; 715 716 tconst = BPS_TO_TCONST(cs->cs_brg_clk, 717 zs_defspeed[0][zs_consunit]); 718 cs->cs_preg[12] = tconst; 719 cs->cs_preg[13] = tconst >> 8; 720 /* can't use zs_set_speed as we haven't set up the 721 * signal sources, and it's not worth it for now 722 */ 723 724 cs->cs_preg[9] &= ~ZSWR9_MASTER_IE; 725 /* no interrupts until later, after attach. */ 726 727 s = splhigh(); 728 zs_loadchannelregs(cs); 729 splx(s); 730 } 731 732 printf("\nNetBSD/next68k console\n"); 733 } 734 735 /* 736 * Polled console input putchar. 737 */ 738 int 739 zscngetc(dev) 740 dev_t dev; 741 { 742 return (zs_getc(zs_conschan)); 743 } 744 745 /* 746 * Polled console output putchar. 747 */ 748 void 749 zscnputc(dev, c) 750 dev_t dev; 751 int c; 752 { 753 zs_putc(zs_conschan, c); 754 } 755 756 /*****************************************************************/ 757
Indexes created Fri Sep 26 20:09:58 GMT 2025