zs.c revision 1.21
1 /* $NetBSD: zs.c,v 1.21 2003/01/01 01:57:16 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves. 45 */ 46 47 /* This was snarfed from the netbsd sparc/dev/zs.c at version 1.56 48 * and then updated to reflect changes in 1.59 49 * by Darrin B Jewell <jewell (at) mit.edu> Mon Mar 30 20:24:46 1998 50 */ 51 52 #include "opt_ddb.h" 53 #include "opt_kgdb.h" 54 #include "opt_serial.h" 55 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/conf.h> 59 #include <sys/device.h> 60 #include <sys/file.h> 61 #include <sys/ioctl.h> 62 #include <sys/kernel.h> 63 #include <sys/proc.h> 64 #include <sys/tty.h> 65 #include <sys/time.h> 66 #include <sys/syslog.h> 67 68 #include <machine/autoconf.h> 69 #include <machine/cpu.h> 70 #include <machine/psl.h> 71 72 #include <dev/cons.h> 73 74 #include <dev/ic/z8530reg.h> 75 #include <machine/z8530var.h> 76 77 #include <next68k/next68k/isr.h> 78 79 #include <next68k/dev/intiovar.h> 80 #include <next68k/dev/zs_cons.h> 81 82 #include "zsc.h" /* NZSC */ 83 84 #if (NZSC < 0) 85 #error "No serial controllers?" 86 #endif 87 88 /* 89 * Some warts needed by z8530tty.c - 90 * The default parity REALLY needs to be the same as the PROM uses, 91 * or you can not see messages done with printf during boot-up... 92 */ 93 int zs_def_cflag = (CREAD | CS8 | HUPCL); 94 95 /* 96 * The NeXT provides a 3.686400 MHz clock to the ZS chips. 97 */ 98 #define PCLK (9600 * 384) /* PCLK pin input clock rate */ 99 100 #define ZS_DELAY() delay(2) 101 102 /* The layout of this is hardware-dependent (padding, order). */ 103 struct zschan { 104 volatile u_char zc_csr; /* ctrl,status, and indirect access */ 105 u_char zc_xxx0; 106 volatile u_char zc_data; /* data */ 107 u_char zc_xxx1; 108 }; 109 110 static char *zsaddr[NZSC]; 111 112 /* Flags from cninit() */ 113 static int zs_hwflags[NZSC][2]; 114 115 /* Default speed for each channel */ 116 static int zs_defspeed[NZSC][2] = { 117 { 9600, /* ttya */ 118 9600 }, /* ttyb */ 119 }; 120 121 static u_char zs_init_reg[16] = { 122 0, /* 0: CMD (reset, etc.) */ 123 0, /* 1: No interrupts yet. */ 124 0x18 + NEXT_I_IPL(NEXT_I_SCC), /* 2: IVECT */ 125 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 126 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 127 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 128 0, /* 6: TXSYNC/SYNCLO */ 129 0, /* 7: RXSYNC/SYNCHI */ 130 0, /* 8: alias for data port */ 131 ZSWR9_MASTER_IE, 132 0, /*10: Misc. TX/RX control bits */ 133 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 134 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */ 135 0, /*13: BAUDHI (default=9600) */ 136 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 137 ZSWR15_BREAK_IE, 138 }; 139 140 struct zschan * 141 zs_get_chan_addr(zs_unit, channel) 142 int zs_unit, channel; 143 { 144 char *addr; 145 struct zschan *zc; 146 147 if (zs_unit >= NZSC) 148 return (NULL); 149 addr = zsaddr[zs_unit]; 150 if (addr == NULL) 151 return (NULL); 152 if (channel == 0) { 153 /* handle the fact the ports are intertwined. */ 154 zc = (struct zschan *)(addr+1); 155 } else { 156 zc = (struct zschan *)(addr); 157 } 158 return (zc); 159 } 160 161 162 /**************************************************************** 163 * Autoconfig 164 ****************************************************************/ 165 166 /* Definition of the driver for autoconfig. */ 167 static int zs_match __P((struct device *, struct cfdata *, void *)); 168 static void zs_attach __P((struct device *, struct device *, void *)); 169 static int zs_print __P((void *, const char *name)); 170 171 extern int zs_getc __P((void *arg)); 172 extern void zs_putc __P((void *arg, int c)); 173 174 CFATTACH_DECL(zsc, sizeof(struct zsc_softc), 175 zs_match, zs_attach, NULL, NULL); 176 177 extern struct cfdriver zsc_cd; 178 179 /* Interrupt handlers. */ 180 static int zshard __P((void *)); 181 static void zssoft __P((void *)); 182 183 static int zs_get_speed __P((struct zs_chanstate *)); 184 185 186 /* 187 * Is the zs chip present? 188 */ 189 static int 190 zs_match(parent, cf, aux) 191 struct device *parent; 192 struct cfdata *cf; 193 void *aux; 194 { 195 struct intio_attach_args *ia = (struct intio_attach_args *)aux; 196 197 if (zsaddr[cf->cf_unit] == NULL) 198 return(0); 199 200 ia->ia_addr = (void *)zsaddr[cf->cf_unit]; 201 202 return(1); 203 } 204 205 /* 206 * Attach a found zs. 207 * 208 * USE ROM PROPERTIES port-a-ignore-cd AND port-b-ignore-cd FOR 209 * SOFT CARRIER, AND keyboard PROPERTY FOR KEYBOARD/MOUSE? 210 */ 211 static void 212 zs_attach(parent, self, aux) 213 struct device *parent; 214 struct device *self; 215 void *aux; 216 { 217 struct zsc_softc *zsc = (void *) self; 218 struct zsc_attach_args zsc_args; 219 volatile struct zschan *zc; 220 struct zs_chanstate *cs; 221 int s, zs_unit, channel; 222 223 printf("\n"); 224 225 zs_unit = zsc->zsc_dev.dv_unit; 226 227 if (zs_unit == 0) { 228 zsaddr[0] = (void *)IIOV(NEXT_P_SCC); 229 } 230 231 if (zsaddr[zs_unit] == NULL) 232 panic("zs_attach: zs%d not mapped", zs_unit); 233 234 /* 235 * Initialize software state for each channel. 236 */ 237 for (channel = 0; channel < 2; channel++) { 238 zsc_args.channel = channel; 239 zsc_args.hwflags = zs_hwflags[zs_unit][channel]; 240 cs = &zsc->zsc_cs_store[channel]; 241 zsc->zsc_cs[channel] = cs; 242 243 cs->cs_channel = channel; 244 cs->cs_private = NULL; 245 cs->cs_ops = &zsops_null; 246 cs->cs_brg_clk = PCLK / 16; 247 248 zc = zs_get_chan_addr(zs_unit, channel); 249 cs->cs_reg_csr = &zc->zc_csr; 250 cs->cs_reg_data = &zc->zc_data; 251 252 bcopy(zs_init_reg, cs->cs_creg, 16); 253 bcopy(zs_init_reg, cs->cs_preg, 16); 254 255 /* XXX: Get these from the PROM properties! */ 256 /* XXX: See the mvme167 code. Better. */ 257 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) 258 cs->cs_defspeed = zs_get_speed(cs); 259 else 260 cs->cs_defspeed = zs_defspeed[zs_unit][channel]; 261 cs->cs_defcflag = zs_def_cflag; 262 263 /* Make these correspond to cs_defcflag (-crtscts) */ 264 cs->cs_rr0_dcd = ZSRR0_DCD; 265 cs->cs_rr0_cts = 0; 266 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 267 cs->cs_wr5_rts = 0; 268 269 /* 270 * Clear the master interrupt enable. 271 * The INTENA is common to both channels, 272 * so just do it on the A channel. 273 */ 274 if (channel == 0) { 275 zs_write_reg(cs, 9, 0); 276 } 277 278 /* 279 * Look for a child driver for this channel. 280 * The child attach will setup the hardware. 281 */ 282 if (!config_found(self, (void *)&zsc_args, zs_print)) { 283 /* No sub-driver. Just reset it. */ 284 u_char reset = (channel == 0) ? 285 ZSWR9_A_RESET : ZSWR9_B_RESET; 286 s = splzs(); 287 zs_write_reg(cs, 9, reset); 288 splx(s); 289 } 290 } 291 292 isrlink_autovec(zshard, NULL, NEXT_I_IPL(NEXT_I_SCC), 0, NULL); 293 INTR_ENABLE(NEXT_I_SCC); 294 295 { 296 int sir; 297 sir = allocate_sir(zssoft, zsc); 298 if (sir != SIR_SERIAL) { 299 panic("Unexpected zssoft sir"); 300 } 301 } 302 303 /* 304 * Set the master interrupt enable and interrupt vector. 305 * (common to both channels, do it on A) 306 */ 307 cs = zsc->zsc_cs[0]; 308 s = splhigh(); 309 /* interrupt vector */ 310 zs_write_reg(cs, 2, zs_init_reg[2]); 311 /* master interrupt control (enable) */ 312 zs_write_reg(cs, 9, zs_init_reg[9]); 313 splx(s); 314 } 315 316 static int 317 zs_print(aux, name) 318 void *aux; 319 const char *name; 320 { 321 struct zsc_attach_args *args = aux; 322 323 if (name != NULL) 324 aprint_normal("%s: ", name); 325 326 if (args->channel != -1) 327 aprint_normal(" channel %d", args->channel); 328 329 return (UNCONF); 330 } 331 332 static volatile int zssoftpending; 333 334 /* 335 * Our ZS chips all share a common, autovectored interrupt, 336 * so we have to look at all of them on each interrupt. 337 */ 338 static int 339 zshard(arg) 340 void *arg; 341 { 342 register struct zsc_softc *zsc; 343 register int unit, rr3, rval, softreq; 344 if (!INTR_OCCURRED(NEXT_I_SCC)) return 0; 345 346 rval = softreq = 0; 347 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 348 zsc = zsc_cd.cd_devs[unit]; 349 if (zsc == NULL) 350 continue; 351 rr3 = zsc_intr_hard(zsc); 352 /* Count up the interrupts. */ 353 if (rr3) { 354 rval |= rr3; 355 zsc->zsc_intrcnt.ev_count++; 356 } 357 softreq |= zsc->zsc_cs[0]->cs_softreq; 358 softreq |= zsc->zsc_cs[1]->cs_softreq; 359 } 360 361 /* We are at splzs here, so no need to lock. */ 362 if (softreq && (zssoftpending == 0)) { 363 zssoftpending = 1; 364 setsoftserial(); 365 } 366 return(1); 367 } 368 369 /* 370 * Similar scheme as for zshard (look at all of them) 371 */ 372 static void 373 zssoft(arg) 374 void *arg; 375 { 376 register struct zsc_softc *zsc; 377 register int s, unit; 378 379 /* This is not the only ISR on this IPL. */ 380 if (zssoftpending == 0) 381 panic("zssoft not pending"); 382 383 /* 384 * The soft intr. bit will be set by zshard only if 385 * the variable zssoftpending is zero. The order of 386 * these next two statements prevents our clearing 387 * the soft intr bit just after zshard has set it. 388 */ 389 /* ienab_bic(IE_ZSSOFT); */ 390 zssoftpending = 0; 391 392 /* Make sure we call the tty layer at spltty. */ 393 s = spltty(); 394 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 395 zsc = zsc_cd.cd_devs[unit]; 396 if (zsc == NULL) 397 continue; 398 (void)zsc_intr_soft(zsc); 399 } 400 splx(s); 401 } 402 403 404 /* 405 * Compute the current baud rate given a ZS channel. 406 */ 407 static int 408 zs_get_speed(cs) 409 struct zs_chanstate *cs; 410 { 411 int tconst; 412 413 tconst = zs_read_reg(cs, 12); 414 tconst |= zs_read_reg(cs, 13) << 8; 415 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 416 } 417 418 /* 419 * MD functions for setting the baud rate and control modes. 420 */ 421 int 422 zs_set_speed(cs, bps) 423 struct zs_chanstate *cs; 424 int bps; /* bits per second */ 425 { 426 int tconst, real_bps; 427 428 if (bps == 0) 429 return (0); 430 431 #ifdef DIAGNOSTIC 432 if (cs->cs_brg_clk == 0) 433 panic("zs_set_speed"); 434 #endif 435 436 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 437 if (tconst < 0) 438 return (EINVAL); 439 440 /* Convert back to make sure we can do it. */ 441 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 442 443 /* XXX - Allow some tolerance here? */ 444 if (real_bps != bps) 445 return (EINVAL); 446 447 cs->cs_preg[12] = tconst; 448 cs->cs_preg[13] = tconst >> 8; 449 450 /* Caller will stuff the pending registers. */ 451 return (0); 452 } 453 454 int 455 zs_set_modes(cs, cflag) 456 struct zs_chanstate *cs; 457 int cflag; /* bits per second */ 458 { 459 int s; 460 461 /* 462 * Output hardware flow control on the chip is horrendous: 463 * if carrier detect drops, the receiver is disabled, and if 464 * CTS drops, the transmitter is stoped IN MID CHARACTER! 465 * Therefore, NEVER set the HFC bit, and instead use the 466 * status interrupt to detect CTS changes. 467 */ 468 s = splzs(); 469 cs->cs_rr0_pps = 0; 470 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 471 cs->cs_rr0_dcd = 0; 472 if ((cflag & MDMBUF) == 0) 473 cs->cs_rr0_pps = ZSRR0_DCD; 474 } else 475 cs->cs_rr0_dcd = ZSRR0_DCD; 476 if ((cflag & CRTSCTS) != 0) { 477 cs->cs_wr5_dtr = ZSWR5_DTR; 478 cs->cs_wr5_rts = ZSWR5_RTS; 479 cs->cs_rr0_cts = ZSRR0_CTS; 480 } else if ((cflag & CDTRCTS) != 0) { 481 cs->cs_wr5_dtr = 0; 482 cs->cs_wr5_rts = ZSWR5_DTR; 483 cs->cs_rr0_cts = ZSRR0_CTS; 484 } else if ((cflag & MDMBUF) != 0) { 485 cs->cs_wr5_dtr = 0; 486 cs->cs_wr5_rts = ZSWR5_DTR; 487 cs->cs_rr0_cts = ZSRR0_DCD; 488 } else { 489 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 490 cs->cs_wr5_rts = 0; 491 cs->cs_rr0_cts = 0; 492 } 493 splx(s); 494 495 /* Caller will stuff the pending registers. */ 496 return (0); 497 } 498 499 /* 500 * Read or write the chip with suitable delays. 501 */ 502 503 u_char 504 zs_read_reg(cs, reg) 505 struct zs_chanstate *cs; 506 u_char reg; 507 { 508 u_char val; 509 510 *cs->cs_reg_csr = reg; 511 ZS_DELAY(); 512 val = *cs->cs_reg_csr; 513 ZS_DELAY(); 514 return (val); 515 } 516 517 void 518 zs_write_reg(cs, reg, val) 519 struct zs_chanstate *cs; 520 u_char reg, val; 521 { 522 *cs->cs_reg_csr = reg; 523 ZS_DELAY(); 524 *cs->cs_reg_csr = val; 525 ZS_DELAY(); 526 } 527 528 u_char 529 zs_read_csr(cs) 530 struct zs_chanstate *cs; 531 { 532 register u_char val; 533 534 val = *cs->cs_reg_csr; 535 ZS_DELAY(); 536 return (val); 537 } 538 539 void zs_write_csr(cs, val) 540 struct zs_chanstate *cs; 541 u_char val; 542 { 543 *cs->cs_reg_csr = val; 544 ZS_DELAY(); 545 } 546 547 u_char zs_read_data(cs) 548 struct zs_chanstate *cs; 549 { 550 register u_char val; 551 552 val = *cs->cs_reg_data; 553 ZS_DELAY(); 554 return (val); 555 } 556 557 void zs_write_data(cs, val) 558 struct zs_chanstate *cs; 559 u_char val; 560 { 561 *cs->cs_reg_data = val; 562 ZS_DELAY(); 563 } 564 565 /**************************************************************** 566 * Console support functions (Sun specific!) 567 * Note: this code is allowed to know about the layout of 568 * the chip registers, and uses that to keep things simple. 569 * XXX - I think I like the mvme167 code better. -gwr 570 ****************************************************************/ 571 572 extern void Debugger __P((void)); 573 void *zs_conschan; 574 int zs_consunit = 0; 575 576 /* 577 * Handle user request to enter kernel debugger. 578 */ 579 void 580 zs_abort(cs) 581 struct zs_chanstate *cs; 582 { 583 #if defined(ZS_CONSOLE_ABORT) 584 register volatile struct zschan *zc = zs_conschan; 585 int rr0; 586 587 /* Wait for end of break to avoid PROM abort. */ 588 /* XXX - Limit the wait? */ 589 do { 590 rr0 = zc->zc_csr; 591 ZS_DELAY(); 592 } while (rr0 & ZSRR0_BREAK); 593 594 #if defined(KGDB) 595 zskgdb(cs); 596 #elif defined(DDB) 597 Debugger(); 598 #else 599 /* XXX eventually, drop into next rom monitor here */ 600 printf("stopping on keyboard abort not supported without DDB or KGDB\n"); 601 #endif 602 #else /* !ZS_CONSOLE_ABORT */ 603 return; 604 #endif 605 } 606 607 /* 608 * Polled input char. 609 */ 610 int 611 zs_getc(arg) 612 void *arg; 613 { 614 register volatile struct zschan *zc = arg; 615 register int s, c, rr0; 616 617 s = splhigh(); 618 /* Wait for a character to arrive. */ 619 do { 620 rr0 = zc->zc_csr; 621 ZS_DELAY(); 622 } while ((rr0 & ZSRR0_RX_READY) == 0); 623 624 c = zc->zc_data; 625 ZS_DELAY(); 626 splx(s); 627 628 /* 629 * This is used by the kd driver to read scan codes, 630 * so don't translate '\r' ==> '\n' here... 631 */ 632 return (c); 633 } 634 635 /* 636 * Polled output char. 637 */ 638 void 639 zs_putc(arg, c) 640 void *arg; 641 int c; 642 { 643 register volatile struct zschan *zc = arg; 644 register int s, rr0; 645 646 s = splhigh(); 647 /* Wait for transmitter to become ready. */ 648 do { 649 rr0 = zc->zc_csr; 650 ZS_DELAY(); 651 } while ((rr0 & ZSRR0_TX_READY) == 0); 652 653 654 zc->zc_data = c; 655 ZS_DELAY(); 656 657 splx(s); 658 } 659 660 /*****************************************************************/ 661 662 void zscninit __P((struct consdev *)); 663 int zscngetc __P((dev_t)); 664 void zscnputc __P((dev_t, int)); 665 void zscnprobe __P((struct consdev *)); 666 667 void 668 zscnprobe(cp) 669 struct consdev * cp; 670 { 671 extern const struct cdevsw zstty_cdevsw; 672 int maj; 673 maj = cdevsw_lookup_major(&zstty_cdevsw); 674 if (maj != -1) { 675 #ifdef SERCONSOLE 676 cp->cn_pri = CN_REMOTE; 677 #else 678 cp->cn_pri = CN_NORMAL; /* Lower than CN_INTERNAL */ 679 #endif 680 zs_consunit = 0; 681 zsaddr[0] = (void *)IIOV(NEXT_P_SCC); 682 cp->cn_dev = makedev(maj, zs_consunit); 683 zs_conschan = zs_get_chan_addr(0, zs_consunit); 684 } else { 685 cp->cn_pri = CN_DEAD; 686 } 687 } 688 689 690 void 691 zscninit(cn) 692 struct consdev *cn; 693 { 694 zs_hwflags[0][zs_consunit] = ZS_HWFLAG_CONSOLE; 695 696 { 697 struct zs_chanstate xcs; 698 struct zs_chanstate *cs; 699 volatile struct zschan *zc; 700 int tconst, s; 701 702 /* Setup temporary chanstate. */ 703 bzero((caddr_t)&xcs, sizeof(xcs)); 704 cs = &xcs; 705 zc = zs_conschan; 706 cs->cs_reg_csr = &zc->zc_csr; 707 cs->cs_reg_data = &zc->zc_data; 708 cs->cs_channel = zs_consunit; 709 cs->cs_brg_clk = PCLK / 16; 710 711 bcopy(zs_init_reg, cs->cs_preg, 16); 712 cs->cs_preg[5] |= ZSWR5_DTR | ZSWR5_RTS; 713 cs->cs_preg[15] = ZSWR15_BREAK_IE; 714 715 tconst = BPS_TO_TCONST(cs->cs_brg_clk, 716 zs_defspeed[0][zs_consunit]); 717 cs->cs_preg[12] = tconst; 718 cs->cs_preg[13] = tconst >> 8; 719 /* can't use zs_set_speed as we haven't set up the 720 * signal sources, and it's not worth it for now 721 */ 722 723 cs->cs_preg[9] &= ~ZSWR9_MASTER_IE; 724 /* no interrupts until later, after attach. */ 725 726 s = splhigh(); 727 zs_loadchannelregs(cs); 728 splx(s); 729 } 730 731 printf("\nNetBSD/next68k console\n"); 732 } 733 734 /* 735 * Polled console input putchar. 736 */ 737 int 738 zscngetc(dev) 739 dev_t dev; 740 { 741 return (zs_getc(zs_conschan)); 742 } 743 744 /* 745 * Polled console output putchar. 746 */ 747 void 748 zscnputc(dev, c) 749 dev_t dev; 750 int c; 751 { 752 zs_putc(zs_conschan, c); 753 } 754 755 /*****************************************************************/ 756
Indexes created Thu Sep 25 16:09:42 GMT 2025