zs.c revision 1.23
1 /* $NetBSD: zs.c,v 1.23 2003/07/15 02:59:32 lukem Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves. 45 */ 46 47 /* This was snarfed from the netbsd sparc/dev/zs.c at version 1.56 48 * and then updated to reflect changes in 1.59 49 * by Darrin B Jewell <jewell (at) mit.edu> Mon Mar 30 20:24:46 1998 50 */ 51 52 #include <sys/cdefs.h> 53 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.23 2003/07/15 02:59:32 lukem Exp $"); 54 55 #include "opt_ddb.h" 56 #include "opt_kgdb.h" 57 #include "opt_serial.h" 58 59 #include <sys/param.h> 60 #include <sys/systm.h> 61 #include <sys/conf.h> 62 #include <sys/device.h> 63 #include <sys/file.h> 64 #include <sys/ioctl.h> 65 #include <sys/kernel.h> 66 #include <sys/proc.h> 67 #include <sys/tty.h> 68 #include <sys/time.h> 69 #include <sys/syslog.h> 70 71 #include <machine/autoconf.h> 72 #include <machine/cpu.h> 73 #include <machine/psl.h> 74 75 #include <dev/cons.h> 76 77 #include <dev/ic/z8530reg.h> 78 #include <machine/z8530var.h> 79 80 #include <next68k/next68k/isr.h> 81 82 #include <next68k/dev/intiovar.h> 83 #include <next68k/dev/zs_cons.h> 84 85 #include "zsc.h" /* NZSC */ 86 87 #if (NZSC < 0) 88 #error "No serial controllers?" 89 #endif 90 91 /* 92 * Some warts needed by z8530tty.c - 93 * The default parity REALLY needs to be the same as the PROM uses, 94 * or you can not see messages done with printf during boot-up... 95 */ 96 int zs_def_cflag = (CREAD | CS8 | HUPCL); 97 98 /* 99 * The NeXT provides a 3.686400 MHz clock to the ZS chips. 100 */ 101 #define PCLK (9600 * 384) /* PCLK pin input clock rate */ 102 103 #define ZS_DELAY() delay(2) 104 105 /* The layout of this is hardware-dependent (padding, order). */ 106 struct zschan { 107 volatile u_char zc_csr; /* ctrl,status, and indirect access */ 108 u_char zc_xxx0; 109 volatile u_char zc_data; /* data */ 110 u_char zc_xxx1; 111 }; 112 113 static char *zsaddr[NZSC]; 114 115 /* Flags from cninit() */ 116 static int zs_hwflags[NZSC][2]; 117 118 /* Default speed for each channel */ 119 static int zs_defspeed[NZSC][2] = { 120 { 9600, /* ttya */ 121 9600 }, /* ttyb */ 122 }; 123 124 static u_char zs_init_reg[16] = { 125 0, /* 0: CMD (reset, etc.) */ 126 0, /* 1: No interrupts yet. */ 127 0x18 + NEXT_I_IPL(NEXT_I_SCC), /* 2: IVECT */ 128 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 129 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 130 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 131 0, /* 6: TXSYNC/SYNCLO */ 132 0, /* 7: RXSYNC/SYNCHI */ 133 0, /* 8: alias for data port */ 134 ZSWR9_MASTER_IE, 135 0, /*10: Misc. TX/RX control bits */ 136 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 137 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */ 138 0, /*13: BAUDHI (default=9600) */ 139 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 140 ZSWR15_BREAK_IE, 141 }; 142 143 struct zschan * 144 zs_get_chan_addr(zs_unit, channel) 145 int zs_unit, channel; 146 { 147 char *addr; 148 struct zschan *zc; 149 150 if (zs_unit >= NZSC) 151 return (NULL); 152 addr = zsaddr[zs_unit]; 153 if (addr == NULL) 154 return (NULL); 155 if (channel == 0) { 156 /* handle the fact the ports are intertwined. */ 157 zc = (struct zschan *)(addr+1); 158 } else { 159 zc = (struct zschan *)(addr); 160 } 161 return (zc); 162 } 163 164 165 /**************************************************************** 166 * Autoconfig 167 ****************************************************************/ 168 169 /* Definition of the driver for autoconfig. */ 170 static int zs_match __P((struct device *, struct cfdata *, void *)); 171 static void zs_attach __P((struct device *, struct device *, void *)); 172 static int zs_print __P((void *, const char *name)); 173 174 extern int zs_getc __P((void *arg)); 175 extern void zs_putc __P((void *arg, int c)); 176 177 CFATTACH_DECL(zsc, sizeof(struct zsc_softc), 178 zs_match, zs_attach, NULL, NULL); 179 180 extern struct cfdriver zsc_cd; 181 182 /* Interrupt handlers. */ 183 static int zshard __P((void *)); 184 static void zssoft __P((void *)); 185 186 static int zs_get_speed __P((struct zs_chanstate *)); 187 188 189 /* 190 * Is the zs chip present? 191 */ 192 static int 193 zs_match(parent, cf, aux) 194 struct device *parent; 195 struct cfdata *cf; 196 void *aux; 197 { 198 struct intio_attach_args *ia = (struct intio_attach_args *)aux; 199 200 if (zsaddr[cf->cf_unit] == NULL) 201 return(0); 202 203 ia->ia_addr = (void *)zsaddr[cf->cf_unit]; 204 205 return(1); 206 } 207 208 /* 209 * Attach a found zs. 210 * 211 * USE ROM PROPERTIES port-a-ignore-cd AND port-b-ignore-cd FOR 212 * SOFT CARRIER, AND keyboard PROPERTY FOR KEYBOARD/MOUSE? 213 */ 214 static void 215 zs_attach(parent, self, aux) 216 struct device *parent; 217 struct device *self; 218 void *aux; 219 { 220 struct zsc_softc *zsc = (void *) self; 221 struct zsc_attach_args zsc_args; 222 volatile struct zschan *zc; 223 struct zs_chanstate *cs; 224 int s, zs_unit, channel; 225 226 printf("\n"); 227 228 zs_unit = zsc->zsc_dev.dv_unit; 229 230 if (zs_unit == 0) { 231 zsaddr[0] = (void *)IIOV(NEXT_P_SCC); 232 } 233 234 if (zsaddr[zs_unit] == NULL) 235 panic("zs_attach: zs%d not mapped", zs_unit); 236 237 /* 238 * Initialize software state for each channel. 239 */ 240 for (channel = 0; channel < 2; channel++) { 241 zsc_args.channel = channel; 242 zsc_args.hwflags = zs_hwflags[zs_unit][channel]; 243 cs = &zsc->zsc_cs_store[channel]; 244 zsc->zsc_cs[channel] = cs; 245 246 simple_lock_init(&cs->cs_lock); 247 cs->cs_channel = channel; 248 cs->cs_private = NULL; 249 cs->cs_ops = &zsops_null; 250 cs->cs_brg_clk = PCLK / 16; 251 252 zc = zs_get_chan_addr(zs_unit, channel); 253 cs->cs_reg_csr = &zc->zc_csr; 254 cs->cs_reg_data = &zc->zc_data; 255 256 bcopy(zs_init_reg, cs->cs_creg, 16); 257 bcopy(zs_init_reg, cs->cs_preg, 16); 258 259 /* XXX: Get these from the PROM properties! */ 260 /* XXX: See the mvme167 code. Better. */ 261 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) 262 cs->cs_defspeed = zs_get_speed(cs); 263 else 264 cs->cs_defspeed = zs_defspeed[zs_unit][channel]; 265 cs->cs_defcflag = zs_def_cflag; 266 267 /* Make these correspond to cs_defcflag (-crtscts) */ 268 cs->cs_rr0_dcd = ZSRR0_DCD; 269 cs->cs_rr0_cts = 0; 270 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 271 cs->cs_wr5_rts = 0; 272 273 /* 274 * Clear the master interrupt enable. 275 * The INTENA is common to both channels, 276 * so just do it on the A channel. 277 */ 278 if (channel == 0) { 279 zs_write_reg(cs, 9, 0); 280 } 281 282 /* 283 * Look for a child driver for this channel. 284 * The child attach will setup the hardware. 285 */ 286 if (!config_found(self, (void *)&zsc_args, zs_print)) { 287 /* No sub-driver. Just reset it. */ 288 u_char reset = (channel == 0) ? 289 ZSWR9_A_RESET : ZSWR9_B_RESET; 290 s = splzs(); 291 zs_write_reg(cs, 9, reset); 292 splx(s); 293 } 294 } 295 296 isrlink_autovec(zshard, NULL, NEXT_I_IPL(NEXT_I_SCC), 0, NULL); 297 INTR_ENABLE(NEXT_I_SCC); 298 299 { 300 int sir; 301 sir = allocate_sir(zssoft, zsc); 302 if (sir != SIR_SERIAL) { 303 panic("Unexpected zssoft sir"); 304 } 305 } 306 307 /* 308 * Set the master interrupt enable and interrupt vector. 309 * (common to both channels, do it on A) 310 */ 311 cs = zsc->zsc_cs[0]; 312 s = splhigh(); 313 /* interrupt vector */ 314 zs_write_reg(cs, 2, zs_init_reg[2]); 315 /* master interrupt control (enable) */ 316 zs_write_reg(cs, 9, zs_init_reg[9]); 317 splx(s); 318 } 319 320 static int 321 zs_print(aux, name) 322 void *aux; 323 const char *name; 324 { 325 struct zsc_attach_args *args = aux; 326 327 if (name != NULL) 328 aprint_normal("%s: ", name); 329 330 if (args->channel != -1) 331 aprint_normal(" channel %d", args->channel); 332 333 return (UNCONF); 334 } 335 336 static volatile int zssoftpending; 337 338 /* 339 * Our ZS chips all share a common, autovectored interrupt, 340 * so we have to look at all of them on each interrupt. 341 */ 342 static int 343 zshard(arg) 344 void *arg; 345 { 346 register struct zsc_softc *zsc; 347 register int unit, rr3, rval, softreq; 348 if (!INTR_OCCURRED(NEXT_I_SCC)) return 0; 349 350 rval = softreq = 0; 351 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 352 zsc = zsc_cd.cd_devs[unit]; 353 if (zsc == NULL) 354 continue; 355 rr3 = zsc_intr_hard(zsc); 356 /* Count up the interrupts. */ 357 if (rr3) { 358 rval |= rr3; 359 zsc->zsc_intrcnt.ev_count++; 360 } 361 softreq |= zsc->zsc_cs[0]->cs_softreq; 362 softreq |= zsc->zsc_cs[1]->cs_softreq; 363 } 364 365 /* We are at splzs here, so no need to lock. */ 366 if (softreq && (zssoftpending == 0)) { 367 zssoftpending = 1; 368 setsoftserial(); 369 } 370 return(1); 371 } 372 373 /* 374 * Similar scheme as for zshard (look at all of them) 375 */ 376 static void 377 zssoft(arg) 378 void *arg; 379 { 380 register struct zsc_softc *zsc; 381 register int s, unit; 382 383 /* This is not the only ISR on this IPL. */ 384 if (zssoftpending == 0) 385 panic("zssoft not pending"); 386 387 /* 388 * The soft intr. bit will be set by zshard only if 389 * the variable zssoftpending is zero. The order of 390 * these next two statements prevents our clearing 391 * the soft intr bit just after zshard has set it. 392 */ 393 /* ienab_bic(IE_ZSSOFT); */ 394 zssoftpending = 0; 395 396 /* Make sure we call the tty layer at spltty. */ 397 s = spltty(); 398 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 399 zsc = zsc_cd.cd_devs[unit]; 400 if (zsc == NULL) 401 continue; 402 (void)zsc_intr_soft(zsc); 403 } 404 splx(s); 405 } 406 407 408 /* 409 * Compute the current baud rate given a ZS channel. 410 */ 411 static int 412 zs_get_speed(cs) 413 struct zs_chanstate *cs; 414 { 415 int tconst; 416 417 tconst = zs_read_reg(cs, 12); 418 tconst |= zs_read_reg(cs, 13) << 8; 419 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 420 } 421 422 /* 423 * MD functions for setting the baud rate and control modes. 424 */ 425 int 426 zs_set_speed(cs, bps) 427 struct zs_chanstate *cs; 428 int bps; /* bits per second */ 429 { 430 int tconst, real_bps; 431 432 if (bps == 0) 433 return (0); 434 435 #ifdef DIAGNOSTIC 436 if (cs->cs_brg_clk == 0) 437 panic("zs_set_speed"); 438 #endif 439 440 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 441 if (tconst < 0) 442 return (EINVAL); 443 444 /* Convert back to make sure we can do it. */ 445 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 446 447 /* XXX - Allow some tolerance here? */ 448 if (real_bps != bps) 449 return (EINVAL); 450 451 cs->cs_preg[12] = tconst; 452 cs->cs_preg[13] = tconst >> 8; 453 454 /* Caller will stuff the pending registers. */ 455 return (0); 456 } 457 458 int 459 zs_set_modes(cs, cflag) 460 struct zs_chanstate *cs; 461 int cflag; /* bits per second */ 462 { 463 int s; 464 465 /* 466 * Output hardware flow control on the chip is horrendous: 467 * if carrier detect drops, the receiver is disabled, and if 468 * CTS drops, the transmitter is stoped IN MID CHARACTER! 469 * Therefore, NEVER set the HFC bit, and instead use the 470 * status interrupt to detect CTS changes. 471 */ 472 s = splzs(); 473 cs->cs_rr0_pps = 0; 474 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 475 cs->cs_rr0_dcd = 0; 476 if ((cflag & MDMBUF) == 0) 477 cs->cs_rr0_pps = ZSRR0_DCD; 478 } else 479 cs->cs_rr0_dcd = ZSRR0_DCD; 480 if ((cflag & CRTSCTS) != 0) { 481 cs->cs_wr5_dtr = ZSWR5_DTR; 482 cs->cs_wr5_rts = ZSWR5_RTS; 483 cs->cs_rr0_cts = ZSRR0_CTS; 484 } else if ((cflag & CDTRCTS) != 0) { 485 cs->cs_wr5_dtr = 0; 486 cs->cs_wr5_rts = ZSWR5_DTR; 487 cs->cs_rr0_cts = ZSRR0_CTS; 488 } else if ((cflag & MDMBUF) != 0) { 489 cs->cs_wr5_dtr = 0; 490 cs->cs_wr5_rts = ZSWR5_DTR; 491 cs->cs_rr0_cts = ZSRR0_DCD; 492 } else { 493 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 494 cs->cs_wr5_rts = 0; 495 cs->cs_rr0_cts = 0; 496 } 497 splx(s); 498 499 /* Caller will stuff the pending registers. */ 500 return (0); 501 } 502 503 /* 504 * Read or write the chip with suitable delays. 505 */ 506 507 u_char 508 zs_read_reg(cs, reg) 509 struct zs_chanstate *cs; 510 u_char reg; 511 { 512 u_char val; 513 514 *cs->cs_reg_csr = reg; 515 ZS_DELAY(); 516 val = *cs->cs_reg_csr; 517 ZS_DELAY(); 518 return (val); 519 } 520 521 void 522 zs_write_reg(cs, reg, val) 523 struct zs_chanstate *cs; 524 u_char reg, val; 525 { 526 *cs->cs_reg_csr = reg; 527 ZS_DELAY(); 528 *cs->cs_reg_csr = val; 529 ZS_DELAY(); 530 } 531 532 u_char 533 zs_read_csr(cs) 534 struct zs_chanstate *cs; 535 { 536 register u_char val; 537 538 val = *cs->cs_reg_csr; 539 ZS_DELAY(); 540 return (val); 541 } 542 543 void zs_write_csr(cs, val) 544 struct zs_chanstate *cs; 545 u_char val; 546 { 547 *cs->cs_reg_csr = val; 548 ZS_DELAY(); 549 } 550 551 u_char zs_read_data(cs) 552 struct zs_chanstate *cs; 553 { 554 register u_char val; 555 556 val = *cs->cs_reg_data; 557 ZS_DELAY(); 558 return (val); 559 } 560 561 void zs_write_data(cs, val) 562 struct zs_chanstate *cs; 563 u_char val; 564 { 565 *cs->cs_reg_data = val; 566 ZS_DELAY(); 567 } 568 569 /**************************************************************** 570 * Console support functions (Sun specific!) 571 * Note: this code is allowed to know about the layout of 572 * the chip registers, and uses that to keep things simple. 573 * XXX - I think I like the mvme167 code better. -gwr 574 ****************************************************************/ 575 576 extern void Debugger __P((void)); 577 void *zs_conschan; 578 int zs_consunit = 0; 579 580 /* 581 * Handle user request to enter kernel debugger. 582 */ 583 void 584 zs_abort(cs) 585 struct zs_chanstate *cs; 586 { 587 #if defined(ZS_CONSOLE_ABORT) 588 register volatile struct zschan *zc = zs_conschan; 589 int rr0; 590 591 /* Wait for end of break to avoid PROM abort. */ 592 /* XXX - Limit the wait? */ 593 do { 594 rr0 = zc->zc_csr; 595 ZS_DELAY(); 596 } while (rr0 & ZSRR0_BREAK); 597 598 #if defined(KGDB) 599 zskgdb(cs); 600 #elif defined(DDB) 601 Debugger(); 602 #else 603 /* XXX eventually, drop into next rom monitor here */ 604 printf("stopping on keyboard abort not supported without DDB or KGDB\n"); 605 #endif 606 #else /* !ZS_CONSOLE_ABORT */ 607 return; 608 #endif 609 } 610 611 /* 612 * Polled input char. 613 */ 614 int 615 zs_getc(arg) 616 void *arg; 617 { 618 register volatile struct zschan *zc = arg; 619 register int s, c, rr0; 620 621 s = splhigh(); 622 /* Wait for a character to arrive. */ 623 do { 624 rr0 = zc->zc_csr; 625 ZS_DELAY(); 626 } while ((rr0 & ZSRR0_RX_READY) == 0); 627 628 c = zc->zc_data; 629 ZS_DELAY(); 630 splx(s); 631 632 /* 633 * This is used by the kd driver to read scan codes, 634 * so don't translate '\r' ==> '\n' here... 635 */ 636 return (c); 637 } 638 639 /* 640 * Polled output char. 641 */ 642 void 643 zs_putc(arg, c) 644 void *arg; 645 int c; 646 { 647 register volatile struct zschan *zc = arg; 648 register int s, rr0; 649 650 s = splhigh(); 651 /* Wait for transmitter to become ready. */ 652 do { 653 rr0 = zc->zc_csr; 654 ZS_DELAY(); 655 } while ((rr0 & ZSRR0_TX_READY) == 0); 656 657 658 zc->zc_data = c; 659 ZS_DELAY(); 660 661 splx(s); 662 } 663 664 /*****************************************************************/ 665 666 void zscninit __P((struct consdev *)); 667 int zscngetc __P((dev_t)); 668 void zscnputc __P((dev_t, int)); 669 void zscnprobe __P((struct consdev *)); 670 671 void 672 zscnprobe(cp) 673 struct consdev * cp; 674 { 675 extern const struct cdevsw zstty_cdevsw; 676 int maj; 677 maj = cdevsw_lookup_major(&zstty_cdevsw); 678 if (maj != -1) { 679 #ifdef SERCONSOLE 680 cp->cn_pri = CN_REMOTE; 681 #else 682 cp->cn_pri = CN_NORMAL; /* Lower than CN_INTERNAL */ 683 #endif 684 zs_consunit = 0; 685 zsaddr[0] = (void *)IIOV(NEXT_P_SCC); 686 cp->cn_dev = makedev(maj, zs_consunit); 687 zs_conschan = zs_get_chan_addr(0, zs_consunit); 688 } else { 689 cp->cn_pri = CN_DEAD; 690 } 691 } 692 693 694 void 695 zscninit(cn) 696 struct consdev *cn; 697 { 698 zs_hwflags[0][zs_consunit] = ZS_HWFLAG_CONSOLE; 699 700 { 701 struct zs_chanstate xcs; 702 struct zs_chanstate *cs; 703 volatile struct zschan *zc; 704 int tconst, s; 705 706 /* Setup temporary chanstate. */ 707 bzero((caddr_t)&xcs, sizeof(xcs)); 708 cs = &xcs; 709 zc = zs_conschan; 710 cs->cs_reg_csr = &zc->zc_csr; 711 cs->cs_reg_data = &zc->zc_data; 712 cs->cs_channel = zs_consunit; 713 cs->cs_brg_clk = PCLK / 16; 714 715 bcopy(zs_init_reg, cs->cs_preg, 16); 716 cs->cs_preg[5] |= ZSWR5_DTR | ZSWR5_RTS; 717 cs->cs_preg[15] = ZSWR15_BREAK_IE; 718 719 tconst = BPS_TO_TCONST(cs->cs_brg_clk, 720 zs_defspeed[0][zs_consunit]); 721 cs->cs_preg[12] = tconst; 722 cs->cs_preg[13] = tconst >> 8; 723 /* can't use zs_set_speed as we haven't set up the 724 * signal sources, and it's not worth it for now 725 */ 726 727 cs->cs_preg[9] &= ~ZSWR9_MASTER_IE; 728 /* no interrupts until later, after attach. */ 729 730 s = splhigh(); 731 zs_loadchannelregs(cs); 732 splx(s); 733 } 734 735 printf("\nNetBSD/next68k console\n"); 736 } 737 738 /* 739 * Polled console input putchar. 740 */ 741 int 742 zscngetc(dev) 743 dev_t dev; 744 { 745 return (zs_getc(zs_conschan)); 746 } 747 748 /* 749 * Polled console output putchar. 750 */ 751 void 752 zscnputc(dev, c) 753 dev_t dev; 754 int c; 755 { 756 zs_putc(zs_conschan, c); 757 } 758 759 /*****************************************************************/ 760
Indexes created Thu Sep 25 16:09:42 GMT 2025