zs.c revision 1.4
1 /* $NetBSD: zs.c,v 1.4 1998/11/10 22:45:44 dbj Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves. 45 */ 46 47 /* This was snarfed from the netbsd sparc/dev/zs.c at version 1.56 48 * and then updated to reflect changes in 1.59 49 * by Darrin B Jewell <jewell (at) mit.edu> Mon Mar 30 20:24:46 1998 50 */ 51 52 #include "opt_ddb.h" 53 54 #include <sys/param.h> 55 #include <sys/systm.h> 56 #include <sys/conf.h> 57 #include <sys/device.h> 58 #include <sys/file.h> 59 #include <sys/ioctl.h> 60 #include <sys/kernel.h> 61 #include <sys/proc.h> 62 #include <sys/tty.h> 63 #include <sys/time.h> 64 #include <sys/syslog.h> 65 66 #include <machine/autoconf.h> 67 #include <machine/cpu.h> 68 #include <machine/psl.h> 69 70 #include <dev/cons.h> 71 72 #include <dev/ic/z8530reg.h> 73 #include <machine/z8530var.h> 74 75 #include <next68k/next68k/isr.h> 76 77 #include "zsc.h" /* NZSC */ 78 79 #if (NZSC < 0) 80 #error "No serial controllers?" 81 #endif 82 83 /* 84 * Some warts needed by z8530tty.c - 85 * The default parity REALLY needs to be the same as the PROM uses, 86 * or you can not see messages done with printf during boot-up... 87 */ 88 int zs_def_cflag = (CREAD | CS8 | HUPCL); 89 int zs_major = 12; 90 91 /* 92 * The NeXT provides a 3.686400 MHz clock to the ZS chips. 93 */ 94 #if 1 95 #define PCLK (57600*4*16) /* PCLK pin input clock rate */ 96 #else 97 #define PCLK 10000000 98 #endif 99 100 #define ZS_DELAY() delay(2) 101 102 /* The layout of this is hardware-dependent (padding, order). */ 103 struct zschan { 104 volatile u_char zc_csr; /* ctrl,status, and indirect access */ 105 u_char zc_xxx0; 106 volatile u_char zc_data; /* data */ 107 u_char zc_xxx1; 108 }; 109 110 static char *zsaddr[NZSC]; 111 112 /* Flags from cninit() */ 113 static int zs_hwflags[NZSC][2]; 114 115 /* Default speed for each channel */ 116 static int zs_defspeed[NZSC][2] = { 117 { 9600, /* ttya */ 118 9600 }, /* ttyb */ 119 }; 120 121 static u_char zs_init_reg[16] = { 122 0, /* 0: CMD (reset, etc.) */ 123 0, /* 1: No interrupts yet. */ 124 0x18 + NEXT_I_IPL(NEXT_I_SCC), /* 2: IVECT */ 125 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 126 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 127 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 128 0, /* 6: TXSYNC/SYNCLO */ 129 0, /* 7: RXSYNC/SYNCHI */ 130 0, /* 8: alias for data port */ 131 ZSWR9_MASTER_IE, 132 0, /*10: Misc. TX/RX control bits */ 133 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 134 14, /*12: BAUDLO (default=9600) */ 135 0, /*13: BAUDHI (default=9600) */ 136 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 137 ZSWR15_BREAK_IE | ZSWR15_DCD_IE, 138 }; 139 140 static struct zschan * 141 zs_get_chan_addr __P((int zsc_unit, int channel)); 142 143 static struct zschan * 144 zs_get_chan_addr(zs_unit, channel) 145 int zs_unit, channel; 146 { 147 char *addr; 148 struct zschan *zc; 149 150 if (zs_unit >= NZSC) 151 return (NULL); 152 addr = zsaddr[zs_unit]; 153 if (addr == NULL) 154 return (NULL); 155 if (channel == 0) { 156 /* handle the fact the ports are intertwined. */ 157 zc = (struct zschan *)(addr+1); 158 } else { 159 zc = (struct zschan *)(addr); 160 } 161 return (zc); 162 } 163 164 165 /**************************************************************** 166 * Autoconfig 167 ****************************************************************/ 168 169 /* Definition of the driver for autoconfig. */ 170 static int zs_match __P((struct device *, struct cfdata *, void *)); 171 static void zs_attach __P((struct device *, struct device *, void *)); 172 static int zs_print __P((void *, const char *name)); 173 174 extern int zs_getc __P((void *arg)); 175 extern void zs_putc __P((void *arg, int c)); 176 177 struct cfattach zsc_ca = { 178 sizeof(struct zsc_softc), zs_match, zs_attach 179 }; 180 181 extern struct cfdriver zsc_cd; 182 183 /* Interrupt handlers. */ 184 static int zshard __P((void *)); 185 static int zssoft __P((void *)); 186 187 static int zs_get_speed __P((struct zs_chanstate *)); 188 189 190 /* 191 * Is the zs chip present? 192 */ 193 static int 194 zs_match(parent, cf, aux) 195 struct device *parent; 196 struct cfdata *cf; 197 void *aux; 198 { 199 return(1); 200 } 201 202 /* 203 * Attach a found zs. 204 * 205 * USE ROM PROPERTIES port-a-ignore-cd AND port-b-ignore-cd FOR 206 * SOFT CARRIER, AND keyboard PROPERTY FOR KEYBOARD/MOUSE? 207 */ 208 static void 209 zs_attach(parent, self, aux) 210 struct device *parent; 211 struct device *self; 212 void *aux; 213 { 214 215 struct zsc_softc *zsc = (void *) self; 216 struct zsc_attach_args zsc_args; 217 volatile struct zschan *zc; 218 struct zs_chanstate *cs; 219 int s, zs_unit, channel; 220 221 zs_unit = zsc->zsc_dev.dv_unit; 222 223 if (zsaddr[zs_unit] == NULL) 224 panic("zs_attach: zs%d not mapped\n", zs_unit); 225 226 /* 227 * Initialize software state for each channel. 228 */ 229 for (channel = 0; channel < 2; channel++) { 230 zsc_args.channel = channel; 231 zsc_args.hwflags = zs_hwflags[zs_unit][channel]; 232 cs = &zsc->zsc_cs_store[channel]; 233 zsc->zsc_cs[channel] = cs; 234 235 cs->cs_channel = channel; 236 cs->cs_private = NULL; 237 cs->cs_ops = &zsops_null; 238 cs->cs_brg_clk = PCLK / 16; 239 240 zc = zs_get_chan_addr(zs_unit, channel); 241 cs->cs_reg_csr = &zc->zc_csr; 242 cs->cs_reg_data = &zc->zc_data; 243 244 bcopy(zs_init_reg, cs->cs_creg, 16); 245 bcopy(zs_init_reg, cs->cs_preg, 16); 246 247 /* XXX: Get these from the PROM properties! */ 248 /* XXX: See the mvme167 code. Better. */ 249 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) 250 cs->cs_defspeed = zs_get_speed(cs); 251 else 252 cs->cs_defspeed = zs_defspeed[zs_unit][channel]; 253 cs->cs_defcflag = zs_def_cflag; 254 255 /* Make these correspond to cs_defcflag (-crtscts) */ 256 cs->cs_rr0_dcd = ZSRR0_DCD; 257 cs->cs_rr0_cts = 0; 258 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 259 cs->cs_wr5_rts = 0; 260 261 /* 262 * Clear the master interrupt enable. 263 * The INTENA is common to both channels, 264 * so just do it on the A channel. 265 */ 266 if (channel == 0) { 267 zs_write_reg(cs, 9, 0); 268 } 269 270 /* 271 * Look for a child driver for this channel. 272 * The child attach will setup the hardware. 273 */ 274 if (!config_found(self, (void *)&zsc_args, zs_print)) { 275 /* No sub-driver. Just reset it. */ 276 u_char reset = (channel == 0) ? 277 ZSWR9_A_RESET : ZSWR9_B_RESET; 278 s = splzs(); 279 zs_write_reg(cs, 9, reset); 280 splx(s); 281 } 282 } 283 284 isrlink_autovec(zshard, NULL, NEXT_I_IPL(NEXT_I_SCC), 0); 285 INTR_ENABLE(NEXT_I_SCC); 286 287 { 288 int sir; 289 sir = allocate_sir(zssoft, zsc); 290 if (sir != SIR_SERIAL) { 291 panic("Unexpected zssoft sir"); 292 } 293 } 294 295 /* 296 * Set the master interrupt enable and interrupt vector. 297 * (common to both channels, do it on A) 298 */ 299 cs = zsc->zsc_cs[0]; 300 s = splhigh(); 301 /* interrupt vector */ 302 zs_write_reg(cs, 2, zs_init_reg[2]); 303 /* master interrupt control (enable) */ 304 zs_write_reg(cs, 9, zs_init_reg[9]); 305 splx(s); 306 307 } 308 309 static int 310 zs_print(aux, name) 311 void *aux; 312 const char *name; 313 { 314 struct zsc_attach_args *args = aux; 315 316 if (name != NULL) 317 printf("%s: ", name); 318 319 if (args->channel != -1) 320 printf(" channel %d", args->channel); 321 322 return (UNCONF); 323 } 324 325 static volatile int zssoftpending; 326 327 /* 328 * Our ZS chips all share a common, autovectored interrupt, 329 * so we have to look at all of them on each interrupt. 330 */ 331 static int 332 zshard(arg) 333 void *arg; 334 { 335 register struct zsc_softc *zsc; 336 register int unit, rr3, rval, softreq; 337 if (!INTR_OCCURRED(NEXT_I_SCC)) return 0; 338 339 rval = softreq = 0; 340 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 341 zsc = zsc_cd.cd_devs[unit]; 342 if (zsc == NULL) 343 continue; 344 rr3 = zsc_intr_hard(zsc); 345 /* Count up the interrupts. */ 346 if (rr3) { 347 rval |= rr3; 348 zsc->zsc_intrcnt.ev_count++; 349 } 350 softreq |= zsc->zsc_cs[0]->cs_softreq; 351 softreq |= zsc->zsc_cs[1]->cs_softreq; 352 } 353 354 /* We are at splzs here, so no need to lock. */ 355 if (softreq && (zssoftpending == 0)) { 356 zssoftpending = 1; 357 setsoftserial(); 358 } 359 return(1); 360 } 361 362 /* 363 * Similar scheme as for zshard (look at all of them) 364 */ 365 static int 366 zssoft(arg) 367 void *arg; 368 { 369 register struct zsc_softc *zsc; 370 register int s, unit; 371 372 /* This is not the only ISR on this IPL. */ 373 if (zssoftpending == 0) 374 return (0); 375 376 /* 377 * The soft intr. bit will be set by zshard only if 378 * the variable zssoftpending is zero. The order of 379 * these next two statements prevents our clearing 380 * the soft intr bit just after zshard has set it. 381 */ 382 /* ienab_bic(IE_ZSSOFT); */ 383 zssoftpending = 0; 384 385 /* Make sure we call the tty layer at spltty. */ 386 s = spltty(); 387 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 388 zsc = zsc_cd.cd_devs[unit]; 389 if (zsc == NULL) 390 continue; 391 (void)zsc_intr_soft(zsc); 392 } 393 splx(s); 394 return (1); 395 } 396 397 398 /* 399 * Compute the current baud rate given a ZS channel. 400 */ 401 static int 402 zs_get_speed(cs) 403 struct zs_chanstate *cs; 404 { 405 int tconst; 406 407 tconst = zs_read_reg(cs, 12); 408 tconst |= zs_read_reg(cs, 13) << 8; 409 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 410 } 411 412 /* 413 * MD functions for setting the baud rate and control modes. 414 */ 415 int 416 zs_set_speed(cs, bps) 417 struct zs_chanstate *cs; 418 int bps; /* bits per second */ 419 { 420 int tconst, real_bps; 421 422 if (bps == 0) 423 return (0); 424 425 #ifdef DIAGNOSTIC 426 if (cs->cs_brg_clk == 0) 427 panic("zs_set_speed"); 428 #endif 429 430 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 431 if (tconst < 0) 432 return (EINVAL); 433 434 /* Convert back to make sure we can do it. */ 435 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 436 437 /* XXX - Allow some tolerance here? */ 438 if (real_bps != bps) 439 return (EINVAL); 440 441 cs->cs_preg[12] = tconst; 442 cs->cs_preg[13] = tconst >> 8; 443 444 /* Caller will stuff the pending registers. */ 445 return (0); 446 } 447 448 int 449 zs_set_modes(cs, cflag) 450 struct zs_chanstate *cs; 451 int cflag; /* bits per second */ 452 { 453 int s; 454 455 /* 456 * Output hardware flow control on the chip is horrendous: 457 * if carrier detect drops, the receiver is disabled, and if 458 * CTS drops, the transmitter is stoped IN MID CHARACTER! 459 * Therefore, NEVER set the HFC bit, and instead use the 460 * status interrupt to detect CTS changes. 461 */ 462 s = splzs(); 463 if ((cflag & (CLOCAL | MDMBUF)) != 0) 464 cs->cs_rr0_dcd = 0; 465 else 466 cs->cs_rr0_dcd = ZSRR0_DCD; 467 if ((cflag & CRTSCTS) != 0) { 468 cs->cs_wr5_dtr = ZSWR5_DTR; 469 cs->cs_wr5_rts = ZSWR5_RTS; 470 cs->cs_rr0_cts = ZSRR0_CTS; 471 } else if ((cflag & CDTRCTS) != 0) { 472 cs->cs_wr5_dtr = 0; 473 cs->cs_wr5_rts = ZSWR5_DTR; 474 cs->cs_rr0_cts = ZSRR0_CTS; 475 } else if ((cflag & MDMBUF) != 0) { 476 cs->cs_wr5_dtr = 0; 477 cs->cs_wr5_rts = ZSWR5_DTR; 478 cs->cs_rr0_cts = ZSRR0_DCD; 479 } else { 480 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 481 cs->cs_wr5_rts = 0; 482 cs->cs_rr0_cts = 0; 483 } 484 splx(s); 485 486 /* Caller will stuff the pending registers. */ 487 return (0); 488 } 489 490 /* 491 * Read or write the chip with suitable delays. 492 */ 493 494 u_char 495 zs_read_reg(cs, reg) 496 struct zs_chanstate *cs; 497 u_char reg; 498 { 499 u_char val; 500 501 *cs->cs_reg_csr = reg; 502 ZS_DELAY(); 503 val = *cs->cs_reg_csr; 504 ZS_DELAY(); 505 return (val); 506 } 507 508 void 509 zs_write_reg(cs, reg, val) 510 struct zs_chanstate *cs; 511 u_char reg, val; 512 { 513 *cs->cs_reg_csr = reg; 514 ZS_DELAY(); 515 *cs->cs_reg_csr = val; 516 ZS_DELAY(); 517 } 518 519 u_char 520 zs_read_csr(cs) 521 struct zs_chanstate *cs; 522 { 523 register u_char val; 524 525 val = *cs->cs_reg_csr; 526 ZS_DELAY(); 527 return (val); 528 } 529 530 void zs_write_csr(cs, val) 531 struct zs_chanstate *cs; 532 u_char val; 533 { 534 *cs->cs_reg_csr = val; 535 ZS_DELAY(); 536 } 537 538 u_char zs_read_data(cs) 539 struct zs_chanstate *cs; 540 { 541 register u_char val; 542 543 val = *cs->cs_reg_data; 544 ZS_DELAY(); 545 return (val); 546 } 547 548 void zs_write_data(cs, val) 549 struct zs_chanstate *cs; 550 u_char val; 551 { 552 *cs->cs_reg_data = val; 553 ZS_DELAY(); 554 } 555 556 /**************************************************************** 557 * Console support functions (Sun specific!) 558 * Note: this code is allowed to know about the layout of 559 * the chip registers, and uses that to keep things simple. 560 * XXX - I think I like the mvme167 code better. -gwr 561 ****************************************************************/ 562 563 extern void Debugger __P((void)); 564 void *zs_conschan; 565 int zs_consunit = 0; 566 567 /* 568 * Handle user request to enter kernel debugger. 569 */ 570 void 571 zs_abort(cs) 572 struct zs_chanstate *cs; 573 { 574 register volatile struct zschan *zc = zs_conschan; 575 int rr0; 576 577 /* Wait for end of break to avoid PROM abort. */ 578 /* XXX - Limit the wait? */ 579 do { 580 rr0 = zc->zc_csr; 581 ZS_DELAY(); 582 } while (rr0 & ZSRR0_BREAK); 583 584 #if defined(KGDB) 585 zskgdb(cs); 586 #elif defined(DDB) 587 Debugger(); 588 #else 589 printf("stopping on keyboard abort\n"); 590 callrom(); 591 #endif 592 } 593 594 /* 595 * Polled input char. 596 */ 597 int 598 zs_getc(arg) 599 void *arg; 600 { 601 register volatile struct zschan *zc = arg; 602 register int s, c, rr0; 603 604 s = splhigh(); 605 /* Wait for a character to arrive. */ 606 do { 607 rr0 = zc->zc_csr; 608 ZS_DELAY(); 609 } while ((rr0 & ZSRR0_RX_READY) == 0); 610 611 c = zc->zc_data; 612 ZS_DELAY(); 613 splx(s); 614 615 /* 616 * This is used by the kd driver to read scan codes, 617 * so don't translate '\r' ==> '\n' here... 618 */ 619 return (c); 620 } 621 622 /* 623 * Polled output char. 624 */ 625 void 626 zs_putc(arg, c) 627 void *arg; 628 int c; 629 { 630 register volatile struct zschan *zc = arg; 631 register int s, rr0; 632 633 s = splhigh(); 634 /* Wait for transmitter to become ready. */ 635 do { 636 rr0 = zc->zc_csr; 637 ZS_DELAY(); 638 } while ((rr0 & ZSRR0_TX_READY) == 0); 639 640 641 zc->zc_data = c; 642 ZS_DELAY(); 643 644 splx(s); 645 } 646 647 /*****************************************************************/ 648 649 void zscninit __P((struct consdev *)); 650 int zscngetc __P((dev_t)); 651 void zscnputc __P((dev_t, int)); 652 void zscnprobe __P((struct consdev *)); 653 extern int zsopen __P(( dev_t dev, int flags, int mode, struct proc *p)); 654 655 void 656 zscnprobe(cp) 657 struct consdev * cp; 658 { 659 int maj; 660 for (maj = 0; maj < nchrdev; maj++) { 661 if (cdevsw[maj].d_open == zsopen) { 662 break; 663 } 664 } 665 if (maj != nchrdev) { 666 cp->cn_pri = CN_NORMAL; /* Lower than CN_INTERNAL */ 667 zs_major = maj; 668 zs_consunit = 0; 669 zsaddr[0] = (void *)IIOV(NEXT_P_SCC); 670 cp->cn_dev = makedev(maj, zs_consunit); 671 zs_conschan = zs_get_chan_addr(0, zs_consunit); 672 } else { 673 cp->cn_pri = CN_DEAD; 674 } 675 } 676 677 678 void 679 zscninit(cn) 680 struct consdev *cn; 681 { 682 zs_hwflags[0][zs_consunit] = ZS_HWFLAG_CONSOLE; 683 684 { 685 struct zs_chanstate xcs; 686 struct zs_chanstate *cs; 687 volatile struct zschan *zc; 688 int tconst, s; 689 690 /* Setup temporary chanstate. */ 691 bzero((caddr_t)&xcs, sizeof(xcs)); 692 cs = &xcs; 693 zc = zs_conschan; 694 cs->cs_reg_csr = &zc->zc_csr; 695 cs->cs_reg_data = &zc->zc_data; 696 cs->cs_channel = zs_consunit; 697 cs->cs_brg_clk = PCLK/16; 698 699 bcopy(zs_init_reg, cs->cs_preg, 16); 700 cs->cs_preg[5] |= ZSWR5_DTR | ZSWR5_RTS; 701 cs->cs_preg[15] = ZSWR15_BREAK_IE; 702 703 tconst = BPS_TO_TCONST(cs->cs_brg_clk, 704 zs_defspeed[0][zs_consunit]); 705 cs->cs_preg[12] = tconst; 706 cs->cs_preg[13] = tconst >> 8; 707 /* can't use zs_set_speed as we haven't set up the 708 * signal sources, and it's not worth it for now 709 */ 710 711 cs->cs_preg[9] &= ~ZSWR9_MASTER_IE; 712 /* no interrupts until later, after attach. */ 713 714 s = splhigh(); 715 zs_loadchannelregs(cs); 716 splx(s); 717 } 718 719 printf("\nNetBSD/next68k console\n"); 720 } 721 722 /* 723 * Polled console input putchar. 724 */ 725 int 726 zscngetc(dev) 727 dev_t dev; 728 { 729 return (zs_getc(zs_conschan)); 730 } 731 732 /* 733 * Polled console output putchar. 734 */ 735 void 736 zscnputc(dev, c) 737 dev_t dev; 738 int c; 739 { 740 zs_putc(zs_conschan, c); 741 } 742 743 /*****************************************************************/ 744
Indexes created Fri Oct 03 02:09:57 GMT 2025