bus_space.h revision 1.23 1 1.23 tsutsui /* $NetBSD: bus_space.h,v 1.23 2023/02/11 02:31:34 tsutsui Exp $ */
2 1.1 dbj
3 1.1 dbj /*-
4 1.1 dbj * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
5 1.1 dbj * All rights reserved.
6 1.1 dbj *
7 1.1 dbj * This code is derived from software contributed to The NetBSD Foundation
8 1.1 dbj * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9 1.1 dbj * NASA Ames Research Center.
10 1.1 dbj *
11 1.1 dbj * Redistribution and use in source and binary forms, with or without
12 1.1 dbj * modification, are permitted provided that the following conditions
13 1.1 dbj * are met:
14 1.1 dbj * 1. Redistributions of source code must retain the above copyright
15 1.1 dbj * notice, this list of conditions and the following disclaimer.
16 1.1 dbj * 2. Redistributions in binary form must reproduce the above copyright
17 1.1 dbj * notice, this list of conditions and the following disclaimer in the
18 1.1 dbj * documentation and/or other materials provided with the distribution.
19 1.1 dbj *
20 1.1 dbj * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21 1.1 dbj * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 1.1 dbj * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 1.1 dbj * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24 1.1 dbj * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 1.1 dbj * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 1.1 dbj * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 1.1 dbj * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 1.1 dbj * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 1.1 dbj * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 1.1 dbj * POSSIBILITY OF SUCH DAMAGE.
31 1.1 dbj */
32 1.1 dbj
33 1.1 dbj /*
34 1.1 dbj * Copyright (C) 1997 Scott Reynolds. All rights reserved.
35 1.1 dbj *
36 1.1 dbj * Redistribution and use in source and binary forms, with or without
37 1.1 dbj * modification, are permitted provided that the following conditions
38 1.1 dbj * are met:
39 1.1 dbj * 1. Redistributions of source code must retain the above copyright
40 1.1 dbj * notice, this list of conditions and the following disclaimer.
41 1.1 dbj * 2. Redistributions in binary form must reproduce the above copyright
42 1.1 dbj * notice, this list of conditions and the following disclaimer in the
43 1.1 dbj * documentation and/or other materials provided with the distribution.
44 1.1 dbj * 3. The name of the author may not be used to endorse or promote products
45 1.1 dbj * derived from this software without specific prior written permission
46 1.1 dbj *
47 1.1 dbj * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
48 1.1 dbj * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
49 1.1 dbj * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
50 1.1 dbj * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
51 1.1 dbj * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
52 1.1 dbj * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
53 1.1 dbj * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
54 1.1 dbj * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
55 1.1 dbj * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
56 1.1 dbj * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
57 1.1 dbj */
58 1.1 dbj
59 1.1 dbj #ifndef _NEXT68K_BUS_SPACE_H_
60 1.1 dbj #define _NEXT68K_BUS_SPACE_H_
61 1.1 dbj /*
62 1.1 dbj * Addresses (in bus space).
63 1.1 dbj */
64 1.1 dbj typedef u_long bus_addr_t;
65 1.1 dbj typedef u_long bus_size_t;
66 1.1 dbj
67 1.17 skrll #define PRIxBUSADDR "lx"
68 1.17 skrll #define PRIxBUSSIZE "lx"
69 1.17 skrll #define PRIuBUSSIZE "lu"
70 1.17 skrll
71 1.1 dbj /*
72 1.1 dbj * Access methods for bus resources and address space.
73 1.1 dbj */
74 1.1 dbj typedef volatile char * bus_space_tag_t;
75 1.1 dbj typedef u_long bus_space_handle_t;
76 1.1 dbj
77 1.17 skrll #define PRIxBSH "lx"
78 1.17 skrll
79 1.1 dbj /*
80 1.1 dbj * Value for the next68k bus space tag, not to be used directly by MI code.
81 1.1 dbj */
82 1.10 mycroft #define NEXT68K_INTIO_BUS_SPACE ((bus_space_tag_t)intiobase)
83 1.1 dbj
84 1.1 dbj /*
85 1.23 tsutsui * Mapping and unmapping operations.
86 1.3 dbj */
87 1.3 dbj
88 1.23 tsutsui int bus_space_map(bus_space_tag_t, bus_addr_t, bus_size_t, int,
89 1.23 tsutsui bus_space_handle_t *);
90 1.1 dbj
91 1.1 dbj #define bus_space_unmap(t, h, s)
92 1.21 tsutsui
93 1.1 dbj #define bus_space_subregion(t, h, o, s, hp) \
94 1.1 dbj (*(hp)=(h)+(o))
95 1.1 dbj
96 1.1 dbj #define BUS_SPACE_MAP_CACHEABLE 0x01
97 1.1 dbj #define BUS_SPACE_MAP_LINEAR 0x02
98 1.1 dbj
99 1.1 dbj /*
100 1.1 dbj * Allocation and deallocation operations.
101 1.1 dbj */
102 1.1 dbj #define bus_space_alloc(t, rs, re, s, a, b, f, ap, hp) \
103 1.1 dbj (-1)
104 1.1 dbj
105 1.1 dbj #define bus_space_free(t, h, s)
106 1.8 deberg
107 1.8 deberg /*
108 1.11 chs * paddr_t bus_space_mmap(bus_space_tag_t t, bus_addr_t base,
109 1.11 chs * off_t offset, int prot, int flags);
110 1.8 deberg *
111 1.8 deberg * Mmap an area of bus space.
112 1.8 deberg */
113 1.8 deberg
114 1.23 tsutsui paddr_t bus_space_mmap(bus_space_tag_t, bus_addr_t, off_t, int, int);
115 1.1 dbj
116 1.1 dbj /*
117 1.22 tsutsui * uintN_t bus_space_read_N(bus_space_tag_t tag,
118 1.11 chs * bus_space_handle_t bsh, bus_size_t offset);
119 1.1 dbj *
120 1.1 dbj * Read a 1, 2, 4, or 8 byte quantity from bus space
121 1.1 dbj * described by tag/handle/offset.
122 1.1 dbj */
123 1.1 dbj
124 1.1 dbj #define bus_space_read_1(t, h, o) \
125 1.22 tsutsui ((void) t, (*(volatile uint8_t *)((h) + (o))))
126 1.1 dbj
127 1.1 dbj #define bus_space_read_2(t, h, o) \
128 1.22 tsutsui ((void) t, (*(volatile uint16_t *)((h) + (o))))
129 1.1 dbj
130 1.1 dbj #define bus_space_read_4(t, h, o) \
131 1.22 tsutsui ((void) t, (*(volatile uint32_t *)((h) + (o))))
132 1.1 dbj
133 1.1 dbj /*
134 1.11 chs * void bus_space_read_multi_N(bus_space_tag_t tag,
135 1.1 dbj * bus_space_handle_t bsh, bus_size_t offset,
136 1.22 tsutsui * uintN_t *addr, size_t count);
137 1.1 dbj *
138 1.1 dbj * Read `count' 1, 2, 4, or 8 byte quantities from bus space
139 1.1 dbj * described by tag/handle/offset and copy into buffer provided.
140 1.1 dbj */
141 1.1 dbj
142 1.1 dbj #define bus_space_read_multi_1(t, h, o, a, c) do { \
143 1.1 dbj (void) t; \
144 1.13 perry __asm volatile (" \
145 1.7 chs movl %0,%%a0 ; \
146 1.7 chs movl %1,%%a1 ; \
147 1.7 chs movl %2,%%d0 ; \
148 1.7 chs 1: movb %%a0@,%%a1@+ ; \
149 1.7 chs subql #1,%%d0 ; \
150 1.1 dbj jne 1b" : \
151 1.1 dbj : \
152 1.1 dbj "r" ((h) + (o)), "g" (a), "g" (c) : \
153 1.20 tsutsui "a0","a1","d0","memory"); \
154 1.1 dbj } while (0);
155 1.1 dbj
156 1.1 dbj #define bus_space_read_multi_2(t, h, o, a, c) do { \
157 1.1 dbj (void) t; \
158 1.13 perry __asm volatile (" \
159 1.7 chs movl %0,%%a0 ; \
160 1.7 chs movl %1,%%a1 ; \
161 1.7 chs movl %2,%%d0 ; \
162 1.7 chs 1: movw %%a0@,%%a1@+ ; \
163 1.7 chs subql #1,%%d0 ; \
164 1.1 dbj jne 1b" : \
165 1.1 dbj : \
166 1.1 dbj "r" ((h) + (o)), "g" (a), "g" (c) : \
167 1.20 tsutsui "a0","a1","d0","memory"); \
168 1.1 dbj } while (0);
169 1.1 dbj
170 1.1 dbj #define bus_space_read_multi_4(t, h, o, a, c) do { \
171 1.1 dbj (void) t; \
172 1.13 perry __asm volatile (" \
173 1.7 chs movl %0,%%a0 ; \
174 1.7 chs movl %1,%%a1 ; \
175 1.7 chs movl %2,%%d0 ; \
176 1.7 chs 1: movl %%a0@,%%a1@+ ; \
177 1.7 chs subql #1,%%d0 ; \
178 1.1 dbj jne 1b" : \
179 1.1 dbj : \
180 1.1 dbj "r" ((h) + (o)), "g" (a), "g" (c) : \
181 1.20 tsutsui "a0","a1","d0","memory"); \
182 1.1 dbj } while (0);
183 1.1 dbj
184 1.1 dbj /*
185 1.11 chs * void bus_space_read_region_N(bus_space_tag_t tag,
186 1.1 dbj * bus_space_handle_t bsh, bus_size_t offset,
187 1.22 tsutsui * uintN_t *addr, size_t count);
188 1.1 dbj *
189 1.1 dbj * Read `count' 1, 2, 4, or 8 byte quantities from bus space
190 1.1 dbj * described by tag/handle and starting at `offset' and copy into
191 1.1 dbj * buffer provided.
192 1.1 dbj */
193 1.1 dbj
194 1.1 dbj #define bus_space_read_region_1(t, h, o, a, c) do { \
195 1.1 dbj (void) t; \
196 1.13 perry __asm volatile (" \
197 1.7 chs movl %0,%%a0 ; \
198 1.7 chs movl %1,%%a1 ; \
199 1.7 chs movl %2,%%d0 ; \
200 1.7 chs 1: movb %%a0@+,%%a1@+ ; \
201 1.7 chs subql #1,%%d0 ; \
202 1.1 dbj jne 1b" : \
203 1.1 dbj : \
204 1.1 dbj "r" ((h) + (o)), "g" (a), "g" (c) : \
205 1.20 tsutsui "a0","a1","d0","memory"); \
206 1.1 dbj } while (0);
207 1.1 dbj
208 1.1 dbj #define bus_space_read_region_2(t, h, o, a, c) do { \
209 1.1 dbj (void) t; \
210 1.13 perry __asm volatile (" \
211 1.7 chs movl %0,%%a0 ; \
212 1.7 chs movl %1,%%a1 ; \
213 1.7 chs movl %2,%%d0 ; \
214 1.7 chs 1: movw %%a0@+,%%a1@+ ; \
215 1.7 chs subql #1,%%d0 ; \
216 1.1 dbj jne 1b" : \
217 1.1 dbj : \
218 1.1 dbj "r" ((h) + (o)), "g" (a), "g" (c) : \
219 1.20 tsutsui "a0","a1","d0","memory"); \
220 1.1 dbj } while (0);
221 1.1 dbj
222 1.1 dbj #define bus_space_read_region_4(t, h, o, a, c) do { \
223 1.1 dbj (void) t; \
224 1.13 perry __asm volatile (" \
225 1.7 chs movl %0,%%a0 ; \
226 1.7 chs movl %1,%%a1 ; \
227 1.7 chs movl %2,%%d0 ; \
228 1.7 chs 1: movl %%a0@+,%%a1@+ ; \
229 1.7 chs subql #1,%%d0 ; \
230 1.1 dbj jne 1b" : \
231 1.1 dbj : \
232 1.1 dbj "r" ((h) + (o)), "g" (a), "g" (c) : \
233 1.20 tsutsui "a0","a1","d0","memory"); \
234 1.1 dbj } while (0);
235 1.1 dbj
236 1.1 dbj /*
237 1.11 chs * void bus_space_write_N(bus_space_tag_t tag,
238 1.1 dbj * bus_space_handle_t bsh, bus_size_t offset,
239 1.22 tsutsui * uintN_t value);
240 1.1 dbj *
241 1.1 dbj * Write the 1, 2, 4, or 8 byte value `value' to bus space
242 1.1 dbj * described by tag/handle/offset.
243 1.1 dbj */
244 1.1 dbj
245 1.1 dbj #define bus_space_write_1(t, h, o, v) \
246 1.22 tsutsui ((void) t, ((void)(*(volatile uint8_t *)((h) + (o)) = (v))))
247 1.1 dbj
248 1.1 dbj #define bus_space_write_2(t, h, o, v) \
249 1.22 tsutsui ((void) t, ((void)(*(volatile uint16_t *)((h) + (o)) = (v))))
250 1.1 dbj
251 1.1 dbj #define bus_space_write_4(t, h, o, v) \
252 1.22 tsutsui ((void) t, ((void)(*(volatile uint32_t *)((h) + (o)) = (v))))
253 1.1 dbj
254 1.1 dbj /*
255 1.11 chs * void bus_space_write_multi_N(bus_space_tag_t tag,
256 1.1 dbj * bus_space_handle_t bsh, bus_size_t offset,
257 1.22 tsutsui * const uintN_t *addr, size_t count);
258 1.1 dbj *
259 1.1 dbj * Write `count' 1, 2, 4, or 8 byte quantities from the buffer
260 1.1 dbj * provided to bus space described by tag/handle/offset.
261 1.1 dbj */
262 1.1 dbj
263 1.1 dbj #define bus_space_write_multi_1(t, h, o, a, c) do { \
264 1.1 dbj (void) t; \
265 1.13 perry __asm volatile (" \
266 1.7 chs movl %0,%%a0 ; \
267 1.7 chs movl %1,%%a1 ; \
268 1.7 chs movl %2,%%d0 ; \
269 1.7 chs 1: movb %%a1@+,%%a0@ ; \
270 1.7 chs subql #1,%%d0 ; \
271 1.1 dbj jne 1b" : \
272 1.1 dbj : \
273 1.1 dbj "r" ((h) + (o)), "g" (a), "g" (c) : \
274 1.1 dbj "a0","a1","d0"); \
275 1.1 dbj } while (0);
276 1.1 dbj
277 1.1 dbj #define bus_space_write_multi_2(t, h, o, a, c) do { \
278 1.1 dbj (void) t; \
279 1.13 perry __asm volatile (" \
280 1.7 chs movl %0,%%a0 ; \
281 1.7 chs movl %1,%%a1 ; \
282 1.7 chs movl %2,%%d0 ; \
283 1.7 chs 1: movw %%a1@+,%%a0@ ; \
284 1.7 chs subql #1,%%d0 ; \
285 1.1 dbj jne 1b" : \
286 1.1 dbj : \
287 1.1 dbj "r" ((h) + (o)), "g" (a), "g" (c) : \
288 1.1 dbj "a0","a1","d0"); \
289 1.1 dbj } while (0);
290 1.1 dbj
291 1.1 dbj #define bus_space_write_multi_4(t, h, o, a, c) do { \
292 1.1 dbj (void) t; \
293 1.13 perry __asm volatile (" \
294 1.7 chs movl %0,%%a0 ; \
295 1.7 chs movl %1,%%a1 ; \
296 1.7 chs movl %2,%%d0 ; \
297 1.7 chs 1: movl %%a1@+,%%a0@ ; \
298 1.7 chs subql #1,%%d0 ; \
299 1.1 dbj jne 1b" : \
300 1.1 dbj : \
301 1.1 dbj "r" ((h) + (o)), "g" (a), "g" (c) : \
302 1.1 dbj "a0","a1","d0"); \
303 1.1 dbj } while (0);
304 1.1 dbj
305 1.1 dbj /*
306 1.11 chs * void bus_space_write_region_N(bus_space_tag_t tag,
307 1.1 dbj * bus_space_handle_t bsh, bus_size_t offset,
308 1.22 tsutsui * const uintN_t *addr, size_t count);
309 1.1 dbj *
310 1.1 dbj * Write `count' 1, 2, 4, or 8 byte quantities from the buffer provided
311 1.1 dbj * to bus space described by tag/handle starting at `offset'.
312 1.1 dbj */
313 1.1 dbj
314 1.1 dbj #define bus_space_write_region_1(t, h, o, a, c) do { \
315 1.1 dbj (void) t; \
316 1.13 perry __asm volatile (" \
317 1.7 chs movl %0,%%a0 ; \
318 1.7 chs movl %1,%%a1 ; \
319 1.7 chs movl %2,%%d0 ; \
320 1.7 chs 1: movb %%a1@+,%%a0@+ ; \
321 1.7 chs subql #1,%%d0 ; \
322 1.1 dbj jne 1b" : \
323 1.1 dbj : \
324 1.1 dbj "r" ((h) + (o)), "g" (a), "g" (c) : \
325 1.1 dbj "a0","a1","d0"); \
326 1.1 dbj } while (0);
327 1.1 dbj
328 1.1 dbj #define bus_space_write_region_2(t, h, o, a, c) do { \
329 1.1 dbj (void) t; \
330 1.13 perry __asm volatile (" \
331 1.7 chs movl %0,%%a0 ; \
332 1.7 chs movl %1,%%a1 ; \
333 1.7 chs movl %2,%%d0 ; \
334 1.7 chs 1: movw %%a1@+,%%a0@+ ; \
335 1.7 chs subql #1,%%d0 ; \
336 1.1 dbj jne 1b" : \
337 1.1 dbj : \
338 1.1 dbj "r" ((h) + (o)), "g" (a), "g" (c) : \
339 1.1 dbj "a0","a1","d0"); \
340 1.1 dbj } while (0);
341 1.1 dbj
342 1.1 dbj #define bus_space_write_region_4(t, h, o, a, c) do { \
343 1.1 dbj (void) t; \
344 1.13 perry __asm volatile (" \
345 1.7 chs movl %0,%%a0 ; \
346 1.7 chs movl %1,%%a1 ; \
347 1.7 chs movl %2,%%d0 ; \
348 1.7 chs 1: movl %%a1@+,%%a0@+ ; \
349 1.7 chs subql #1,%%d0 ; \
350 1.1 dbj jne 1b" : \
351 1.1 dbj : \
352 1.1 dbj "r" ((h) + (o)), "g" (a), "g" (c) : \
353 1.1 dbj "a0","a1","d0"); \
354 1.1 dbj } while (0);
355 1.1 dbj
356 1.1 dbj /*
357 1.11 chs * void bus_space_set_multi_N(bus_space_tag_t tag,
358 1.22 tsutsui * bus_space_handle_t bsh, bus_size_t offset, uintN_t val,
359 1.11 chs * size_t count);
360 1.1 dbj *
361 1.1 dbj * Write the 1, 2, 4, or 8 byte value `val' to bus space described
362 1.1 dbj * by tag/handle/offset `count' times.
363 1.1 dbj */
364 1.1 dbj
365 1.1 dbj #define bus_space_set_multi_1(t, h, o, val, c) do { \
366 1.1 dbj (void) t; \
367 1.13 perry __asm volatile (" \
368 1.7 chs movl %0,%%a0 ; \
369 1.7 chs movl %1,%%d1 ; \
370 1.7 chs movl %2,%%d0 ; \
371 1.7 chs 1: movb %%d1,%%a0@ ; \
372 1.7 chs subql #1,%%d0 ; \
373 1.1 dbj jne 1b" : \
374 1.1 dbj : \
375 1.1 dbj "r" ((h) + (o)), "g" (val), "g" (c) : \
376 1.1 dbj "a0","d0","d1"); \
377 1.1 dbj } while (0);
378 1.1 dbj
379 1.1 dbj #define bus_space_set_multi_2(t, h, o, val, c) do { \
380 1.1 dbj (void) t; \
381 1.13 perry __asm volatile (" \
382 1.7 chs movl %0,%%a0 ; \
383 1.7 chs movl %1,%%d1 ; \
384 1.7 chs movl %2,%%d0 ; \
385 1.7 chs 1: movw %%d1,%%a0@ ; \
386 1.7 chs subql #1,%%d0 ; \
387 1.1 dbj jne 1b" : \
388 1.1 dbj : \
389 1.1 dbj "r" ((h) + (o)), "g" (val), "g" (c) : \
390 1.1 dbj "a0","d0","d1"); \
391 1.1 dbj } while (0);
392 1.1 dbj
393 1.1 dbj #define bus_space_set_multi_4(t, h, o, val, c) do { \
394 1.1 dbj (void) t; \
395 1.13 perry __asm volatile (" \
396 1.7 chs movl %0,%%a0 ; \
397 1.7 chs movl %1,%%d1 ; \
398 1.7 chs movl %2,%%d0 ; \
399 1.7 chs 1: movl %%d1,%%a0@ ; \
400 1.7 chs subql #1,%%d0 ; \
401 1.1 dbj jne 1b" : \
402 1.1 dbj : \
403 1.1 dbj "r" ((h) + (o)), "g" (val), "g" (c) : \
404 1.1 dbj "a0","d0","d1"); \
405 1.1 dbj } while (0);
406 1.1 dbj
407 1.1 dbj /*
408 1.11 chs * void bus_space_set_region_N(bus_space_tag_t tag,
409 1.22 tsutsui * bus_space_handle_t bsh, bus_size_t offset, uintN_t val,
410 1.11 chs * size_t count);
411 1.1 dbj *
412 1.1 dbj * Write `count' 1, 2, 4, or 8 byte value `val' to bus space described
413 1.1 dbj * by tag/handle starting at `offset'.
414 1.1 dbj */
415 1.1 dbj
416 1.1 dbj #define bus_space_set_region_1(t, h, o, val, c) do { \
417 1.1 dbj (void) t; \
418 1.13 perry __asm volatile (" \
419 1.7 chs movl %0,%%a0 ; \
420 1.7 chs movl %1,%%d1 ; \
421 1.7 chs movl %2,%%d0 ; \
422 1.7 chs 1: movb %%d1,%%a0@+ ; \
423 1.7 chs subql #1,%%d0 ; \
424 1.1 dbj jne 1b" : \
425 1.1 dbj : \
426 1.1 dbj "r" ((h) + (o)), "g" (val), "g" (c) : \
427 1.1 dbj "a0","d0","d1"); \
428 1.1 dbj } while (0);
429 1.1 dbj
430 1.1 dbj #define bus_space_set_region_2(t, h, o, val, c) do { \
431 1.1 dbj (void) t; \
432 1.13 perry __asm volatile (" \
433 1.7 chs movl %0,%%a0 ; \
434 1.7 chs movl %1,%%d1 ; \
435 1.7 chs movl %2,%%d0 ; \
436 1.7 chs 1: movw %%d1,%%a0@+ ; \
437 1.7 chs subql #1,%%d0 ; \
438 1.1 dbj jne 1b" : \
439 1.1 dbj : \
440 1.1 dbj "r" ((h) + (o)), "g" (val), "g" (c) : \
441 1.1 dbj "a0","d0","d1"); \
442 1.1 dbj } while (0);
443 1.1 dbj
444 1.1 dbj #define bus_space_set_region_4(t, h, o, val, c) do { \
445 1.1 dbj (void) t; \
446 1.13 perry __asm volatile (" \
447 1.7 chs movl %0,%%a0 ; \
448 1.7 chs movl %1,%%d1 ; \
449 1.7 chs movl %2,%%d0 ; \
450 1.7 chs 1: movl %%d1,%%a0@+ ; \
451 1.7 chs subql #1,%%d0 ; \
452 1.1 dbj jne 1b" : \
453 1.1 dbj : \
454 1.1 dbj "r" ((h) + (o)), "g" (val), "g" (c) : \
455 1.1 dbj "a0","d0","d1"); \
456 1.1 dbj } while (0);
457 1.1 dbj
458 1.1 dbj /*
459 1.11 chs * void bus_space_copy_N(bus_space_tag_t tag,
460 1.1 dbj * bus_space_handle_t bsh1, bus_size_t off1,
461 1.1 dbj * bus_space_handle_t bsh2, bus_size_t off2,
462 1.11 chs * size_t count);
463 1.1 dbj *
464 1.1 dbj * Copy `count' 1, 2, 4, or 8 byte values from bus space starting
465 1.1 dbj * at tag/bsh1/off1 to bus space starting at tag/bsh2/off2.
466 1.1 dbj */
467 1.1 dbj
468 1.1 dbj #define __NEXT68K_copy_region_N(BYTES) \
469 1.14 perry static __inline void __CONCAT(bus_space_copy_region_,BYTES) \
470 1.11 chs (bus_space_tag_t, \
471 1.11 chs bus_space_handle_t, bus_size_t, \
472 1.11 chs bus_space_handle_t, bus_size_t, \
473 1.11 chs bus_size_t); \
474 1.1 dbj \
475 1.14 perry static __inline void \
476 1.16 matt __CONCAT(bus_space_copy_region_,BYTES)( \
477 1.16 matt bus_space_tag_t t, \
478 1.16 matt bus_space_handle_t h1, \
479 1.16 matt bus_size_t o1, \
480 1.16 matt bus_space_handle_t h2, \
481 1.16 matt bus_size_t o2, \
482 1.16 matt bus_size_t c) \
483 1.1 dbj { \
484 1.1 dbj bus_size_t o; \
485 1.1 dbj \
486 1.1 dbj if ((h1 + o1) >= (h2 + o2)) { \
487 1.1 dbj /* src after dest: copy forward */ \
488 1.1 dbj for (o = 0; c != 0; c--, o += BYTES) \
489 1.1 dbj __CONCAT(bus_space_write_,BYTES)(t, h2, o2 + o, \
490 1.1 dbj __CONCAT(bus_space_read_,BYTES)(t, h1, o1 + o)); \
491 1.1 dbj } else { \
492 1.1 dbj /* dest after src: copy backwards */ \
493 1.1 dbj for (o = (c - 1) * BYTES; c != 0; c--, o -= BYTES) \
494 1.1 dbj __CONCAT(bus_space_write_,BYTES)(t, h2, o2 + o, \
495 1.1 dbj __CONCAT(bus_space_read_,BYTES)(t, h1, o1 + o)); \
496 1.1 dbj } \
497 1.1 dbj }
498 1.1 dbj __NEXT68K_copy_region_N(1)
499 1.1 dbj __NEXT68K_copy_region_N(2)
500 1.1 dbj __NEXT68K_copy_region_N(4)
501 1.1 dbj
502 1.1 dbj #undef __NEXT68K_copy_region_N
503 1.1 dbj
504 1.1 dbj /*
505 1.1 dbj * Bus read/write barrier methods.
506 1.1 dbj *
507 1.11 chs * void bus_space_barrier(bus_space_tag_t tag,
508 1.1 dbj * bus_space_handle_t bsh, bus_size_t offset,
509 1.11 chs * bus_size_t len, int flags);
510 1.1 dbj *
511 1.1 dbj * Note: the 680x0 does not currently require barriers, but we must
512 1.1 dbj * provide the flags to MI code.
513 1.1 dbj */
514 1.1 dbj #define bus_space_barrier(t, h, o, l, f) \
515 1.1 dbj ((void)((void)(t), (void)(h), (void)(o), (void)(l), (void)(f)))
516 1.1 dbj #define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */
517 1.1 dbj #define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */
518 1.5 drochner
519 1.5 drochner #define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t)
520 1.1 dbj
521 1.1 dbj #endif /* _NEXT68K_BUS_SPACE_H_ */
522