cpu.h revision 1.14
1 /* $NetBSD: cpu.h,v 1.14 2000/09/29 06:35:57 deberg Exp $ */ 2 3 /* 4 * Copyright (c) 1988 University of Utah. 5 * Copyright (c) 1982, 1990, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * the Systems Programming Group of the University of Utah Computer 10 * Science Department. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the University of 23 * California, Berkeley and its contributors. 24 * 4. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * from: Utah $Hdr: cpu.h 1.16 91/03/25$ 41 * 42 * @(#)cpu.h 8.4 (Berkeley) 1/5/94 43 */ 44 45 46 #ifndef _CPU_MACHINE_ 47 #define _CPU_MACHINE_ 48 49 #if defined(_KERNEL) && !defined(_LKM) 50 #include "opt_lockdebug.h" 51 #endif 52 53 /* 54 * Exported definitions unique to next68k/68k cpu support. 55 */ 56 57 /* 58 * Get common m68k definitions. 59 */ 60 #include <m68k/cpu.h> 61 62 #define M68K_MMU_MOTOROLA 63 64 /* 65 * Get interrupt glue. 66 */ 67 #include <machine/intr.h> 68 69 #include <sys/sched.h> 70 struct cpu_info { 71 struct schedstate_percpu ci_schedstate; /* scheduler state */ 72 #if defined(DIAGNOSTIC) || defined(LOCKDEBUG) 73 u_long ci_spin_locks; /* # of spin locks held */ 74 u_long ci_simple_locks; /* # of simple locks held */ 75 #endif 76 }; 77 78 #ifdef _KERNEL 79 extern struct cpu_info cpu_info_store; 80 81 #define curcpu() (&cpu_info_store) 82 83 /* 84 * definitions of cpu-dependent requirements 85 * referenced in generic code 86 */ 87 #define cpu_swapin(p) /* nothing */ 88 #define cpu_wait(p) /* nothing */ 89 #define cpu_swapout(p) /* nothing */ 90 #define cpu_number() 0 91 92 /* 93 * Arguments to hardclock and gatherstats encapsulate the previous 94 * machine state in an opaque clockframe. One the hp300, we use 95 * what the hardware pushes on an interrupt (frame format 0). 96 */ 97 struct clockframe { 98 u_short sr; /* sr at time of interrupt */ 99 u_long pc; /* pc at time of interrupt */ 100 u_short vo; /* vector offset (4-word frame) */ 101 }; 102 103 #define CLKF_USERMODE(framep) (((framep)->sr & PSL_S) == 0) 104 #define CLKF_BASEPRI(framep) (((framep)->sr & PSL_IPL) == 0) 105 #define CLKF_PC(framep) ((framep)->pc) 106 #if 0 107 /* We would like to do it this way... */ 108 #define CLKF_INTR(framep) (((framep)->sr & PSL_M) == 0) 109 #else 110 /* but until we start using PSL_M, we have to do this instead */ 111 #define CLKF_INTR(framep) (0) /* XXX */ 112 #endif 113 114 /* 115 * Preempt the current process if in interrupt from user mode, 116 * or after the current trap/syscall if in system mode. 117 */ 118 extern int want_resched; /* resched() was called */ 119 #define need_resched(ci) { want_resched = 1; aston(); } 120 121 /* 122 * Give a profiling tick to the current process when the user profiling 123 * buffer pages are invalid. On the sun3, request an ast to send us 124 * through trap, marking the proc as needing a profiling tick. 125 */ 126 #define need_proftick(p) ((p)->p_flag |= P_OWEUPC, aston()) 127 128 /* 129 * Notify the current process (p) that it has a signal pending, 130 * process as soon as possible. 131 */ 132 #define signotify(p) aston() 133 134 #define aston() (astpending++) 135 136 int astpending; /* need to trap before returning to user mode */ 137 int want_resched; /* resched() was called */ 138 139 extern volatile char *intiobase; 140 extern volatile char *intiolimit; 141 extern volatile char *monobase; 142 extern volatile char *monolimit; 143 extern volatile char *colorbase; 144 extern volatile char *colorlimit; 145 extern void (*vectab[]) __P((void)); 146 147 struct frame; 148 struct fpframe; 149 struct pcb; 150 151 /* locore.s functions */ 152 void m68881_save __P((struct fpframe *)); 153 void m68881_restore __P((struct fpframe *)); 154 #if 0 /* it's already in m68k/m68k.h */ 155 u_long getdfc __P((void)); 156 u_long getsfc __P((void)); 157 #endif 158 159 #if 0 /* {@@@ Use cacheops.h? */ 160 161 void DCIA __P((void)); 162 void DCIS __P((void)); 163 void DCIU __P((void)); 164 void ICIA __P((void)); 165 void ICPA __P((void)); 166 void PCIA __P((void)); 167 void TBIA __P((void)); 168 void TBIS __P((vm_offset_t)); 169 void TBIAS __P((void)); 170 void TBIAU __P((void)); 171 #if defined(M68040) 172 void DCFA __P((void)); 173 void DCFP __P((vm_offset_t)); 174 void DCFL __P((vm_offset_t)); 175 void DCPL __P((vm_offset_t)); 176 void DCPP __P((vm_offset_t)); 177 void ICPL __P((vm_offset_t)); 178 void ICPP __P((vm_offset_t)); 179 #endif 180 #endif /* }@@@ use m68k/cacheops.c */ 181 182 int suline __P((caddr_t, caddr_t)); 183 void savectx __P((struct pcb *)); 184 void switch_exit __P((struct proc *)); 185 void proc_trampoline __P((void)); 186 void loadustp __P((int)); 187 188 void doboot __P((void)) __attribute__((__noreturn__)); 189 190 /* sys_machdep.c functions */ 191 int cachectl1 __P((unsigned long, vaddr_t, size_t, struct proc *)); 192 193 /* vm_machdep.c functions */ 194 void physaccess __P((caddr_t, caddr_t, int, int)); 195 void physunaccess __P((caddr_t, int)); 196 int kvtop __P((caddr_t)); 197 198 /* clock.c functions */ 199 void next68k_calibrate_delay __P((void)); 200 201 /* trap.c function */ 202 void child_return __P((void *)); 203 204 #endif /* _KERNEL */ 205 206 #define NEXT_RAMBASE (0x4000000) /* really depends on slot, but... */ 207 #define NEXT_BANKSIZE (0x1000000) /* Size of a memory bank in physical address */ 208 209 #if 0 210 /* @@@ this needs to be fixed to work on 030's */ 211 #define NEXT_SLOT_ID 0x0 212 #ifdef M68030 213 #define NEXT_SLOT_ID_BMAP 0x0 214 #endif M68030 215 #endif 216 #ifdef M68040 217 #ifdef DISABLE_NEXT_BMAP_CHIP /* @@@ For turbo testing */ 218 #define NEXT_SLOT_ID_BMAP 0x0 219 #else 220 #define NEXT_SLOT_ID_BMAP 0x00100000 221 #endif 222 #define NEXT_SLOT_ID 0x0 223 #endif M68040 224 225 /****************************************************************/ 226 227 /* Eventually, I'd like to move these defines off into 228 * configure somewhere 229 * Darrin B Jewell <jewell (at) mit.edu> Thu Feb 5 03:50:58 1998 230 */ 231 /* ROM */ 232 #define NEXT_P_EPROM (NEXT_SLOT_ID+0x00000000) 233 #define NEXT_P_EPROM_BMAP (NEXT_SLOT_ID+0x01000000) 234 #define NEXT_P_EPROM_SIZE (128 * 1024) 235 236 /* device space */ 237 #define NEXT_P_DEV_SPACE (NEXT_SLOT_ID+0x02000000) 238 #define NEXT_P_DEV_BMAP (NEXT_SLOT_ID+0x02100000) 239 #define NEXT_DEV_SPACE_SIZE 0x0001c000 240 241 /* DMA control/status (writes MUST be 32-bit) */ 242 #define NEXT_P_SCSI_CSR (NEXT_SLOT_ID+0x02000010) 243 #define NEXT_P_SOUNDOUT_CSR (NEXT_SLOT_ID+0x02000040) 244 #define NEXT_P_DISK_CSR (NEXT_SLOT_ID+0x02000050) 245 #define NEXT_P_SOUNDIN_CSR (NEXT_SLOT_ID+0x02000080) 246 #define NEXT_P_PRINTER_CSR (NEXT_SLOT_ID+0x02000090) 247 #define NEXT_P_SCC_CSR (NEXT_SLOT_ID+0x020000c0) 248 #define NEXT_P_DSP_CSR (NEXT_SLOT_ID+0x020000d0) 249 #define NEXT_P_ENETX_CSR (NEXT_SLOT_ID+0x02000110) 250 #define NEXT_P_ENETR_CSR (NEXT_SLOT_ID+0x02000150) 251 #define NEXT_P_VIDEO_CSR (NEXT_SLOT_ID+0x02000180) 252 #define NEXT_P_M2R_CSR (NEXT_SLOT_ID+0x020001d0) 253 #define NEXT_P_R2M_CSR (NEXT_SLOT_ID+0x020001c0) 254 255 /* DMA scratch pad (writes MUST be 32-bit) */ 256 #define NEXT_P_VIDEO_SPAD (NEXT_SLOT_ID+0x02004180) 257 #define NEXT_P_EVENT_SPAD (NEXT_SLOT_ID+0x0200418c) 258 #define NEXT_P_M2M_SPAD (NEXT_SLOT_ID+0x020041e0) 259 260 /* device registers */ 261 #define NEXT_P_ENET (NEXT_SLOT_ID_BMAP+0x02006000) 262 #define NEXT_P_DSP (NEXT_SLOT_ID_BMAP+0x02008000) 263 #define NEXT_P_MON (NEXT_SLOT_ID+0x0200e000) 264 #define NEXT_P_PRINTER (NEXT_SLOT_ID+0x0200f000) 265 #define NEXT_P_DISK (NEXT_SLOT_ID_BMAP+0x02012000) 266 #define NEXT_P_SCSI (NEXT_SLOT_ID_BMAP+0x02014000) 267 #define NEXT_P_FLOPPY (NEXT_SLOT_ID_BMAP+0x02014100) 268 #define NEXT_P_TIMER (NEXT_SLOT_ID_BMAP+0x02016000) 269 #define NEXT_P_TIMER_CSR (NEXT_SLOT_ID_BMAP+0x02016004) 270 #define NEXT_P_SCC (NEXT_SLOT_ID_BMAP+0x02018000) 271 #define NEXT_P_SCC_CLK (NEXT_SLOT_ID_BMAP+0x02018004) 272 #define NEXT_P_EVENTC (NEXT_SLOT_ID_BMAP+0x0201a000) 273 #define NEXT_P_BMAP (NEXT_SLOT_ID+0x020c0000) 274 /* All COLOR_FB registers are 1 byte wide */ 275 #define NEXT_P_C16_DAC_0 (NEXT_SLOT_ID_BMAP+0x02018100) /* COLOR_FB - RAMDAC */ 276 #define NEXT_P_C16_DAC_1 (NEXT_SLOT_ID_BMAP+0x02018101) 277 #define NEXT_P_C16_DAC_2 (NEXT_SLOT_ID_BMAP+0x02018102) 278 #define NEXT_P_C16_DAC_3 (NEXT_SLOT_ID_BMAP+0x02018103) 279 #define NEXT_P_C16_CMD_REG (NEXT_SLOT_ID_BMAP+0x02018180) /* COLOR_FB - CSR */ 280 281 /* system control registers */ 282 #define NEXT_P_MEMTIMING (NEXT_SLOT_ID_BMAP+0x02006010) 283 #define NEXT_P_INTRSTAT (NEXT_SLOT_ID+0x02007000) 284 #define NEXT_P_INTRSTAT_CON 0x02007000 285 #define NEXT_P_INTRMASK (NEXT_SLOT_ID+0x02007800) 286 #define NEXT_P_INTRMASK_CON 0x02007800 287 #define NEXT_P_SCR1 (NEXT_SLOT_ID+0x0200c000) 288 #define NEXT_P_SCR1_CON 0x0200c000 289 #define NEXT_P_SID 0x0200c800 /* NOT slot-relative */ 290 #define NEXT_P_SCR2 (NEXT_SLOT_ID+0x0200d000) 291 #define NEXT_P_SCR2_CON 0x0200d000 292 #define NEXT_P_RMTINT (NEXT_SLOT_ID+0x0200d800) 293 #define NEXT_P_BRIGHTNESS (NEXT_SLOT_ID_BMAP+0x02010000) 294 #define NEXT_P_DRAM_TIMING (NEXT_SLOT_ID_BMAP+0x02018190) /* Warp 9C memory ctlr */ 295 #define NEXT_P_VRAM_TIMING (NEXT_SLOT_ID_BMAP+0x02018198) /* Warp 9C memory ctlr */ 296 297 /* memory */ 298 #define NEXT_P_MAINMEM (NEXT_SLOT_ID+0x04000000) 299 #define NEXT_P_MEMSIZE 0x04000000 300 #define NEXT_P_VIDEOMEM (NEXT_SLOT_ID+0x0b000000) 301 #define NEXT_P_VIDEOSIZE 0x0003a800 302 #if 0 303 #define NEXT_P_C16_VIDEOMEM (NEXT_SLOT_ID+0x06000000) /* COLOR_FB */ 304 #endif 305 #define NEXT_P_C16_VIDEOMEM (0x2c000000) 306 #define NEXT_P_C16_VIDEOSIZE 0x001D4000 /* COLOR_FB */ 307 #define NEXT_P_WF4VIDEO (NEXT_SLOT_ID+0x0c000000) /* w A+B-AB function */ 308 #define NEXT_P_WF3VIDEO (NEXT_SLOT_ID+0x0d000000) /* w (1-A)B function */ 309 #define NEXT_P_WF2VIDEO (NEXT_SLOT_ID+0x0e000000) /* w ceil(A+B) function */ 310 #define NEXT_P_WF1VIDEO (NEXT_SLOT_ID+0x0f000000) /* w AB function */ 311 #define NEXT_P_WF4MEM (NEXT_SLOT_ID+0x10000000) /* w A+B-AB function */ 312 #define NEXT_P_WF3MEM (NEXT_SLOT_ID+0x14000000) /* w (1-A)B function */ 313 #define NEXT_P_WF2MEM (NEXT_SLOT_ID+0x18000000) /* w ceil(A+B) function */ 314 #define NEXT_P_WF1MEM (NEXT_SLOT_ID+0x1c000000) /* w AB function */ 315 #define NEXT_NMWF 4 /* # of memory write funcs */ 316 317 /* 318 * Interrupt structure. 319 * BASE and BITS define the origin and length of the bit field in the 320 * interrupt status/mask register for the particular interrupt level. 321 * The first component of the interrupt device name indicates the bit 322 * position in the interrupt status and mask registers; the second is the 323 * interrupt level; the third is the bit index relative to the start of the 324 * bit field. 325 */ 326 #define NEXT_I(l,i,b) (((b) << 8) | ((l) << 4) | (i)) 327 #define NEXT_I_INDEX(i) ((i) & 0xf) 328 #define NEXT_I_IPL(i) (((i) >> 4) & 7) 329 #define NEXT_I_BIT(i) ( 1 << (((i) >> 8) & 0x1f)) 330 331 #define NEXT_I_IPL7_BASE 0 332 #define NEXT_I_IPL7_BITS 2 333 #define NEXT_I_NMI NEXT_I(7,0,31) 334 #define NEXT_I_PFAIL NEXT_I(7,1,30) 335 336 #define NEXT_I_IPL6_BASE 2 337 #define NEXT_I_IPL6_BITS 12 338 #define NEXT_I_TIMER NEXT_I(6,0,29) 339 #define NEXT_I_ENETX_DMA NEXT_I(6,1,28) 340 #define NEXT_I_ENETR_DMA NEXT_I(6,2,27) 341 #define NEXT_I_SCSI_DMA NEXT_I(6,3,26) 342 #define NEXT_I_DISK_DMA NEXT_I(6,4,25) 343 #define NEXT_I_PRINTER_DMA NEXT_I(6,5,24) 344 #define NEXT_I_SOUND_OUT_DMA NEXT_I(6,6,23) 345 #define NEXT_I_SOUND_IN_DMA NEXT_I(6,7,22) 346 #define NEXT_I_SCC_DMA NEXT_I(6,8,21) 347 #define NEXT_I_DSP_DMA NEXT_I(6,9,20) 348 #define NEXT_I_M2R_DMA NEXT_I(6,10,19) 349 #define NEXT_I_R2M_DMA NEXT_I(6,11,18) 350 351 #define NEXT_I_IPL5_BASE 14 352 #define NEXT_I_IPL5_BITS 3 353 #define NEXT_I_SCC NEXT_I(5,0,17) 354 #define NEXT_I_REMOTE NEXT_I(5,1,16) 355 #define NEXT_I_BUS NEXT_I(5,2,15) 356 357 #define NEXT_I_IPL4_BASE 17 358 #define NEXT_I_IPL4_BITS 1 359 #define NEXT_I_DSP_4 NEXT_I(4,0,14) 360 361 #define NEXT_I_IPL3_BASE 18 362 #define NEXT_I_IPL3_BITS 12 363 #define NEXT_I_DISK NEXT_I(3,0,13) 364 #define NEXT_I_C16_VIDEO NEXT_I(3,0,13) /* COLOR_FB - Steals old ESDI interrupt */ 365 #define NEXT_I_SCSI NEXT_I(3,1,12) 366 #define NEXT_I_PRINTER NEXT_I(3,2,11) 367 #define NEXT_I_ENETX NEXT_I(3,3,10) 368 #define NEXT_I_ENETR NEXT_I(3,4,9) 369 #define NEXT_I_SOUND_OVRUN NEXT_I(3,5,8) 370 #define NEXT_I_PHONE NEXT_I(3,6,7) 371 #define NEXT_I_DSP_3 NEXT_I(3,7,6) 372 #define NEXT_I_VIDEO NEXT_I(3,8,5) 373 #define NEXT_I_MONITOR NEXT_I(3,9,4) 374 #define NEXT_I_KYBD_MOUSE NEXT_I(3,10,3) 375 #define NEXT_I_POWER NEXT_I(3,11,2) 376 377 #define NEXT_I_IPL2_BASE 30 378 #define NEXT_I_IPL2_BITS 1 379 #define NEXT_I_SOFTINT1 NEXT_I(2,0,1) 380 381 #define NEXT_I_IPL1_BASE 31 382 #define NEXT_I_IPL1_BITS 1 383 #define NEXT_I_SOFTINT0 NEXT_I(1,0,0) 384 385 /****************************************************************/ 386 387 /* physical memory sections */ 388 #if 0 389 #define ROMBASE (0x00000000) 390 #endif 391 392 #define INTIOBASE (0x02000000) 393 #define INTIOTOP (0x02120000) 394 #define MONOBASE (0x0b000000) 395 #define MONOTOP (0x0b03a800) 396 #define COLORBASE (0x2c000000) 397 #define COLORTOP (0x2c1D4000) 398 399 #define NEXT_INTR_BITS \ 400 "\20\40NMI\37PFAIL\36TIMER\35ENETX_DMA\34ENETR_DMA\33SCSI_DMA\32DISK_DMA\31PRINTER_DMA\30SOUND_OUT_DMA\27SOUND_IN_DMA\26SCC_DMA\25DSP_DMA\24M2R_DMA\23R2M_DMA\22SCC\21REMOTE\20BUS\17DSP_4\16DISK|C16_VIDEO\15SCSI\14PRINTER\13ENETX\12ENETR\11SOUND_OVRUN\10PHONE\07DSP_3\06VIDEO\05MONITOR\04KYBD_MOUSE\03POWER\02SOFTINT1\01SOFTINT0" 401 402 /* 403 * Internal IO space: 404 * 405 * Ranges from 0x400000 to 0x600000 (IIOMAPSIZE). 406 * 407 * Internal IO space is mapped in the kernel from ``intiobase'' to 408 * ``intiolimit'' (defined in locore.s). Since it is always mapped, 409 * conversion between physical and kernel virtual addresses is easy. 410 */ 411 #define ISIIOVA(va) \ 412 ((char *)(va) >= intiobase && (char *)(va) < intiolimit) 413 #define IIOV(pa) ((int)(pa)-INTIOBASE+(int)intiobase) 414 #define IIOP(va) ((int)(va)-(int)intiobase+INTIOBASE) 415 #define IIOPOFF(pa) ((int)(pa)-INTIOBASE) 416 #define IIOMAPSIZE btoc(INTIOTOP-INTIOBASE) /* 2mb */ 417 418 /* mono fb space */ 419 #define ISMONOVA(va) \ 420 ((char *)(va) >= monobase && (char *)(va) < monolimit) 421 #define MONOV(pa) ((int)(pa)-MONOBASE+(int)monobase) 422 #define MONOP(va) ((int)(va)-(int)monobase+MONOBASE) 423 #define MONOPOFF(pa) ((int)(pa)-MONOBASE) 424 #define MONOMAPSIZE btoc(MONOTOP-MONOBASE) /* who cares */ 425 426 /* color fb space */ 427 #define ISCOLORVA(va) \ 428 ((char *)(va) >= colorbase && (char *)(va) < colorlimit) 429 #define COLORV(pa) ((int)(pa)-COLORBASE+(int)colorbase) 430 #define COLORP(va) ((int)(va)-(int)colorbase+COLORBASE) 431 #define COLORPOFF(pa) ((int)(pa)-COLORBASE) 432 #define COLORMAPSIZE btoc(COLORTOP-COLORBASE) /* who cares */ 433 434 #endif /* _CPU_MACHINE_ */ 435
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