cpu.h revision 1.18.8.4
1 /* $NetBSD: cpu.h,v 1.18.8.4 2002/06/20 03:40:22 nathanw Exp $ */ 2 3 /* 4 * Copyright (c) 1988 University of Utah. 5 * Copyright (c) 1982, 1990, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * the Systems Programming Group of the University of Utah Computer 10 * Science Department. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the University of 23 * California, Berkeley and its contributors. 24 * 4. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * from: Utah $Hdr: cpu.h 1.16 91/03/25$ 41 * 42 * @(#)cpu.h 8.4 (Berkeley) 1/5/94 43 */ 44 45 46 #ifndef _CPU_MACHINE_ 47 #define _CPU_MACHINE_ 48 49 #if defined(_KERNEL_OPT) 50 #include "opt_lockdebug.h" 51 #endif 52 53 /* 54 * Exported definitions unique to next68k/68k cpu support. 55 */ 56 57 /* 58 * Get common m68k definitions. 59 */ 60 #include <m68k/cpu.h> 61 62 #define M68K_MMU_MOTOROLA 63 64 /* 65 * Get interrupt glue. 66 */ 67 #include <machine/intr.h> 68 69 #include <sys/sched.h> 70 struct cpu_info { 71 struct schedstate_percpu ci_schedstate; /* scheduler state */ 72 #if defined(DIAGNOSTIC) || defined(LOCKDEBUG) 73 u_long ci_spin_locks; /* # of spin locks held */ 74 u_long ci_simple_locks; /* # of simple locks held */ 75 #endif 76 }; 77 78 #ifdef _KERNEL 79 extern struct cpu_info cpu_info_store; 80 81 #define curcpu() (&cpu_info_store) 82 83 /* 84 * definitions of cpu-dependent requirements 85 * referenced in generic code 86 */ 87 #define cpu_swapin(p) /* nothing */ 88 #define cpu_wait(p) /* nothing */ 89 #define cpu_swapout(p) /* nothing */ 90 #define cpu_number() 0 91 #define cpu_proc_fork(p1, p2) /* nothing */ 92 93 /* 94 * Arguments to hardclock and gatherstats encapsulate the previous 95 * machine state in an opaque clockframe. One the hp300, we use 96 * what the hardware pushes on an interrupt (frame format 0). 97 */ 98 struct clockframe { 99 u_short sr; /* sr at time of interrupt */ 100 u_long pc; /* pc at time of interrupt */ 101 u_short vo; /* vector offset (4-word frame) */ 102 } __attribute__((packed)); 103 104 #define CLKF_USERMODE(framep) (((framep)->sr & PSL_S) == 0) 105 #define CLKF_BASEPRI(framep) (((framep)->sr & PSL_IPL) == 0) 106 #define CLKF_PC(framep) ((framep)->pc) 107 #if 0 108 /* We would like to do it this way... */ 109 #define CLKF_INTR(framep) (((framep)->sr & PSL_M) == 0) 110 #else 111 /* but until we start using PSL_M, we have to do this instead */ 112 #define CLKF_INTR(framep) (0) /* XXX */ 113 #endif 114 115 /* 116 * Preempt the current process if in interrupt from user mode, 117 * or after the current trap/syscall if in system mode. 118 */ 119 extern int want_resched; /* resched() was called */ 120 #define need_resched(ci) { want_resched = 1; aston(); } 121 122 /* 123 * Give a profiling tick to the current process when the user profiling 124 * buffer pages are invalid. On the sun3, request an ast to send us 125 * through trap, marking the proc as needing a profiling tick. 126 */ 127 #define need_proftick(p) ((p)->p_flag |= P_OWEUPC, aston()) 128 129 /* 130 * Notify the current process (p) that it has a signal pending, 131 * process as soon as possible. 132 */ 133 #define signotify(p) aston() 134 135 #define aston() (astpending++) 136 137 extern int astpending; /* need to trap before returning to user mode */ 138 extern int want_resched; /* resched() was called */ 139 140 extern volatile char *intiobase; 141 extern volatile char *intiolimit; 142 extern volatile char *monobase; 143 extern volatile char *monolimit; 144 extern volatile char *colorbase; 145 extern volatile char *colorlimit; 146 extern void (*vectab[]) __P((void)); 147 148 struct frame; 149 struct fpframe; 150 struct pcb; 151 152 /* locore.s functions */ 153 void m68881_save __P((struct fpframe *)); 154 void m68881_restore __P((struct fpframe *)); 155 #if 0 /* it's already in m68k/m68k.h */ 156 u_long getdfc __P((void)); 157 u_long getsfc __P((void)); 158 #endif 159 160 #if 0 /* {@@@ Use cacheops.h? */ 161 162 void DCIA __P((void)); 163 void DCIS __P((void)); 164 void DCIU __P((void)); 165 void ICIA __P((void)); 166 void ICPA __P((void)); 167 void PCIA __P((void)); 168 void TBIA __P((void)); 169 void TBIS __P((vm_offset_t)); 170 void TBIAS __P((void)); 171 void TBIAU __P((void)); 172 #if defined(M68040) 173 void DCFA __P((void)); 174 void DCFP __P((vm_offset_t)); 175 void DCFL __P((vm_offset_t)); 176 void DCPL __P((vm_offset_t)); 177 void DCPP __P((vm_offset_t)); 178 void ICPL __P((vm_offset_t)); 179 void ICPP __P((vm_offset_t)); 180 #endif 181 #endif /* }@@@ use m68k/cacheops.c */ 182 183 int suline __P((caddr_t, caddr_t)); 184 void savectx __P((struct pcb *)); 185 void switch_exit __P((struct lwp *)); 186 void switch_lwp_exit __P((struct lwp *)); 187 void proc_trampoline __P((void)); 188 void loadustp __P((int)); 189 190 void doboot __P((void)) __attribute__((__noreturn__)); 191 192 /* sys_machdep.c functions */ 193 int cachectl1 __P((unsigned long, vaddr_t, size_t, struct proc *)); 194 195 /* clock.c functions */ 196 void next68k_calibrate_delay __P((void)); 197 198 #endif /* _KERNEL */ 199 200 #define NEXT_RAMBASE (0x4000000) /* really depends on slot, but... */ 201 #define NEXT_BANKSIZE (0x1000000) /* Size of a memory bank in physical address */ 202 203 #if 0 204 /* @@@ this needs to be fixed to work on 030's */ 205 #define NEXT_SLOT_ID 0x0 206 #ifdef M68030 207 #define NEXT_SLOT_ID_BMAP 0x0 208 #endif /* M68030 */ 209 #endif 210 #ifdef M68040 211 #ifdef DISABLE_NEXT_BMAP_CHIP /* @@@ For turbo testing */ 212 #define NEXT_SLOT_ID_BMAP 0x0 213 #else 214 #define NEXT_SLOT_ID_BMAP 0x00100000 215 #endif 216 #define NEXT_SLOT_ID 0x0 217 #endif /* M68040 */ 218 219 /****************************************************************/ 220 221 /* Eventually, I'd like to move these defines off into 222 * configure somewhere 223 * Darrin B Jewell <jewell (at) mit.edu> Thu Feb 5 03:50:58 1998 224 */ 225 /* ROM */ 226 #define NEXT_P_EPROM (NEXT_SLOT_ID+0x00000000) 227 #define NEXT_P_EPROM_BMAP (NEXT_SLOT_ID+0x01000000) 228 #define NEXT_P_EPROM_SIZE (128 * 1024) 229 230 /* device space */ 231 #define NEXT_P_DEV_SPACE (NEXT_SLOT_ID+0x02000000) 232 #define NEXT_P_DEV_BMAP (NEXT_SLOT_ID+0x02100000) 233 #define NEXT_DEV_SPACE_SIZE 0x0001c000 234 235 /* DMA control/status (writes MUST be 32-bit) */ 236 #define NEXT_P_SCSI_CSR (NEXT_SLOT_ID+0x02000010) 237 #define NEXT_P_SOUNDOUT_CSR (NEXT_SLOT_ID+0x02000040) 238 #define NEXT_P_DISK_CSR (NEXT_SLOT_ID+0x02000050) 239 #define NEXT_P_SOUNDIN_CSR (NEXT_SLOT_ID+0x02000080) 240 #define NEXT_P_PRINTER_CSR (NEXT_SLOT_ID+0x02000090) 241 #define NEXT_P_SCC_CSR (NEXT_SLOT_ID+0x020000c0) 242 #define NEXT_P_DSP_CSR (NEXT_SLOT_ID+0x020000d0) 243 #define NEXT_P_ENETX_CSR (NEXT_SLOT_ID+0x02000110) 244 #define NEXT_P_ENETR_CSR (NEXT_SLOT_ID+0x02000150) 245 #define NEXT_P_VIDEO_CSR (NEXT_SLOT_ID+0x02000180) 246 #define NEXT_P_M2R_CSR (NEXT_SLOT_ID+0x020001d0) 247 #define NEXT_P_R2M_CSR (NEXT_SLOT_ID+0x020001c0) 248 249 /* DMA scratch pad (writes MUST be 32-bit) */ 250 #define NEXT_P_VIDEO_SPAD (NEXT_SLOT_ID+0x02004180) 251 #define NEXT_P_EVENT_SPAD (NEXT_SLOT_ID+0x0200418c) 252 #define NEXT_P_M2M_SPAD (NEXT_SLOT_ID+0x020041e0) 253 254 /* device registers */ 255 #define NEXT_P_ENET (NEXT_SLOT_ID_BMAP+0x02006000) 256 #define NEXT_P_DSP (NEXT_SLOT_ID_BMAP+0x02008000) 257 #define NEXT_P_MON (NEXT_SLOT_ID+0x0200e000) 258 #define NEXT_P_PRINTER (NEXT_SLOT_ID+0x0200f000) 259 #define NEXT_P_DISK (NEXT_SLOT_ID_BMAP+0x02012000) 260 #define NEXT_P_SCSI (NEXT_SLOT_ID_BMAP+0x02014000) 261 #define NEXT_P_FLOPPY (NEXT_SLOT_ID_BMAP+0x02014100) 262 #define NEXT_P_TIMER (NEXT_SLOT_ID_BMAP+0x02016000) 263 #define NEXT_P_TIMER_CSR (NEXT_SLOT_ID_BMAP+0x02016004) 264 #define NEXT_P_SCC (NEXT_SLOT_ID_BMAP+0x02018000) 265 #define NEXT_P_SCC_CLK (NEXT_SLOT_ID_BMAP+0x02018004) 266 #define NEXT_P_EVENTC (NEXT_SLOT_ID_BMAP+0x0201a000) 267 #define NEXT_P_BMAP (NEXT_SLOT_ID+0x020c0000) 268 /* All COLOR_FB registers are 1 byte wide */ 269 #define NEXT_P_C16_DAC_0 (NEXT_SLOT_ID_BMAP+0x02018100) /* COLOR_FB - RAMDAC */ 270 #define NEXT_P_C16_DAC_1 (NEXT_SLOT_ID_BMAP+0x02018101) 271 #define NEXT_P_C16_DAC_2 (NEXT_SLOT_ID_BMAP+0x02018102) 272 #define NEXT_P_C16_DAC_3 (NEXT_SLOT_ID_BMAP+0x02018103) 273 #define NEXT_P_C16_CMD_REG (NEXT_SLOT_ID_BMAP+0x02018180) /* COLOR_FB - CSR */ 274 275 /* system control registers */ 276 #define NEXT_P_MEMTIMING (NEXT_SLOT_ID_BMAP+0x02006010) 277 #define NEXT_P_INTRSTAT (NEXT_SLOT_ID+0x02007000) 278 #define NEXT_P_INTRSTAT_CON 0x02007000 279 #define NEXT_P_INTRMASK (NEXT_SLOT_ID+0x02007800) 280 #define NEXT_P_INTRMASK_CON 0x02007800 281 #define NEXT_P_SCR1 (NEXT_SLOT_ID+0x0200c000) 282 #define NEXT_P_SCR1_CON 0x0200c000 283 #define NEXT_P_SID 0x0200c800 /* NOT slot-relative */ 284 #define NEXT_P_SCR2 (NEXT_SLOT_ID+0x0200d000) 285 #define NEXT_P_SCR2_CON 0x0200d000 286 #define NEXT_P_RMTINT (NEXT_SLOT_ID+0x0200d800) 287 #define NEXT_P_BRIGHTNESS (NEXT_SLOT_ID_BMAP+0x02010000) 288 #define NEXT_P_DRAM_TIMING (NEXT_SLOT_ID_BMAP+0x02018190) /* Warp 9C memory ctlr */ 289 #define NEXT_P_VRAM_TIMING (NEXT_SLOT_ID_BMAP+0x02018198) /* Warp 9C memory ctlr */ 290 291 /* memory */ 292 #define NEXT_P_MAINMEM (NEXT_SLOT_ID+0x04000000) 293 #define NEXT_P_MEMSIZE 0x04000000 294 #define NEXT_P_VIDEOMEM (NEXT_SLOT_ID+0x0b000000) 295 #define NEXT_P_VIDEOSIZE 0x0003a800 296 #if 0 297 #define NEXT_P_C16_VIDEOMEM (NEXT_SLOT_ID+0x06000000) /* COLOR_FB */ 298 #endif 299 #define NEXT_P_C16_VIDEOMEM (0x2c000000) 300 #define NEXT_P_C16_VIDEOSIZE 0x001D4000 /* COLOR_FB */ 301 #define NEXT_P_WF4VIDEO (NEXT_SLOT_ID+0x0c000000) /* w A+B-AB function */ 302 #define NEXT_P_WF3VIDEO (NEXT_SLOT_ID+0x0d000000) /* w (1-A)B function */ 303 #define NEXT_P_WF2VIDEO (NEXT_SLOT_ID+0x0e000000) /* w ceil(A+B) function */ 304 #define NEXT_P_WF1VIDEO (NEXT_SLOT_ID+0x0f000000) /* w AB function */ 305 #define NEXT_P_WF4MEM (NEXT_SLOT_ID+0x10000000) /* w A+B-AB function */ 306 #define NEXT_P_WF3MEM (NEXT_SLOT_ID+0x14000000) /* w (1-A)B function */ 307 #define NEXT_P_WF2MEM (NEXT_SLOT_ID+0x18000000) /* w ceil(A+B) function */ 308 #define NEXT_P_WF1MEM (NEXT_SLOT_ID+0x1c000000) /* w AB function */ 309 #define NEXT_NMWF 4 /* # of memory write funcs */ 310 311 /* 312 * Interrupt structure. 313 * BASE and BITS define the origin and length of the bit field in the 314 * interrupt status/mask register for the particular interrupt level. 315 * The first component of the interrupt device name indicates the bit 316 * position in the interrupt status and mask registers; the second is the 317 * interrupt level; the third is the bit index relative to the start of the 318 * bit field. 319 */ 320 #define NEXT_I(l,i,b) (((b) << 8) | ((l) << 4) | (i)) 321 #define NEXT_I_INDEX(i) ((i) & 0xf) 322 #define NEXT_I_IPL(i) (((i) >> 4) & 7) 323 #define NEXT_I_BIT(i) ( 1 << (((i) >> 8) & 0x1f)) 324 325 #define NEXT_I_IPL7_BASE 0 326 #define NEXT_I_IPL7_BITS 2 327 #define NEXT_I_NMI NEXT_I(7,0,31) 328 #define NEXT_I_PFAIL NEXT_I(7,1,30) 329 330 #define NEXT_I_IPL6_BASE 2 331 #define NEXT_I_IPL6_BITS 12 332 #define NEXT_I_TIMER NEXT_I(6,0,29) 333 #define NEXT_I_ENETX_DMA NEXT_I(6,1,28) 334 #define NEXT_I_ENETR_DMA NEXT_I(6,2,27) 335 #define NEXT_I_SCSI_DMA NEXT_I(6,3,26) 336 #define NEXT_I_DISK_DMA NEXT_I(6,4,25) 337 #define NEXT_I_PRINTER_DMA NEXT_I(6,5,24) 338 #define NEXT_I_SOUND_OUT_DMA NEXT_I(6,6,23) 339 #define NEXT_I_SOUND_IN_DMA NEXT_I(6,7,22) 340 #define NEXT_I_SCC_DMA NEXT_I(6,8,21) 341 #define NEXT_I_DSP_DMA NEXT_I(6,9,20) 342 #define NEXT_I_M2R_DMA NEXT_I(6,10,19) 343 #define NEXT_I_R2M_DMA NEXT_I(6,11,18) 344 345 #define NEXT_I_IPL5_BASE 14 346 #define NEXT_I_IPL5_BITS 3 347 #define NEXT_I_SCC NEXT_I(5,0,17) 348 #define NEXT_I_REMOTE NEXT_I(5,1,16) 349 #define NEXT_I_BUS NEXT_I(5,2,15) 350 351 #define NEXT_I_IPL4_BASE 17 352 #define NEXT_I_IPL4_BITS 1 353 #define NEXT_I_DSP_4 NEXT_I(4,0,14) 354 355 #define NEXT_I_IPL3_BASE 18 356 #define NEXT_I_IPL3_BITS 12 357 #define NEXT_I_DISK NEXT_I(3,0,13) 358 #define NEXT_I_C16_VIDEO NEXT_I(3,0,13) /* COLOR_FB - Steals old ESDI interrupt */ 359 #define NEXT_I_SCSI NEXT_I(3,1,12) 360 #define NEXT_I_PRINTER NEXT_I(3,2,11) 361 #define NEXT_I_ENETX NEXT_I(3,3,10) 362 #define NEXT_I_ENETR NEXT_I(3,4,9) 363 #define NEXT_I_SOUND_OVRUN NEXT_I(3,5,8) 364 #define NEXT_I_PHONE NEXT_I(3,6,7) 365 #define NEXT_I_DSP_3 NEXT_I(3,7,6) 366 #define NEXT_I_VIDEO NEXT_I(3,8,5) 367 #define NEXT_I_MONITOR NEXT_I(3,9,4) 368 #define NEXT_I_KYBD_MOUSE NEXT_I(3,10,3) 369 #define NEXT_I_POWER NEXT_I(3,11,2) 370 371 #define NEXT_I_IPL2_BASE 30 372 #define NEXT_I_IPL2_BITS 1 373 #define NEXT_I_SOFTINT1 NEXT_I(2,0,1) 374 375 #define NEXT_I_IPL1_BASE 31 376 #define NEXT_I_IPL1_BITS 1 377 #define NEXT_I_SOFTINT0 NEXT_I(1,0,0) 378 379 /****************************************************************/ 380 381 /* physical memory sections */ 382 #if 0 383 #define ROMBASE (0x00000000) 384 #endif 385 386 #define INTIOBASE (0x02000000) 387 #define INTIOTOP (0x02120000) 388 #define MONOBASE (0x0b000000) 389 #define MONOTOP (0x0b03a800) 390 #define COLORBASE (0x2c000000) 391 #define COLORTOP (0x2c1D4000) 392 393 #define NEXT_INTR_BITS \ 394 "\20\40NMI\37PFAIL\36TIMER\35ENETX_DMA\34ENETR_DMA\33SCSI_DMA\32DISK_DMA\31PRINTER_DMA\30SOUND_OUT_DMA\27SOUND_IN_DMA\26SCC_DMA\25DSP_DMA\24M2R_DMA\23R2M_DMA\22SCC\21REMOTE\20BUS\17DSP_4\16DISK|C16_VIDEO\15SCSI\14PRINTER\13ENETX\12ENETR\11SOUND_OVRUN\10PHONE\07DSP_3\06VIDEO\05MONITOR\04KYBD_MOUSE\03POWER\02SOFTINT1\01SOFTINT0" 395 396 /* 397 * Internal IO space: 398 * 399 * Ranges from 0x400000 to 0x600000 (IIOMAPSIZE). 400 * 401 * Internal IO space is mapped in the kernel from ``intiobase'' to 402 * ``intiolimit'' (defined in locore.s). Since it is always mapped, 403 * conversion between physical and kernel virtual addresses is easy. 404 */ 405 #define ISIIOVA(va) \ 406 ((char *)(va) >= intiobase && (char *)(va) < intiolimit) 407 #define IIOV(pa) ((int)(pa)-INTIOBASE+(int)intiobase) 408 #define IIOP(va) ((int)(va)-(int)intiobase+INTIOBASE) 409 #define IIOPOFF(pa) ((int)(pa)-INTIOBASE) 410 #define IIOMAPSIZE btoc(INTIOTOP-INTIOBASE) /* 2mb */ 411 412 /* mono fb space */ 413 #define ISMONOVA(va) \ 414 ((char *)(va) >= monobase && (char *)(va) < monolimit) 415 #define MONOV(pa) ((int)(pa)-MONOBASE+(int)monobase) 416 #define MONOP(va) ((int)(va)-(int)monobase+MONOBASE) 417 #define MONOPOFF(pa) ((int)(pa)-MONOBASE) 418 #define MONOMAPSIZE btoc(MONOTOP-MONOBASE) /* who cares */ 419 420 /* color fb space */ 421 #define ISCOLORVA(va) \ 422 ((char *)(va) >= colorbase && (char *)(va) < colorlimit) 423 #define COLORV(pa) ((int)(pa)-COLORBASE+(int)colorbase) 424 #define COLORP(va) ((int)(va)-(int)colorbase+COLORBASE) 425 #define COLORPOFF(pa) ((int)(pa)-COLORBASE) 426 #define COLORMAPSIZE btoc(COLORTOP-COLORBASE) /* who cares */ 427 428 #endif /* _CPU_MACHINE_ */ 429
Indexes created Tue Oct 14 15:09:51 GMT 2025