cpu.h revision 1.21
1 /* $NetBSD: cpu.h,v 1.21 2002/10/20 02:37:32 chs Exp $ */ 2 3 /* 4 * Copyright (c) 1988 University of Utah. 5 * Copyright (c) 1982, 1990, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * the Systems Programming Group of the University of Utah Computer 10 * Science Department. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the University of 23 * California, Berkeley and its contributors. 24 * 4. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * from: Utah $Hdr: cpu.h 1.16 91/03/25$ 41 * 42 * @(#)cpu.h 8.4 (Berkeley) 1/5/94 43 */ 44 45 46 #ifndef _MACHINE_CPU_H_ 47 #define _MACHINE_CPU_H_ 48 49 #if defined(_KERNEL_OPT) 50 #include "opt_lockdebug.h" 51 #endif 52 53 /* 54 * Exported definitions unique to next68k/68k cpu support. 55 */ 56 57 /* 58 * Get common m68k definitions. 59 */ 60 #include <m68k/cpu.h> 61 62 #define M68K_MMU_MOTOROLA 63 64 /* 65 * Get interrupt glue. 66 */ 67 #include <machine/intr.h> 68 69 #include <sys/sched.h> 70 struct cpu_info { 71 struct schedstate_percpu ci_schedstate; /* scheduler state */ 72 #if defined(DIAGNOSTIC) || defined(LOCKDEBUG) 73 u_long ci_spin_locks; /* # of spin locks held */ 74 u_long ci_simple_locks; /* # of simple locks held */ 75 #endif 76 }; 77 78 #ifdef _KERNEL 79 extern struct cpu_info cpu_info_store; 80 81 #define curcpu() (&cpu_info_store) 82 83 /* 84 * definitions of cpu-dependent requirements 85 * referenced in generic code 86 */ 87 #define cpu_swapin(p) /* nothing */ 88 #define cpu_wait(p) /* nothing */ 89 #define cpu_swapout(p) /* nothing */ 90 #define cpu_number() 0 91 92 /* 93 * Arguments to hardclock and gatherstats encapsulate the previous 94 * machine state in an opaque clockframe. One the hp300, we use 95 * what the hardware pushes on an interrupt (frame format 0). 96 */ 97 struct clockframe { 98 u_short sr; /* sr at time of interrupt */ 99 u_long pc; /* pc at time of interrupt */ 100 u_short fmt:4, 101 vec:12; /* vector offset (4-word frame) */ 102 } __attribute__((packed)); 103 104 #define CLKF_USERMODE(framep) (((framep)->sr & PSL_S) == 0) 105 #define CLKF_BASEPRI(framep) (((framep)->sr & PSL_IPL) == 0) 106 #define CLKF_PC(framep) ((framep)->pc) 107 108 /* 109 * The clock interrupt handler can determine if it's a nested 110 * interrupt by checking for interrupt_depth > 1. 111 * (Remember, the clock interrupt handler itself will cause the 112 * depth counter to be incremented). 113 */ 114 extern volatile unsigned int interrupt_depth; 115 #define CLKF_INTR(framep) (interrupt_depth > 1) 116 117 /* 118 * Preempt the current process if in interrupt from user mode, 119 * or after the current trap/syscall if in system mode. 120 */ 121 extern int want_resched; /* resched() was called */ 122 #define need_resched(ci) { want_resched = 1; aston(); } 123 124 /* 125 * Give a profiling tick to the current process when the user profiling 126 * buffer pages are invalid. On the sun3, request an ast to send us 127 * through trap, marking the proc as needing a profiling tick. 128 */ 129 #define need_proftick(p) ((p)->p_flag |= P_OWEUPC, aston()) 130 131 /* 132 * Notify the current process (p) that it has a signal pending, 133 * process as soon as possible. 134 */ 135 #define signotify(p) aston() 136 137 #define aston() (astpending++) 138 139 extern int astpending; /* need to trap before returning to user mode */ 140 extern int want_resched; /* resched() was called */ 141 142 extern void (*vectab[]) __P((void)); 143 144 struct frame; 145 struct fpframe; 146 struct pcb; 147 148 /* locore.s functions */ 149 void m68881_save __P((struct fpframe *)); 150 void m68881_restore __P((struct fpframe *)); 151 152 int suline __P((caddr_t, caddr_t)); 153 void savectx __P((struct pcb *)); 154 void switch_exit __P((struct proc *)); 155 void proc_trampoline __P((void)); 156 void loadustp __P((int)); 157 158 void doboot __P((void)) __attribute__((__noreturn__)); 159 int nmihand __P((void *)); 160 161 /* sys_machdep.c functions */ 162 int cachectl1 __P((unsigned long, vaddr_t, size_t, struct proc *)); 163 164 /* vm_machdep.c functions */ 165 void physaccess __P((caddr_t, caddr_t, int, int)); 166 void physunaccess __P((caddr_t, int)); 167 int kvtop __P((caddr_t)); 168 169 /* clock.c functions */ 170 void next68k_calibrate_delay __P((void)); 171 172 #endif /* _KERNEL */ 173 174 #define NEXT_RAMBASE (0x4000000) /* really depends on slot, but... */ 175 #define NEXT_BANKSIZE (0x1000000) /* Size of a memory bank in physical address */ 176 177 #if 0 178 /* @@@ this needs to be fixed to work on 030's */ 179 #define NEXT_SLOT_ID 0x0 180 #ifdef M68030 181 #define NEXT_SLOT_ID_BMAP 0x0 182 #endif /* M68030 */ 183 #endif 184 #ifdef M68040 185 #ifdef DISABLE_NEXT_BMAP_CHIP /* @@@ For turbo testing */ 186 #define NEXT_SLOT_ID_BMAP 0x0 187 #else 188 #define NEXT_SLOT_ID_BMAP 0x00100000 189 #endif 190 #define NEXT_SLOT_ID 0x0 191 #endif /* M68040 */ 192 193 /****************************************************************/ 194 195 /* Eventually, I'd like to move these defines off into 196 * configure somewhere 197 * Darrin B Jewell <jewell (at) mit.edu> Thu Feb 5 03:50:58 1998 198 */ 199 /* ROM */ 200 #define NEXT_P_EPROM (NEXT_SLOT_ID+0x00000000) 201 #define NEXT_P_EPROM_BMAP (NEXT_SLOT_ID+0x01000000) 202 #define NEXT_P_EPROM_SIZE (128 * 1024) 203 204 /* device space */ 205 #define NEXT_P_DEV_SPACE (NEXT_SLOT_ID+0x02000000) 206 #define NEXT_P_DEV_BMAP (NEXT_SLOT_ID+0x02100000) 207 #define NEXT_DEV_SPACE_SIZE 0x0001c000 208 209 /* DMA control/status (writes MUST be 32-bit) */ 210 #define NEXT_P_SCSI_CSR (NEXT_SLOT_ID+0x02000010) 211 #define NEXT_P_SOUNDOUT_CSR (NEXT_SLOT_ID+0x02000040) 212 #define NEXT_P_DISK_CSR (NEXT_SLOT_ID+0x02000050) 213 #define NEXT_P_SOUNDIN_CSR (NEXT_SLOT_ID+0x02000080) 214 #define NEXT_P_PRINTER_CSR (NEXT_SLOT_ID+0x02000090) 215 #define NEXT_P_SCC_CSR (NEXT_SLOT_ID+0x020000c0) 216 #define NEXT_P_DSP_CSR (NEXT_SLOT_ID+0x020000d0) 217 #define NEXT_P_ENETX_CSR (NEXT_SLOT_ID+0x02000110) 218 #define NEXT_P_ENETR_CSR (NEXT_SLOT_ID+0x02000150) 219 #define NEXT_P_VIDEO_CSR (NEXT_SLOT_ID+0x02000180) 220 #define NEXT_P_M2R_CSR (NEXT_SLOT_ID+0x020001d0) 221 #define NEXT_P_R2M_CSR (NEXT_SLOT_ID+0x020001c0) 222 223 /* DMA scratch pad (writes MUST be 32-bit) */ 224 #define NEXT_P_VIDEO_SPAD (NEXT_SLOT_ID+0x02004180) 225 #define NEXT_P_EVENT_SPAD (NEXT_SLOT_ID+0x0200418c) 226 #define NEXT_P_M2M_SPAD (NEXT_SLOT_ID+0x020041e0) 227 228 /* device registers */ 229 #define NEXT_P_ENET (NEXT_SLOT_ID_BMAP+0x02006000) 230 #define NEXT_P_DSP (NEXT_SLOT_ID_BMAP+0x02008000) 231 #define NEXT_P_MON (NEXT_SLOT_ID+0x0200e000) 232 #define NEXT_P_PRINTER (NEXT_SLOT_ID+0x0200f000) 233 #define NEXT_P_DISK (NEXT_SLOT_ID_BMAP+0x02012000) 234 #define NEXT_P_SCSI (NEXT_SLOT_ID_BMAP+0x02014000) 235 #define NEXT_P_FLOPPY (NEXT_SLOT_ID_BMAP+0x02014100) 236 #define NEXT_P_TIMER (NEXT_SLOT_ID_BMAP+0x02016000) 237 #define NEXT_P_TIMER_CSR (NEXT_SLOT_ID_BMAP+0x02016004) 238 #define NEXT_P_SCC (NEXT_SLOT_ID_BMAP+0x02018000) 239 #define NEXT_P_SCC_CLK (NEXT_SLOT_ID_BMAP+0x02018004) 240 #define NEXT_P_EVENTC (NEXT_SLOT_ID_BMAP+0x0201a000) 241 #define NEXT_P_BMAP (NEXT_SLOT_ID+0x020c0000) 242 /* All COLOR_FB registers are 1 byte wide */ 243 #define NEXT_P_C16_DAC_0 (NEXT_SLOT_ID_BMAP+0x02018100) /* COLOR_FB - RAMDAC */ 244 #define NEXT_P_C16_DAC_1 (NEXT_SLOT_ID_BMAP+0x02018101) 245 #define NEXT_P_C16_DAC_2 (NEXT_SLOT_ID_BMAP+0x02018102) 246 #define NEXT_P_C16_DAC_3 (NEXT_SLOT_ID_BMAP+0x02018103) 247 #define NEXT_P_C16_CMD_REG (NEXT_SLOT_ID_BMAP+0x02018180) /* COLOR_FB - CSR */ 248 249 /* system control registers */ 250 #define NEXT_P_MEMTIMING (NEXT_SLOT_ID_BMAP+0x02006010) 251 #define NEXT_P_INTRSTAT (NEXT_SLOT_ID+0x02007000) 252 #define NEXT_P_INTRSTAT_CON 0x02007000 253 /* #define NEXT_P_INTRSTAT_0 (NEXT_SLOT_ID+0x02008000) */ 254 #define NEXT_P_INTRMASK (NEXT_SLOT_ID+0x02007800) 255 #define NEXT_P_INTRMASK_CON 0x02007800 256 /* #define NEXT_P_INTRMASK_0 (NEXT_SLOT_ID+0x0200a000) */ 257 #define NEXT_P_SCR1 (NEXT_SLOT_ID+0x0200c000) 258 #define NEXT_P_SCR1_CON 0x0200c000 259 #define NEXT_P_SID 0x0200c800 /* NOT slot-relative */ 260 #define NEXT_P_SCR2 (NEXT_SLOT_ID+0x0200d000) 261 #define NEXT_P_SCR2_CON 0x0200d000 262 #define NEXT_P_RMTINT (NEXT_SLOT_ID+0x0200d800) 263 #define NEXT_P_BRIGHTNESS (NEXT_SLOT_ID_BMAP+0x02010000) 264 #define NEXT_P_DRAM_TIMING (NEXT_SLOT_ID_BMAP+0x02018190) /* Warp 9C memory ctlr */ 265 #define NEXT_P_VRAM_TIMING (NEXT_SLOT_ID_BMAP+0x02018198) /* Warp 9C memory ctlr */ 266 267 /* memory */ 268 #define NEXT_P_MAINMEM (NEXT_SLOT_ID+0x04000000) 269 #define NEXT_P_MEMSIZE 0x04000000 270 #define NEXT_P_VIDEOMEM (NEXT_SLOT_ID+0x0b000000) 271 #define NEXT_P_VIDEOSIZE 0x0003a800 272 #if 0 273 #define NEXT_P_C16_VIDEOMEM (NEXT_SLOT_ID+0x06000000) /* COLOR_FB */ 274 #endif 275 #define NEXT_P_C16_VIDEOMEM (0x2c000000) 276 #define NEXT_P_C16_VIDEOSIZE 0x001D4000 /* COLOR_FB */ 277 #define NEXT_P_WF4VIDEO (NEXT_SLOT_ID+0x0c000000) /* w A+B-AB function */ 278 #define NEXT_P_WF3VIDEO (NEXT_SLOT_ID+0x0d000000) /* w (1-A)B function */ 279 #define NEXT_P_WF2VIDEO (NEXT_SLOT_ID+0x0e000000) /* w ceil(A+B) function */ 280 #define NEXT_P_WF1VIDEO (NEXT_SLOT_ID+0x0f000000) /* w AB function */ 281 #define NEXT_P_WF4MEM (NEXT_SLOT_ID+0x10000000) /* w A+B-AB function */ 282 #define NEXT_P_WF3MEM (NEXT_SLOT_ID+0x14000000) /* w (1-A)B function */ 283 #define NEXT_P_WF2MEM (NEXT_SLOT_ID+0x18000000) /* w ceil(A+B) function */ 284 #define NEXT_P_WF1MEM (NEXT_SLOT_ID+0x1c000000) /* w AB function */ 285 #define NEXT_NMWF 4 /* # of memory write funcs */ 286 287 /* 288 * Interrupt structure. 289 * BASE and BITS define the origin and length of the bit field in the 290 * interrupt status/mask register for the particular interrupt level. 291 * The first component of the interrupt device name indicates the bit 292 * position in the interrupt status and mask registers; the second is the 293 * interrupt level; the third is the bit index relative to the start of the 294 * bit field. 295 */ 296 #define NEXT_I(l,i,b) (((b) << 8) | ((l) << 4) | (i)) 297 #define NEXT_I_INDEX(i) ((i) & 0xf) 298 #define NEXT_I_IPL(i) (((i) >> 4) & 7) 299 #define NEXT_I_BIT(i) ( 1 << (((i) >> 8) & 0x1f)) 300 301 #define NEXT_I_IPL7_BASE 0 302 #define NEXT_I_IPL7_BITS 2 303 #define NEXT_I_NMI NEXT_I(7,0,31) 304 #define NEXT_I_PFAIL NEXT_I(7,1,30) 305 306 #define NEXT_I_IPL6_BASE 2 307 #define NEXT_I_IPL6_BITS 12 308 #define NEXT_I_TIMER NEXT_I(6,0,29) 309 #define NEXT_I_ENETX_DMA NEXT_I(6,1,28) 310 #define NEXT_I_ENETR_DMA NEXT_I(6,2,27) 311 #define NEXT_I_SCSI_DMA NEXT_I(6,3,26) 312 #define NEXT_I_DISK_DMA NEXT_I(6,4,25) 313 #define NEXT_I_PRINTER_DMA NEXT_I(6,5,24) 314 #define NEXT_I_SOUND_OUT_DMA NEXT_I(6,6,23) 315 #define NEXT_I_SOUND_IN_DMA NEXT_I(6,7,22) 316 #define NEXT_I_SCC_DMA NEXT_I(6,8,21) 317 #define NEXT_I_DSP_DMA NEXT_I(6,9,20) 318 #define NEXT_I_M2R_DMA NEXT_I(6,10,19) 319 #define NEXT_I_R2M_DMA NEXT_I(6,11,18) 320 321 #define NEXT_I_IPL5_BASE 14 322 #define NEXT_I_IPL5_BITS 3 323 #define NEXT_I_SCC NEXT_I(5,0,17) 324 #define NEXT_I_REMOTE NEXT_I(5,1,16) 325 #define NEXT_I_BUS NEXT_I(5,2,15) 326 327 #define NEXT_I_IPL4_BASE 17 328 #define NEXT_I_IPL4_BITS 1 329 #define NEXT_I_DSP_4 NEXT_I(4,0,14) 330 331 #define NEXT_I_IPL3_BASE 18 332 #define NEXT_I_IPL3_BITS 12 333 #define NEXT_I_DISK NEXT_I(3,0,13) 334 #define NEXT_I_C16_VIDEO NEXT_I(3,0,13) /* COLOR_FB - Steals old ESDI interrupt */ 335 #define NEXT_I_SCSI NEXT_I(3,1,12) 336 #define NEXT_I_PRINTER NEXT_I(3,2,11) 337 #define NEXT_I_ENETX NEXT_I(3,3,10) 338 #define NEXT_I_ENETR NEXT_I(3,4,9) 339 #define NEXT_I_SOUND_OVRUN NEXT_I(3,5,8) 340 #define NEXT_I_PHONE NEXT_I(3,6,7) 341 #define NEXT_I_DSP_3 NEXT_I(3,7,6) 342 #define NEXT_I_VIDEO NEXT_I(3,8,5) 343 #define NEXT_I_MONITOR NEXT_I(3,9,4) 344 #define NEXT_I_KYBD_MOUSE NEXT_I(3,10,3) 345 #define NEXT_I_POWER NEXT_I(3,11,2) 346 347 #define NEXT_I_IPL2_BASE 30 348 #define NEXT_I_IPL2_BITS 1 349 #define NEXT_I_SOFTINT1 NEXT_I(2,0,1) 350 351 #define NEXT_I_IPL1_BASE 31 352 #define NEXT_I_IPL1_BITS 1 353 #define NEXT_I_SOFTINT0 NEXT_I(1,0,0) 354 355 /****************************************************************/ 356 357 /* physical memory sections */ 358 #if 0 359 #define ROMBASE (0x00000000) 360 #endif 361 362 #define INTIOBASE (0x02000000) 363 #define INTIOTOP (0x02120000) 364 #define MONOBASE (0x0b000000) 365 #define MONOTOP (0x0b03a800) 366 #define COLORBASE (0x2c000000) 367 #define COLORTOP (0x2c1D4000) 368 369 #define NEXT_INTR_BITS \ 370 "\20\40NMI\37PFAIL\36TIMER\35ENETX_DMA\34ENETR_DMA\33SCSI_DMA\32DISK_DMA\31PRINTER_DMA\30SOUND_OUT_DMA\27SOUND_IN_DMA\26SCC_DMA\25DSP_DMA\24M2R_DMA\23R2M_DMA\22SCC\21REMOTE\20BUS\17DSP_4\16DISK|C16_VIDEO\15SCSI\14PRINTER\13ENETX\12ENETR\11SOUND_OVRUN\10PHONE\07DSP_3\06VIDEO\05MONITOR\04KYBD_MOUSE\03POWER\02SOFTINT1\01SOFTINT0" 371 372 /* 373 * Internal IO space: 374 * 375 * Ranges from 0x400000 to 0x600000 (IIOMAPSIZE). 376 * 377 * Internal IO space is mapped in the kernel from ``intiobase'' to 378 * ``intiolimit'' (defined in locore.s). Since it is always mapped, 379 * conversion between physical and kernel virtual addresses is easy. 380 */ 381 #define ISIIOVA(va) \ 382 ((char *)(va) >= intiobase && (char *)(va) < intiolimit) 383 #define IIOV(pa) ((int)(pa)-INTIOBASE+(int)intiobase) 384 #define IIOP(va) ((int)(va)-(int)intiobase+INTIOBASE) 385 #define IIOPOFF(pa) ((int)(pa)-INTIOBASE) 386 #define IIOMAPSIZE btoc(INTIOTOP-INTIOBASE) /* 2mb */ 387 388 /* mono fb space */ 389 #define ISMONOVA(va) \ 390 ((char *)(va) >= monobase && (char *)(va) < monolimit) 391 #define MONOV(pa) ((int)(pa)-MONOBASE+(int)monobase) 392 #define MONOP(va) ((int)(va)-(int)monobase+MONOBASE) 393 #define MONOPOFF(pa) ((int)(pa)-MONOBASE) 394 #define MONOMAPSIZE btoc(MONOTOP-MONOBASE) /* who cares */ 395 396 /* color fb space */ 397 #define ISCOLORVA(va) \ 398 ((char *)(va) >= colorbase && (char *)(va) < colorlimit) 399 #define COLORV(pa) ((int)(pa)-COLORBASE+(int)colorbase) 400 #define COLORP(va) ((int)(va)-(int)colorbase+COLORBASE) 401 #define COLORPOFF(pa) ((int)(pa)-COLORBASE) 402 #define COLORMAPSIZE btoc(COLORTOP-COLORBASE) /* who cares */ 403 404 #endif /* _MACHINE_CPU_H_ */ 405
Indexes created Mon Sep 22 13:09:51 GMT 2025