cpu.h revision 1.27
1 /* $NetBSD: cpu.h,v 1.27 2004/09/22 11:32:03 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 1982, 1990, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * the Systems Programming Group of the University of Utah Computer 9 * Science Department. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * from: Utah $Hdr: cpu.h 1.16 91/03/25$ 36 * 37 * @(#)cpu.h 8.4 (Berkeley) 1/5/94 38 */ 39 /* 40 * Copyright (c) 1988 University of Utah. 41 * 42 * This code is derived from software contributed to Berkeley by 43 * the Systems Programming Group of the University of Utah Computer 44 * Science Department. 45 * 46 * Redistribution and use in source and binary forms, with or without 47 * modification, are permitted provided that the following conditions 48 * are met: 49 * 1. Redistributions of source code must retain the above copyright 50 * notice, this list of conditions and the following disclaimer. 51 * 2. Redistributions in binary form must reproduce the above copyright 52 * notice, this list of conditions and the following disclaimer in the 53 * documentation and/or other materials provided with the distribution. 54 * 3. All advertising materials mentioning features or use of this software 55 * must display the following acknowledgement: 56 * This product includes software developed by the University of 57 * California, Berkeley and its contributors. 58 * 4. Neither the name of the University nor the names of its contributors 59 * may be used to endorse or promote products derived from this software 60 * without specific prior written permission. 61 * 62 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 63 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 64 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 65 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 66 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 67 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 68 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 69 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 70 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 71 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 72 * SUCH DAMAGE. 73 * 74 * from: Utah $Hdr: cpu.h 1.16 91/03/25$ 75 * 76 * @(#)cpu.h 8.4 (Berkeley) 1/5/94 77 */ 78 79 80 #ifndef _MACHINE_CPU_H_ 81 #define _MACHINE_CPU_H_ 82 83 #if defined(_KERNEL_OPT) 84 #include "opt_lockdebug.h" 85 #endif 86 87 /* 88 * Exported definitions unique to next68k/68k cpu support. 89 */ 90 91 /* 92 * Get common m68k definitions. 93 */ 94 #include <m68k/cpu.h> 95 96 #define M68K_MMU_MOTOROLA 97 98 /* 99 * Get interrupt glue. 100 */ 101 #include <machine/intr.h> 102 103 #include <sys/cpu_data.h> 104 struct cpu_info { 105 struct cpu_data ci_data; /* MI per-cpu data */ 106 }; 107 108 #ifdef _KERNEL 109 extern struct cpu_info cpu_info_store; 110 111 #define curcpu() (&cpu_info_store) 112 113 /* 114 * definitions of cpu-dependent requirements 115 * referenced in generic code 116 */ 117 #define cpu_swapin(p) /* nothing */ 118 #define cpu_swapout(p) /* nothing */ 119 #define cpu_number() 0 120 121 void cpu_proc_fork(struct proc *, struct proc *); 122 123 124 /* 125 * Arguments to hardclock and gatherstats encapsulate the previous 126 * machine state in an opaque clockframe. One the hp300, we use 127 * what the hardware pushes on an interrupt (frame format 0). 128 */ 129 struct clockframe { 130 u_short sr; /* sr at time of interrupt */ 131 u_long pc; /* pc at time of interrupt */ 132 u_short fmt:4, 133 vec:12; /* vector offset (4-word frame) */ 134 } __attribute__((packed)); 135 136 #define CLKF_USERMODE(framep) (((framep)->sr & PSL_S) == 0) 137 #define CLKF_BASEPRI(framep) (((framep)->sr & PSL_IPL) == 0) 138 #define CLKF_PC(framep) ((framep)->pc) 139 140 /* 141 * The clock interrupt handler can determine if it's a nested 142 * interrupt by checking for interrupt_depth > 1. 143 * (Remember, the clock interrupt handler itself will cause the 144 * depth counter to be incremented). 145 */ 146 extern volatile unsigned int interrupt_depth; 147 #define CLKF_INTR(framep) (interrupt_depth > 1) 148 149 /* 150 * Preempt the current process if in interrupt from user mode, 151 * or after the current trap/syscall if in system mode. 152 */ 153 extern int want_resched; /* resched() was called */ 154 #define need_resched(ci) { want_resched = 1; aston(); } 155 156 /* 157 * Give a profiling tick to the current process when the user profiling 158 * buffer pages are invalid. On the sun3, request an ast to send us 159 * through trap, marking the proc as needing a profiling tick. 160 */ 161 #define need_proftick(p) ((p)->p_flag |= P_OWEUPC, aston()) 162 163 /* 164 * Notify the current process (p) that it has a signal pending, 165 * process as soon as possible. 166 */ 167 #define signotify(p) aston() 168 169 #define aston() (astpending++) 170 171 extern int astpending; /* need to trap before returning to user mode */ 172 extern int want_resched; /* resched() was called */ 173 174 extern void (*vectab[]) __P((void)); 175 176 struct frame; 177 struct fpframe; 178 struct pcb; 179 180 /* locore.s functions */ 181 void m68881_save __P((struct fpframe *)); 182 void m68881_restore __P((struct fpframe *)); 183 184 int suline __P((caddr_t, caddr_t)); 185 void savectx __P((struct pcb *)); 186 void switch_exit __P((struct lwp *)); 187 void switch_lwp_exit __P((struct lwp *)); 188 void proc_trampoline __P((void)); 189 void loadustp __P((int)); 190 191 void doboot __P((void)) __attribute__((__noreturn__)); 192 int nmihand __P((void *)); 193 194 /* sys_machdep.c functions */ 195 int cachectl1 __P((unsigned long, vaddr_t, size_t, struct proc *)); 196 197 /* vm_machdep.c functions */ 198 void physaccess __P((caddr_t, caddr_t, int, int)); 199 void physunaccess __P((caddr_t, int)); 200 int kvtop __P((caddr_t)); 201 202 /* clock.c functions */ 203 void next68k_calibrate_delay __P((void)); 204 205 #endif /* _KERNEL */ 206 207 #define NEXT_RAMBASE (0x4000000) /* really depends on slot, but... */ 208 #define NEXT_BANKSIZE (0x1000000) /* Size of a memory bank in physical address */ 209 210 #if 0 211 /* @@@ this needs to be fixed to work on 030's */ 212 #define NEXT_SLOT_ID 0x0 213 #ifdef M68030 214 #define NEXT_SLOT_ID_BMAP 0x0 215 #endif /* M68030 */ 216 #endif 217 #ifdef M68040 218 #ifdef DISABLE_NEXT_BMAP_CHIP /* @@@ For turbo testing */ 219 #define NEXT_SLOT_ID_BMAP 0x0 220 #else 221 #define NEXT_SLOT_ID_BMAP 0x00100000 222 #endif 223 #define NEXT_SLOT_ID 0x0 224 #endif /* M68040 */ 225 226 /****************************************************************/ 227 228 /* Eventually, I'd like to move these defines off into 229 * configure somewhere 230 * Darrin B Jewell <jewell (at) mit.edu> Thu Feb 5 03:50:58 1998 231 */ 232 /* ROM */ 233 #define NEXT_P_EPROM (NEXT_SLOT_ID+0x00000000) 234 #define NEXT_P_EPROM_BMAP (NEXT_SLOT_ID+0x01000000) 235 #define NEXT_P_EPROM_SIZE (128 * 1024) 236 237 /* device space */ 238 #define NEXT_P_DEV_SPACE (NEXT_SLOT_ID+0x02000000) 239 #define NEXT_P_DEV_BMAP (NEXT_SLOT_ID+0x02100000) 240 #define NEXT_DEV_SPACE_SIZE 0x0001c000 241 242 /* DMA control/status (writes MUST be 32-bit) */ 243 #define NEXT_P_SCSI_CSR (NEXT_SLOT_ID+0x02000010) 244 #define NEXT_P_SOUNDOUT_CSR (NEXT_SLOT_ID+0x02000040) 245 #define NEXT_P_DISK_CSR (NEXT_SLOT_ID+0x02000050) 246 #define NEXT_P_SOUNDIN_CSR (NEXT_SLOT_ID+0x02000080) 247 #define NEXT_P_PRINTER_CSR (NEXT_SLOT_ID+0x02000090) 248 #define NEXT_P_SCC_CSR (NEXT_SLOT_ID+0x020000c0) 249 #define NEXT_P_DSP_CSR (NEXT_SLOT_ID+0x020000d0) 250 #define NEXT_P_ENETX_CSR (NEXT_SLOT_ID+0x02000110) 251 #define NEXT_P_ENETR_CSR (NEXT_SLOT_ID+0x02000150) 252 #define NEXT_P_VIDEO_CSR (NEXT_SLOT_ID+0x02000180) 253 #define NEXT_P_M2R_CSR (NEXT_SLOT_ID+0x020001d0) 254 #define NEXT_P_R2M_CSR (NEXT_SLOT_ID+0x020001c0) 255 256 /* DMA scratch pad (writes MUST be 32-bit) */ 257 #define NEXT_P_VIDEO_SPAD (NEXT_SLOT_ID+0x02004180) 258 #define NEXT_P_EVENT_SPAD (NEXT_SLOT_ID+0x0200418c) 259 #define NEXT_P_M2M_SPAD (NEXT_SLOT_ID+0x020041e0) 260 261 /* device registers */ 262 #define NEXT_P_ENET (NEXT_SLOT_ID_BMAP+0x02006000) 263 #define NEXT_P_DSP (NEXT_SLOT_ID_BMAP+0x02008000) 264 #define NEXT_P_MON (NEXT_SLOT_ID+0x0200e000) 265 #define NEXT_P_PRINTER (NEXT_SLOT_ID+0x0200f000) 266 #define NEXT_P_DISK (NEXT_SLOT_ID_BMAP+0x02012000) 267 #define NEXT_P_SCSI (NEXT_SLOT_ID_BMAP+0x02014000) 268 #define NEXT_P_FLOPPY (NEXT_SLOT_ID_BMAP+0x02014100) 269 #define NEXT_P_TIMER (NEXT_SLOT_ID_BMAP+0x02016000) 270 #define NEXT_P_TIMER_CSR (NEXT_SLOT_ID_BMAP+0x02016004) 271 #define NEXT_P_SCC (NEXT_SLOT_ID_BMAP+0x02018000) 272 #define NEXT_P_SCC_CLK (NEXT_SLOT_ID_BMAP+0x02018004) 273 #define NEXT_P_EVENTC (NEXT_SLOT_ID_BMAP+0x0201a000) 274 #define NEXT_P_BMAP (NEXT_SLOT_ID+0x020c0000) 275 /* All COLOR_FB registers are 1 byte wide */ 276 #define NEXT_P_C16_DAC_0 (NEXT_SLOT_ID_BMAP+0x02018100) /* COLOR_FB - RAMDAC */ 277 #define NEXT_P_C16_DAC_1 (NEXT_SLOT_ID_BMAP+0x02018101) 278 #define NEXT_P_C16_DAC_2 (NEXT_SLOT_ID_BMAP+0x02018102) 279 #define NEXT_P_C16_DAC_3 (NEXT_SLOT_ID_BMAP+0x02018103) 280 #define NEXT_P_C16_CMD_REG (NEXT_SLOT_ID_BMAP+0x02018180) /* COLOR_FB - CSR */ 281 282 /* system control registers */ 283 #define NEXT_P_MEMTIMING (NEXT_SLOT_ID_BMAP+0x02006010) 284 #define NEXT_P_INTRSTAT (NEXT_SLOT_ID+0x02007000) 285 #define NEXT_P_INTRSTAT_CON 0x02007000 286 /* #define NEXT_P_INTRSTAT_0 (NEXT_SLOT_ID+0x02008000) */ 287 #define NEXT_P_INTRMASK (NEXT_SLOT_ID+0x02007800) 288 #define NEXT_P_INTRMASK_CON 0x02007800 289 /* #define NEXT_P_INTRMASK_0 (NEXT_SLOT_ID+0x0200a000) */ 290 #define NEXT_P_SCR1 (NEXT_SLOT_ID+0x0200c000) 291 #define NEXT_P_SCR1_CON 0x0200c000 292 #define NEXT_P_SID 0x0200c800 /* NOT slot-relative */ 293 #define NEXT_P_SCR2 (NEXT_SLOT_ID+0x0200d000) 294 #define NEXT_P_SCR2_CON 0x0200d000 295 #define NEXT_P_RMTINT (NEXT_SLOT_ID+0x0200d800) 296 #define NEXT_P_BRIGHTNESS (NEXT_SLOT_ID_BMAP+0x02010000) 297 #define NEXT_P_DRAM_TIMING (NEXT_SLOT_ID_BMAP+0x02018190) /* Warp 9C memory ctlr */ 298 #define NEXT_P_VRAM_TIMING (NEXT_SLOT_ID_BMAP+0x02018198) /* Warp 9C memory ctlr */ 299 300 /* memory */ 301 #define NEXT_P_MAINMEM (NEXT_SLOT_ID+0x04000000) 302 #define NEXT_P_MEMSIZE 0x04000000 303 #define NEXT_P_VIDEOMEM (NEXT_SLOT_ID+0x0b000000) 304 #define NEXT_P_VIDEOSIZE 0x0003a800 305 #if 0 306 #define NEXT_P_C16_VIDEOMEM (NEXT_SLOT_ID+0x06000000) /* COLOR_FB */ 307 #endif 308 #define NEXT_P_C16_VIDEOMEM (0x2c000000) 309 #define NEXT_P_C16_VIDEOSIZE 0x001D4000 /* COLOR_FB */ 310 #define NEXT_P_WF4VIDEO (NEXT_SLOT_ID+0x0c000000) /* w A+B-AB function */ 311 #define NEXT_P_WF3VIDEO (NEXT_SLOT_ID+0x0d000000) /* w (1-A)B function */ 312 #define NEXT_P_WF2VIDEO (NEXT_SLOT_ID+0x0e000000) /* w ceil(A+B) function */ 313 #define NEXT_P_WF1VIDEO (NEXT_SLOT_ID+0x0f000000) /* w AB function */ 314 #define NEXT_P_WF4MEM (NEXT_SLOT_ID+0x10000000) /* w A+B-AB function */ 315 #define NEXT_P_WF3MEM (NEXT_SLOT_ID+0x14000000) /* w (1-A)B function */ 316 #define NEXT_P_WF2MEM (NEXT_SLOT_ID+0x18000000) /* w ceil(A+B) function */ 317 #define NEXT_P_WF1MEM (NEXT_SLOT_ID+0x1c000000) /* w AB function */ 318 #define NEXT_NMWF 4 /* # of memory write funcs */ 319 320 /* 321 * Interrupt structure. 322 * BASE and BITS define the origin and length of the bit field in the 323 * interrupt status/mask register for the particular interrupt level. 324 * The first component of the interrupt device name indicates the bit 325 * position in the interrupt status and mask registers; the second is the 326 * interrupt level; the third is the bit index relative to the start of the 327 * bit field. 328 */ 329 #define NEXT_I(l,i,b) (((b) << 8) | ((l) << 4) | (i)) 330 #define NEXT_I_INDEX(i) ((i) & 0xf) 331 #define NEXT_I_IPL(i) (((i) >> 4) & 7) 332 #define NEXT_I_BIT(i) ( 1 << (((i) >> 8) & 0x1f)) 333 334 #define NEXT_I_IPL7_BASE 0 335 #define NEXT_I_IPL7_BITS 2 336 #define NEXT_I_NMI NEXT_I(7,0,31) 337 #define NEXT_I_PFAIL NEXT_I(7,1,30) 338 339 #define NEXT_I_IPL6_BASE 2 340 #define NEXT_I_IPL6_BITS 12 341 #define NEXT_I_TIMER NEXT_I(6,0,29) 342 #define NEXT_I_ENETX_DMA NEXT_I(6,1,28) 343 #define NEXT_I_ENETR_DMA NEXT_I(6,2,27) 344 #define NEXT_I_SCSI_DMA NEXT_I(6,3,26) 345 #define NEXT_I_DISK_DMA NEXT_I(6,4,25) 346 #define NEXT_I_PRINTER_DMA NEXT_I(6,5,24) 347 #define NEXT_I_SOUND_OUT_DMA NEXT_I(6,6,23) 348 #define NEXT_I_SOUND_IN_DMA NEXT_I(6,7,22) 349 #define NEXT_I_SCC_DMA NEXT_I(6,8,21) 350 #define NEXT_I_DSP_DMA NEXT_I(6,9,20) 351 #define NEXT_I_M2R_DMA NEXT_I(6,10,19) 352 #define NEXT_I_R2M_DMA NEXT_I(6,11,18) 353 354 #define NEXT_I_IPL5_BASE 14 355 #define NEXT_I_IPL5_BITS 3 356 #define NEXT_I_SCC NEXT_I(5,0,17) 357 #define NEXT_I_REMOTE NEXT_I(5,1,16) 358 #define NEXT_I_BUS NEXT_I(5,2,15) 359 360 #define NEXT_I_IPL4_BASE 17 361 #define NEXT_I_IPL4_BITS 1 362 #define NEXT_I_DSP_4 NEXT_I(4,0,14) 363 364 #define NEXT_I_IPL3_BASE 18 365 #define NEXT_I_IPL3_BITS 12 366 #define NEXT_I_DISK NEXT_I(3,0,13) 367 #define NEXT_I_C16_VIDEO NEXT_I(3,0,13) /* COLOR_FB - Steals old ESDI interrupt */ 368 #define NEXT_I_SCSI NEXT_I(3,1,12) 369 #define NEXT_I_PRINTER NEXT_I(3,2,11) 370 #define NEXT_I_ENETX NEXT_I(3,3,10) 371 #define NEXT_I_ENETR NEXT_I(3,4,9) 372 #define NEXT_I_SOUND_OVRUN NEXT_I(3,5,8) 373 #define NEXT_I_PHONE NEXT_I(3,6,7) 374 #define NEXT_I_DSP_3 NEXT_I(3,7,6) 375 #define NEXT_I_VIDEO NEXT_I(3,8,5) 376 #define NEXT_I_MONITOR NEXT_I(3,9,4) 377 #define NEXT_I_KYBD_MOUSE NEXT_I(3,10,3) 378 #define NEXT_I_POWER NEXT_I(3,11,2) 379 380 #define NEXT_I_IPL2_BASE 30 381 #define NEXT_I_IPL2_BITS 1 382 #define NEXT_I_SOFTINT1 NEXT_I(2,0,1) 383 384 #define NEXT_I_IPL1_BASE 31 385 #define NEXT_I_IPL1_BITS 1 386 #define NEXT_I_SOFTINT0 NEXT_I(1,0,0) 387 388 /****************************************************************/ 389 390 /* physical memory sections */ 391 #if 0 392 #define ROMBASE (0x00000000) 393 #endif 394 395 #define INTIOBASE (0x02000000) 396 #define INTIOTOP (0x02120000) 397 #define MONOBASE (0x0b000000) 398 #define MONOTOP (0x0b03a800) 399 #define COLORBASE (0x2c000000) 400 #define COLORTOP (0x2c1D4000) 401 402 #define NEXT_INTR_BITS \ 403 "\20\40NMI\37PFAIL\36TIMER\35ENETX_DMA\34ENETR_DMA\33SCSI_DMA\32DISK_DMA\31PRINTER_DMA\30SOUND_OUT_DMA\27SOUND_IN_DMA\26SCC_DMA\25DSP_DMA\24M2R_DMA\23R2M_DMA\22SCC\21REMOTE\20BUS\17DSP_4\16DISK|C16_VIDEO\15SCSI\14PRINTER\13ENETX\12ENETR\11SOUND_OVRUN\10PHONE\07DSP_3\06VIDEO\05MONITOR\04KYBD_MOUSE\03POWER\02SOFTINT1\01SOFTINT0" 404 405 /* 406 * Internal IO space: 407 * 408 * Ranges from 0x400000 to 0x600000 (IIOMAPSIZE). 409 * 410 * Internal IO space is mapped in the kernel from ``intiobase'' to 411 * ``intiolimit'' (defined in locore.s). Since it is always mapped, 412 * conversion between physical and kernel virtual addresses is easy. 413 */ 414 #define IIOV(pa) ((int)(pa)-INTIOBASE+intiobase) 415 #define IIOP(va) ((int)(va)-intiobase+INTIOBASE) 416 #define IIOMAPSIZE btoc(INTIOTOP-INTIOBASE) /* 2mb */ 417 418 /* mono fb space */ 419 #define MONOMAPSIZE btoc(MONOTOP-MONOBASE) /* who cares */ 420 421 /* color fb space */ 422 #define COLORMAPSIZE btoc(COLORTOP-COLORBASE) /* who cares */ 423 424 #endif /* _MACHINE_CPU_H_ */ 425
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