cpu.h revision 1.31
1 /* $NetBSD: cpu.h,v 1.31 2007/02/09 21:55:07 ad Exp $ */ 2 3 /* 4 * Copyright (c) 1982, 1990, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * the Systems Programming Group of the University of Utah Computer 9 * Science Department. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * from: Utah $Hdr: cpu.h 1.16 91/03/25$ 36 * 37 * @(#)cpu.h 8.4 (Berkeley) 1/5/94 38 */ 39 /* 40 * Copyright (c) 1988 University of Utah. 41 * 42 * This code is derived from software contributed to Berkeley by 43 * the Systems Programming Group of the University of Utah Computer 44 * Science Department. 45 * 46 * Redistribution and use in source and binary forms, with or without 47 * modification, are permitted provided that the following conditions 48 * are met: 49 * 1. Redistributions of source code must retain the above copyright 50 * notice, this list of conditions and the following disclaimer. 51 * 2. Redistributions in binary form must reproduce the above copyright 52 * notice, this list of conditions and the following disclaimer in the 53 * documentation and/or other materials provided with the distribution. 54 * 3. All advertising materials mentioning features or use of this software 55 * must display the following acknowledgement: 56 * This product includes software developed by the University of 57 * California, Berkeley and its contributors. 58 * 4. Neither the name of the University nor the names of its contributors 59 * may be used to endorse or promote products derived from this software 60 * without specific prior written permission. 61 * 62 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 63 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 64 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 65 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 66 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 67 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 68 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 69 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 70 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 71 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 72 * SUCH DAMAGE. 73 * 74 * from: Utah $Hdr: cpu.h 1.16 91/03/25$ 75 * 76 * @(#)cpu.h 8.4 (Berkeley) 1/5/94 77 */ 78 79 80 #ifndef _MACHINE_CPU_H_ 81 #define _MACHINE_CPU_H_ 82 83 #if defined(_KERNEL) 84 85 #if defined(_KERNEL_OPT) 86 #include "opt_lockdebug.h" 87 #endif 88 89 /* 90 * Exported definitions unique to next68k/68k cpu support. 91 */ 92 93 /* 94 * Get common m68k definitions. 95 */ 96 #include <m68k/cpu.h> 97 98 #define M68K_MMU_MOTOROLA 99 100 /* 101 * Get interrupt glue. 102 */ 103 #include <machine/intr.h> 104 105 #include <sys/cpu_data.h> 106 struct cpu_info { 107 struct cpu_data ci_data; /* MI per-cpu data */ 108 int ci_mtx_count; 109 int ci_mtx_oldspl; 110 }; 111 112 extern struct cpu_info cpu_info_store; 113 114 #define curcpu() (&cpu_info_store) 115 116 /* 117 * definitions of cpu-dependent requirements 118 * referenced in generic code 119 */ 120 #define cpu_swapin(p) /* nothing */ 121 #define cpu_swapout(p) /* nothing */ 122 #define cpu_number() 0 123 124 void cpu_proc_fork(struct proc *, struct proc *); 125 126 127 /* 128 * Arguments to hardclock and gatherstats encapsulate the previous 129 * machine state in an opaque clockframe. One the hp300, we use 130 * what the hardware pushes on an interrupt (frame format 0). 131 */ 132 struct clockframe { 133 u_short sr; /* sr at time of interrupt */ 134 u_long pc; /* pc at time of interrupt */ 135 u_short fmt:4, 136 vec:12; /* vector offset (4-word frame) */ 137 } __attribute__((packed)); 138 139 #define CLKF_USERMODE(framep) (((framep)->sr & PSL_S) == 0) 140 #define CLKF_BASEPRI(framep) (((framep)->sr & PSL_IPL) == 0) 141 #define CLKF_PC(framep) ((framep)->pc) 142 143 /* 144 * The clock interrupt handler can determine if it's a nested 145 * interrupt by checking for interrupt_depth > 1. 146 * (Remember, the clock interrupt handler itself will cause the 147 * depth counter to be incremented). 148 */ 149 extern volatile unsigned int interrupt_depth; 150 #define CLKF_INTR(framep) (interrupt_depth > 1) 151 152 /* 153 * Preempt the current process if in interrupt from user mode, 154 * or after the current trap/syscall if in system mode. 155 */ 156 extern int want_resched; /* resched() was called */ 157 #define cpu_need_resched(ci) { want_resched = 1; aston(); } 158 159 /* 160 * Give a profiling tick to the current process when the user profiling 161 * buffer pages are invalid. On the sun3, request an ast to send us 162 * through trap, marking the proc as needing a profiling tick. 163 */ 164 #define cpu_need_proftick(l) ((l)->l_pflag |= LP_OWEUPC, aston()) 165 166 /* 167 * Notify the current process (p) that it has a signal pending, 168 * process as soon as possible. 169 */ 170 #define cpu_signotify(l) aston() 171 172 #define aston() (astpending++) 173 174 extern int astpending; /* need to trap before returning to user mode */ 175 extern int want_resched; /* resched() was called */ 176 177 extern void (*vectab[])(void); 178 179 struct frame; 180 struct fpframe; 181 struct pcb; 182 183 /* locore.s functions */ 184 void m68881_save(struct fpframe *); 185 void m68881_restore(struct fpframe *); 186 187 int suline(caddr_t, caddr_t); 188 void savectx(struct pcb *); 189 void switch_exit(struct lwp *); 190 void switch_lwp_exit(struct lwp *); 191 void proc_trampoline(void); 192 void loadustp(int); 193 194 void doboot(void) __attribute__((__noreturn__)); 195 int nmihand(void *); 196 197 /* sys_machdep.c functions */ 198 int cachectl1(unsigned long, vaddr_t, size_t, struct proc *); 199 200 /* vm_machdep.c functions */ 201 void physaccess(caddr_t, caddr_t, int, int); 202 void physunaccess(caddr_t, int); 203 int kvtop(caddr_t); 204 205 /* clock.c functions */ 206 void next68k_calibrate_delay(void); 207 208 #endif /* _KERNEL */ 209 210 #define NEXT_RAMBASE (0x4000000) /* really depends on slot, but... */ 211 #define NEXT_BANKSIZE (0x1000000) /* Size of a memory bank in physical address */ 212 213 #if 0 214 /* @@@ this needs to be fixed to work on 030's */ 215 #define NEXT_SLOT_ID 0x0 216 #ifdef M68030 217 #define NEXT_SLOT_ID_BMAP 0x0 218 #endif /* M68030 */ 219 #endif 220 #ifdef M68040 221 #ifdef DISABLE_NEXT_BMAP_CHIP /* @@@ For turbo testing */ 222 #define NEXT_SLOT_ID_BMAP 0x0 223 #else 224 #define NEXT_SLOT_ID_BMAP 0x00100000 225 #endif 226 #define NEXT_SLOT_ID 0x0 227 #endif /* M68040 */ 228 229 /****************************************************************/ 230 231 /* Eventually, I'd like to move these defines off into 232 * configure somewhere 233 * Darrin B Jewell <jewell (at) mit.edu> Thu Feb 5 03:50:58 1998 234 */ 235 /* ROM */ 236 #define NEXT_P_EPROM (NEXT_SLOT_ID+0x00000000) 237 #define NEXT_P_EPROM_BMAP (NEXT_SLOT_ID+0x01000000) 238 #define NEXT_P_EPROM_SIZE (128 * 1024) 239 240 /* device space */ 241 #define NEXT_P_DEV_SPACE (NEXT_SLOT_ID+0x02000000) 242 #define NEXT_P_DEV_BMAP (NEXT_SLOT_ID+0x02100000) 243 #define NEXT_DEV_SPACE_SIZE 0x0001c000 244 245 /* DMA control/status (writes MUST be 32-bit) */ 246 #define NEXT_P_SCSI_CSR (NEXT_SLOT_ID+0x02000010) 247 #define NEXT_P_SOUNDOUT_CSR (NEXT_SLOT_ID+0x02000040) 248 #define NEXT_P_DISK_CSR (NEXT_SLOT_ID+0x02000050) 249 #define NEXT_P_SOUNDIN_CSR (NEXT_SLOT_ID+0x02000080) 250 #define NEXT_P_PRINTER_CSR (NEXT_SLOT_ID+0x02000090) 251 #define NEXT_P_SCC_CSR (NEXT_SLOT_ID+0x020000c0) 252 #define NEXT_P_DSP_CSR (NEXT_SLOT_ID+0x020000d0) 253 #define NEXT_P_ENETX_CSR (NEXT_SLOT_ID+0x02000110) 254 #define NEXT_P_ENETR_CSR (NEXT_SLOT_ID+0x02000150) 255 #define NEXT_P_VIDEO_CSR (NEXT_SLOT_ID+0x02000180) 256 #define NEXT_P_M2R_CSR (NEXT_SLOT_ID+0x020001d0) 257 #define NEXT_P_R2M_CSR (NEXT_SLOT_ID+0x020001c0) 258 259 /* DMA scratch pad (writes MUST be 32-bit) */ 260 #define NEXT_P_VIDEO_SPAD (NEXT_SLOT_ID+0x02004180) 261 #define NEXT_P_EVENT_SPAD (NEXT_SLOT_ID+0x0200418c) 262 #define NEXT_P_M2M_SPAD (NEXT_SLOT_ID+0x020041e0) 263 264 /* device registers */ 265 #define NEXT_P_ENET (NEXT_SLOT_ID_BMAP+0x02006000) 266 #define NEXT_P_DSP (NEXT_SLOT_ID_BMAP+0x02008000) 267 #define NEXT_P_MON (NEXT_SLOT_ID+0x0200e000) 268 #define NEXT_P_PRINTER (NEXT_SLOT_ID+0x0200f000) 269 #define NEXT_P_DISK (NEXT_SLOT_ID_BMAP+0x02012000) 270 #define NEXT_P_SCSI (NEXT_SLOT_ID_BMAP+0x02014000) 271 #define NEXT_P_FLOPPY (NEXT_SLOT_ID_BMAP+0x02014100) 272 #define NEXT_P_TIMER (NEXT_SLOT_ID_BMAP+0x02016000) 273 #define NEXT_P_TIMER_CSR (NEXT_SLOT_ID_BMAP+0x02016004) 274 #define NEXT_P_SCC (NEXT_SLOT_ID_BMAP+0x02018000) 275 #define NEXT_P_SCC_CLK (NEXT_SLOT_ID_BMAP+0x02018004) 276 #define NEXT_P_EVENTC (NEXT_SLOT_ID_BMAP+0x0201a000) 277 #define NEXT_P_BMAP (NEXT_SLOT_ID+0x020c0000) 278 /* All COLOR_FB registers are 1 byte wide */ 279 #define NEXT_P_C16_DAC_0 (NEXT_SLOT_ID_BMAP+0x02018100) /* COLOR_FB - RAMDAC */ 280 #define NEXT_P_C16_DAC_1 (NEXT_SLOT_ID_BMAP+0x02018101) 281 #define NEXT_P_C16_DAC_2 (NEXT_SLOT_ID_BMAP+0x02018102) 282 #define NEXT_P_C16_DAC_3 (NEXT_SLOT_ID_BMAP+0x02018103) 283 #define NEXT_P_C16_CMD_REG (NEXT_SLOT_ID_BMAP+0x02018180) /* COLOR_FB - CSR */ 284 285 /* system control registers */ 286 #define NEXT_P_MEMTIMING (NEXT_SLOT_ID_BMAP+0x02006010) 287 #define NEXT_P_INTRSTAT (NEXT_SLOT_ID+0x02007000) 288 #define NEXT_P_INTRSTAT_CON 0x02007000 289 /* #define NEXT_P_INTRSTAT_0 (NEXT_SLOT_ID+0x02008000) */ 290 #define NEXT_P_INTRMASK (NEXT_SLOT_ID+0x02007800) 291 #define NEXT_P_INTRMASK_CON 0x02007800 292 /* #define NEXT_P_INTRMASK_0 (NEXT_SLOT_ID+0x0200a000) */ 293 #define NEXT_P_SCR1 (NEXT_SLOT_ID+0x0200c000) 294 #define NEXT_P_SCR1_CON 0x0200c000 295 #define NEXT_P_SID 0x0200c800 /* NOT slot-relative */ 296 #define NEXT_P_SCR2 (NEXT_SLOT_ID+0x0200d000) 297 #define NEXT_P_SCR2_CON 0x0200d000 298 #define NEXT_P_RMTINT (NEXT_SLOT_ID+0x0200d800) 299 #define NEXT_P_BRIGHTNESS (NEXT_SLOT_ID_BMAP+0x02010000) 300 #define NEXT_P_DRAM_TIMING (NEXT_SLOT_ID_BMAP+0x02018190) /* Warp 9C memory ctlr */ 301 #define NEXT_P_VRAM_TIMING (NEXT_SLOT_ID_BMAP+0x02018198) /* Warp 9C memory ctlr */ 302 303 /* memory */ 304 #define NEXT_P_MAINMEM (NEXT_SLOT_ID+0x04000000) 305 #define NEXT_P_MEMSIZE 0x04000000 306 #define NEXT_P_VIDEOMEM (NEXT_SLOT_ID+0x0b000000) 307 #define NEXT_P_VIDEOSIZE 0x0003a800 308 #if 0 309 #define NEXT_P_C16_VIDEOMEM (NEXT_SLOT_ID+0x06000000) /* COLOR_FB */ 310 #endif 311 #define NEXT_P_C16_VIDEOMEM (0x2c000000) 312 #define NEXT_P_C16_VIDEOSIZE 0x001D4000 /* COLOR_FB */ 313 #define NEXT_P_WF4VIDEO (NEXT_SLOT_ID+0x0c000000) /* w A+B-AB function */ 314 #define NEXT_P_WF3VIDEO (NEXT_SLOT_ID+0x0d000000) /* w (1-A)B function */ 315 #define NEXT_P_WF2VIDEO (NEXT_SLOT_ID+0x0e000000) /* w ceil(A+B) function */ 316 #define NEXT_P_WF1VIDEO (NEXT_SLOT_ID+0x0f000000) /* w AB function */ 317 #define NEXT_P_WF4MEM (NEXT_SLOT_ID+0x10000000) /* w A+B-AB function */ 318 #define NEXT_P_WF3MEM (NEXT_SLOT_ID+0x14000000) /* w (1-A)B function */ 319 #define NEXT_P_WF2MEM (NEXT_SLOT_ID+0x18000000) /* w ceil(A+B) function */ 320 #define NEXT_P_WF1MEM (NEXT_SLOT_ID+0x1c000000) /* w AB function */ 321 #define NEXT_NMWF 4 /* # of memory write funcs */ 322 323 /* 324 * Interrupt structure. 325 * BASE and BITS define the origin and length of the bit field in the 326 * interrupt status/mask register for the particular interrupt level. 327 * The first component of the interrupt device name indicates the bit 328 * position in the interrupt status and mask registers; the second is the 329 * interrupt level; the third is the bit index relative to the start of the 330 * bit field. 331 */ 332 #define NEXT_I(l,i,b) (((b) << 8) | ((l) << 4) | (i)) 333 #define NEXT_I_INDEX(i) ((i) & 0xf) 334 #define NEXT_I_IPL(i) (((i) >> 4) & 7) 335 #define NEXT_I_BIT(i) ( 1 << (((i) >> 8) & 0x1f)) 336 337 #define NEXT_I_IPL7_BASE 0 338 #define NEXT_I_IPL7_BITS 2 339 #define NEXT_I_NMI NEXT_I(7,0,31) 340 #define NEXT_I_PFAIL NEXT_I(7,1,30) 341 342 #define NEXT_I_IPL6_BASE 2 343 #define NEXT_I_IPL6_BITS 12 344 #define NEXT_I_TIMER NEXT_I(6,0,29) 345 #define NEXT_I_ENETX_DMA NEXT_I(6,1,28) 346 #define NEXT_I_ENETR_DMA NEXT_I(6,2,27) 347 #define NEXT_I_SCSI_DMA NEXT_I(6,3,26) 348 #define NEXT_I_DISK_DMA NEXT_I(6,4,25) 349 #define NEXT_I_PRINTER_DMA NEXT_I(6,5,24) 350 #define NEXT_I_SOUND_OUT_DMA NEXT_I(6,6,23) 351 #define NEXT_I_SOUND_IN_DMA NEXT_I(6,7,22) 352 #define NEXT_I_SCC_DMA NEXT_I(6,8,21) 353 #define NEXT_I_DSP_DMA NEXT_I(6,9,20) 354 #define NEXT_I_M2R_DMA NEXT_I(6,10,19) 355 #define NEXT_I_R2M_DMA NEXT_I(6,11,18) 356 357 #define NEXT_I_IPL5_BASE 14 358 #define NEXT_I_IPL5_BITS 3 359 #define NEXT_I_SCC NEXT_I(5,0,17) 360 #define NEXT_I_REMOTE NEXT_I(5,1,16) 361 #define NEXT_I_BUS NEXT_I(5,2,15) 362 363 #define NEXT_I_IPL4_BASE 17 364 #define NEXT_I_IPL4_BITS 1 365 #define NEXT_I_DSP_4 NEXT_I(4,0,14) 366 367 #define NEXT_I_IPL3_BASE 18 368 #define NEXT_I_IPL3_BITS 12 369 #define NEXT_I_DISK NEXT_I(3,0,13) 370 #define NEXT_I_C16_VIDEO NEXT_I(3,0,13) /* COLOR_FB - Steals old ESDI interrupt */ 371 #define NEXT_I_SCSI NEXT_I(3,1,12) 372 #define NEXT_I_PRINTER NEXT_I(3,2,11) 373 #define NEXT_I_ENETX NEXT_I(3,3,10) 374 #define NEXT_I_ENETR NEXT_I(3,4,9) 375 #define NEXT_I_SOUND_OVRUN NEXT_I(3,5,8) 376 #define NEXT_I_PHONE NEXT_I(3,6,7) 377 #define NEXT_I_DSP_3 NEXT_I(3,7,6) 378 #define NEXT_I_VIDEO NEXT_I(3,8,5) 379 #define NEXT_I_MONITOR NEXT_I(3,9,4) 380 #define NEXT_I_KYBD_MOUSE NEXT_I(3,10,3) 381 #define NEXT_I_POWER NEXT_I(3,11,2) 382 383 #define NEXT_I_IPL2_BASE 30 384 #define NEXT_I_IPL2_BITS 1 385 #define NEXT_I_SOFTINT1 NEXT_I(2,0,1) 386 387 #define NEXT_I_IPL1_BASE 31 388 #define NEXT_I_IPL1_BITS 1 389 #define NEXT_I_SOFTINT0 NEXT_I(1,0,0) 390 391 /****************************************************************/ 392 393 /* physical memory sections */ 394 #if 0 395 #define ROMBASE (0x00000000) 396 #endif 397 398 #define INTIOBASE (0x02000000) 399 #define INTIOTOP (0x02120000) 400 #define MONOBASE (0x0b000000) 401 #define MONOTOP (0x0b03a800) 402 #define COLORBASE (0x2c000000) 403 #define COLORTOP (0x2c1D4000) 404 405 #define NEXT_INTR_BITS \ 406 "\20\40NMI\37PFAIL\36TIMER\35ENETX_DMA\34ENETR_DMA\33SCSI_DMA\32DISK_DMA\31PRINTER_DMA\30SOUND_OUT_DMA\27SOUND_IN_DMA\26SCC_DMA\25DSP_DMA\24M2R_DMA\23R2M_DMA\22SCC\21REMOTE\20BUS\17DSP_4\16DISK|C16_VIDEO\15SCSI\14PRINTER\13ENETX\12ENETR\11SOUND_OVRUN\10PHONE\07DSP_3\06VIDEO\05MONITOR\04KYBD_MOUSE\03POWER\02SOFTINT1\01SOFTINT0" 407 408 /* 409 * Internal IO space: 410 * 411 * Ranges from 0x400000 to 0x600000 (IIOMAPSIZE). 412 * 413 * Internal IO space is mapped in the kernel from ``intiobase'' to 414 * ``intiolimit'' (defined in locore.s). Since it is always mapped, 415 * conversion between physical and kernel virtual addresses is easy. 416 */ 417 #define IIOV(pa) ((int)(pa)-INTIOBASE+intiobase) 418 #define IIOP(va) ((int)(va)-intiobase+INTIOBASE) 419 #define IIOMAPSIZE btoc(INTIOTOP-INTIOBASE) /* 2mb */ 420 421 /* mono fb space */ 422 #define MONOMAPSIZE btoc(MONOTOP-MONOBASE) /* who cares */ 423 424 /* color fb space */ 425 #define COLORMAPSIZE btoc(COLORTOP-COLORBASE) /* who cares */ 426 427 #endif /* _MACHINE_CPU_H_ */ 428
Indexes created Thu Sep 25 16:09:42 GMT 2025