cpu.h revision 1.39
1 /* $NetBSD: cpu.h,v 1.39 2007/08/04 13:00:45 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 1982, 1990, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * the Systems Programming Group of the University of Utah Computer 9 * Science Department. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * from: Utah $Hdr: cpu.h 1.16 91/03/25$ 36 * 37 * @(#)cpu.h 8.4 (Berkeley) 1/5/94 38 */ 39 /* 40 * Copyright (c) 1988 University of Utah. 41 * 42 * This code is derived from software contributed to Berkeley by 43 * the Systems Programming Group of the University of Utah Computer 44 * Science Department. 45 * 46 * Redistribution and use in source and binary forms, with or without 47 * modification, are permitted provided that the following conditions 48 * are met: 49 * 1. Redistributions of source code must retain the above copyright 50 * notice, this list of conditions and the following disclaimer. 51 * 2. Redistributions in binary form must reproduce the above copyright 52 * notice, this list of conditions and the following disclaimer in the 53 * documentation and/or other materials provided with the distribution. 54 * 3. All advertising materials mentioning features or use of this software 55 * must display the following acknowledgement: 56 * This product includes software developed by the University of 57 * California, Berkeley and its contributors. 58 * 4. Neither the name of the University nor the names of its contributors 59 * may be used to endorse or promote products derived from this software 60 * without specific prior written permission. 61 * 62 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 63 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 64 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 65 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 66 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 67 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 68 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 69 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 70 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 71 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 72 * SUCH DAMAGE. 73 * 74 * from: Utah $Hdr: cpu.h 1.16 91/03/25$ 75 * 76 * @(#)cpu.h 8.4 (Berkeley) 1/5/94 77 */ 78 79 80 #ifndef _MACHINE_CPU_H_ 81 #define _MACHINE_CPU_H_ 82 83 #if defined(_KERNEL) 84 85 #if defined(_KERNEL_OPT) 86 #include "opt_lockdebug.h" 87 #endif 88 89 /* 90 * Exported definitions unique to next68k/68k cpu support. 91 */ 92 93 /* 94 * Get common m68k definitions. 95 */ 96 #include <m68k/cpu.h> 97 98 #define M68K_MMU_MOTOROLA 99 100 /* 101 * Get interrupt glue. 102 */ 103 #include <machine/intr.h> 104 105 #include <sys/cpu_data.h> 106 struct cpu_info { 107 struct cpu_data ci_data; /* MI per-cpu data */ 108 cpuid_t ci_cpuid; 109 int ci_mtx_count; 110 int ci_mtx_oldspl; 111 int ci_want_resched; 112 }; 113 114 extern struct cpu_info cpu_info_store; 115 116 #define curcpu() (&cpu_info_store) 117 118 /* 119 * definitions of cpu-dependent requirements 120 * referenced in generic code 121 */ 122 #define cpu_swapin(p) /* nothing */ 123 #define cpu_swapout(p) /* nothing */ 124 #define cpu_number() 0 125 126 void cpu_proc_fork(struct proc *, struct proc *); 127 128 129 /* 130 * Arguments to hardclock and gatherstats encapsulate the previous 131 * machine state in an opaque clockframe. One the hp300, we use 132 * what the hardware pushes on an interrupt (frame format 0). 133 */ 134 struct clockframe { 135 u_short sr; /* sr at time of interrupt */ 136 u_long pc; /* pc at time of interrupt */ 137 u_short fmt:4, 138 vec:12; /* vector offset (4-word frame) */ 139 } __attribute__((packed)); 140 141 #define CLKF_USERMODE(framep) (((framep)->sr & PSL_S) == 0) 142 #define CLKF_PC(framep) ((framep)->pc) 143 144 /* 145 * The clock interrupt handler can determine if it's a nested 146 * interrupt by checking for interrupt_depth > 1. 147 * (Remember, the clock interrupt handler itself will cause the 148 * depth counter to be incremented). 149 */ 150 extern volatile unsigned int interrupt_depth; 151 #define CLKF_INTR(framep) (interrupt_depth > 1) 152 153 /* 154 * Preempt the current process if in interrupt from user mode, 155 * or after the current trap/syscall if in system mode. 156 */ 157 #define cpu_need_resched(ci, flags) \ 158 do { ci->ci_want_resched = 1; aston(); } while (/* CONSTCOND */0) 159 160 /* 161 * Give a profiling tick to the current process when the user profiling 162 * buffer pages are invalid. On the sun3, request an ast to send us 163 * through trap, marking the proc as needing a profiling tick. 164 */ 165 #define cpu_need_proftick(l) ((l)->l_pflag |= LP_OWEUPC, aston()) 166 167 /* 168 * Notify the current process (p) that it has a signal pending, 169 * process as soon as possible. 170 */ 171 #define cpu_signotify(l) aston() 172 173 #define aston() (astpending++) 174 175 extern int astpending; /* need to trap before returning to user mode */ 176 177 extern void (*vectab[])(void); 178 179 struct fpframe; 180 181 /* locore.s functions */ 182 void m68881_save(struct fpframe *); 183 void m68881_restore(struct fpframe *); 184 185 int suline(void *, void *); 186 void loadustp(int); 187 188 void doboot(void) __attribute__((__noreturn__)); 189 int nmihand(void *); 190 191 /* clock.c functions */ 192 void next68k_calibrate_delay(void); 193 194 #endif /* _KERNEL */ 195 196 #define NEXT_RAMBASE (0x4000000) /* really depends on slot, but... */ 197 #define NEXT_BANKSIZE (0x1000000) /* Size of a memory bank in physical address */ 198 199 #if 0 200 /* @@@ this needs to be fixed to work on 030's */ 201 #define NEXT_SLOT_ID 0x0 202 #ifdef M68030 203 #define NEXT_SLOT_ID_BMAP 0x0 204 #endif /* M68030 */ 205 #endif 206 #ifdef M68040 207 #ifdef DISABLE_NEXT_BMAP_CHIP /* @@@ For turbo testing */ 208 #define NEXT_SLOT_ID_BMAP 0x0 209 #else 210 #define NEXT_SLOT_ID_BMAP 0x00100000 211 #endif 212 #define NEXT_SLOT_ID 0x0 213 #endif /* M68040 */ 214 215 /****************************************************************/ 216 217 /* Eventually, I'd like to move these defines off into 218 * configure somewhere 219 * Darrin B Jewell <jewell (at) mit.edu> Thu Feb 5 03:50:58 1998 220 */ 221 /* ROM */ 222 #define NEXT_P_EPROM (NEXT_SLOT_ID+0x00000000) 223 #define NEXT_P_EPROM_BMAP (NEXT_SLOT_ID+0x01000000) 224 #define NEXT_P_EPROM_SIZE (128 * 1024) 225 226 /* device space */ 227 #define NEXT_P_DEV_SPACE (NEXT_SLOT_ID+0x02000000) 228 #define NEXT_P_DEV_BMAP (NEXT_SLOT_ID+0x02100000) 229 #define NEXT_DEV_SPACE_SIZE 0x0001c000 230 231 /* DMA control/status (writes MUST be 32-bit) */ 232 #define NEXT_P_SCSI_CSR (NEXT_SLOT_ID+0x02000010) 233 #define NEXT_P_SOUNDOUT_CSR (NEXT_SLOT_ID+0x02000040) 234 #define NEXT_P_DISK_CSR (NEXT_SLOT_ID+0x02000050) 235 #define NEXT_P_SOUNDIN_CSR (NEXT_SLOT_ID+0x02000080) 236 #define NEXT_P_PRINTER_CSR (NEXT_SLOT_ID+0x02000090) 237 #define NEXT_P_SCC_CSR (NEXT_SLOT_ID+0x020000c0) 238 #define NEXT_P_DSP_CSR (NEXT_SLOT_ID+0x020000d0) 239 #define NEXT_P_ENETX_CSR (NEXT_SLOT_ID+0x02000110) 240 #define NEXT_P_ENETR_CSR (NEXT_SLOT_ID+0x02000150) 241 #define NEXT_P_VIDEO_CSR (NEXT_SLOT_ID+0x02000180) 242 #define NEXT_P_M2R_CSR (NEXT_SLOT_ID+0x020001d0) 243 #define NEXT_P_R2M_CSR (NEXT_SLOT_ID+0x020001c0) 244 245 /* DMA scratch pad (writes MUST be 32-bit) */ 246 #define NEXT_P_VIDEO_SPAD (NEXT_SLOT_ID+0x02004180) 247 #define NEXT_P_EVENT_SPAD (NEXT_SLOT_ID+0x0200418c) 248 #define NEXT_P_M2M_SPAD (NEXT_SLOT_ID+0x020041e0) 249 250 /* device registers */ 251 #define NEXT_P_ENET (NEXT_SLOT_ID_BMAP+0x02006000) 252 #define NEXT_P_DSP (NEXT_SLOT_ID_BMAP+0x02008000) 253 #define NEXT_P_MON (NEXT_SLOT_ID+0x0200e000) 254 #define NEXT_P_PRINTER (NEXT_SLOT_ID+0x0200f000) 255 #define NEXT_P_DISK (NEXT_SLOT_ID_BMAP+0x02012000) 256 #define NEXT_P_SCSI (NEXT_SLOT_ID_BMAP+0x02014000) 257 #define NEXT_P_FLOPPY (NEXT_SLOT_ID_BMAP+0x02014100) 258 #define NEXT_P_TIMER (NEXT_SLOT_ID_BMAP+0x02016000) 259 #define NEXT_P_TIMER_CSR (NEXT_SLOT_ID_BMAP+0x02016004) 260 #define NEXT_P_SCC (NEXT_SLOT_ID_BMAP+0x02018000) 261 #define NEXT_P_SCC_CLK (NEXT_SLOT_ID_BMAP+0x02018004) 262 #define NEXT_P_EVENTC (NEXT_SLOT_ID_BMAP+0x0201a000) 263 #define NEXT_P_BMAP (NEXT_SLOT_ID+0x020c0000) 264 /* All COLOR_FB registers are 1 byte wide */ 265 #define NEXT_P_C16_DAC_0 (NEXT_SLOT_ID_BMAP+0x02018100) /* COLOR_FB - RAMDAC */ 266 #define NEXT_P_C16_DAC_1 (NEXT_SLOT_ID_BMAP+0x02018101) 267 #define NEXT_P_C16_DAC_2 (NEXT_SLOT_ID_BMAP+0x02018102) 268 #define NEXT_P_C16_DAC_3 (NEXT_SLOT_ID_BMAP+0x02018103) 269 #define NEXT_P_C16_CMD_REG (NEXT_SLOT_ID_BMAP+0x02018180) /* COLOR_FB - CSR */ 270 271 /* system control registers */ 272 #define NEXT_P_MEMTIMING (NEXT_SLOT_ID_BMAP+0x02006010) 273 #define NEXT_P_INTRSTAT (NEXT_SLOT_ID+0x02007000) 274 #define NEXT_P_INTRSTAT_CON 0x02007000 275 /* #define NEXT_P_INTRSTAT_0 (NEXT_SLOT_ID+0x02008000) */ 276 #define NEXT_P_INTRMASK (NEXT_SLOT_ID+0x02007800) 277 #define NEXT_P_INTRMASK_CON 0x02007800 278 /* #define NEXT_P_INTRMASK_0 (NEXT_SLOT_ID+0x0200a000) */ 279 #define NEXT_P_SCR1 (NEXT_SLOT_ID+0x0200c000) 280 #define NEXT_P_SCR1_CON 0x0200c000 281 #define NEXT_P_SID 0x0200c800 /* NOT slot-relative */ 282 #define NEXT_P_SCR2 (NEXT_SLOT_ID+0x0200d000) 283 #define NEXT_P_SCR2_CON 0x0200d000 284 #define NEXT_P_RMTINT (NEXT_SLOT_ID+0x0200d800) 285 #define NEXT_P_BRIGHTNESS (NEXT_SLOT_ID_BMAP+0x02010000) 286 #define NEXT_P_DRAM_TIMING (NEXT_SLOT_ID_BMAP+0x02018190) /* Warp 9C memory ctlr */ 287 #define NEXT_P_VRAM_TIMING (NEXT_SLOT_ID_BMAP+0x02018198) /* Warp 9C memory ctlr */ 288 289 /* memory */ 290 #define NEXT_P_MAINMEM (NEXT_SLOT_ID+0x04000000) 291 #define NEXT_P_MEMSIZE 0x04000000 292 #define NEXT_P_VIDEOMEM (NEXT_SLOT_ID+0x0b000000) 293 #define NEXT_P_VIDEOSIZE 0x0003a800 294 #if 0 295 #define NEXT_P_C16_VIDEOMEM (NEXT_SLOT_ID+0x06000000) /* COLOR_FB */ 296 #endif 297 #define NEXT_P_C16_VIDEOMEM (0x2c000000) 298 #define NEXT_P_C16_VIDEOSIZE 0x001D4000 /* COLOR_FB */ 299 #define NEXT_P_WF4VIDEO (NEXT_SLOT_ID+0x0c000000) /* w A+B-AB function */ 300 #define NEXT_P_WF3VIDEO (NEXT_SLOT_ID+0x0d000000) /* w (1-A)B function */ 301 #define NEXT_P_WF2VIDEO (NEXT_SLOT_ID+0x0e000000) /* w ceil(A+B) function */ 302 #define NEXT_P_WF1VIDEO (NEXT_SLOT_ID+0x0f000000) /* w AB function */ 303 #define NEXT_P_WF4MEM (NEXT_SLOT_ID+0x10000000) /* w A+B-AB function */ 304 #define NEXT_P_WF3MEM (NEXT_SLOT_ID+0x14000000) /* w (1-A)B function */ 305 #define NEXT_P_WF2MEM (NEXT_SLOT_ID+0x18000000) /* w ceil(A+B) function */ 306 #define NEXT_P_WF1MEM (NEXT_SLOT_ID+0x1c000000) /* w AB function */ 307 #define NEXT_NMWF 4 /* # of memory write funcs */ 308 309 /* 310 * Interrupt structure. 311 * BASE and BITS define the origin and length of the bit field in the 312 * interrupt status/mask register for the particular interrupt level. 313 * The first component of the interrupt device name indicates the bit 314 * position in the interrupt status and mask registers; the second is the 315 * interrupt level; the third is the bit index relative to the start of the 316 * bit field. 317 */ 318 #define NEXT_I(l,i,b) (((b) << 8) | ((l) << 4) | (i)) 319 #define NEXT_I_INDEX(i) ((i) & 0xf) 320 #define NEXT_I_IPL(i) (((i) >> 4) & 7) 321 #define NEXT_I_BIT(i) ( 1 << (((i) >> 8) & 0x1f)) 322 323 #define NEXT_I_IPL7_BASE 0 324 #define NEXT_I_IPL7_BITS 2 325 #define NEXT_I_NMI NEXT_I(7,0,31) 326 #define NEXT_I_PFAIL NEXT_I(7,1,30) 327 328 #define NEXT_I_IPL6_BASE 2 329 #define NEXT_I_IPL6_BITS 12 330 #define NEXT_I_TIMER NEXT_I(6,0,29) 331 #define NEXT_I_ENETX_DMA NEXT_I(6,1,28) 332 #define NEXT_I_ENETR_DMA NEXT_I(6,2,27) 333 #define NEXT_I_SCSI_DMA NEXT_I(6,3,26) 334 #define NEXT_I_DISK_DMA NEXT_I(6,4,25) 335 #define NEXT_I_PRINTER_DMA NEXT_I(6,5,24) 336 #define NEXT_I_SOUND_OUT_DMA NEXT_I(6,6,23) 337 #define NEXT_I_SOUND_IN_DMA NEXT_I(6,7,22) 338 #define NEXT_I_SCC_DMA NEXT_I(6,8,21) 339 #define NEXT_I_DSP_DMA NEXT_I(6,9,20) 340 #define NEXT_I_M2R_DMA NEXT_I(6,10,19) 341 #define NEXT_I_R2M_DMA NEXT_I(6,11,18) 342 343 #define NEXT_I_IPL5_BASE 14 344 #define NEXT_I_IPL5_BITS 3 345 #define NEXT_I_SCC NEXT_I(5,0,17) 346 #define NEXT_I_REMOTE NEXT_I(5,1,16) 347 #define NEXT_I_BUS NEXT_I(5,2,15) 348 349 #define NEXT_I_IPL4_BASE 17 350 #define NEXT_I_IPL4_BITS 1 351 #define NEXT_I_DSP_4 NEXT_I(4,0,14) 352 353 #define NEXT_I_IPL3_BASE 18 354 #define NEXT_I_IPL3_BITS 12 355 #define NEXT_I_DISK NEXT_I(3,0,13) 356 #define NEXT_I_C16_VIDEO NEXT_I(3,0,13) /* COLOR_FB - Steals old ESDI interrupt */ 357 #define NEXT_I_SCSI NEXT_I(3,1,12) 358 #define NEXT_I_PRINTER NEXT_I(3,2,11) 359 #define NEXT_I_ENETX NEXT_I(3,3,10) 360 #define NEXT_I_ENETR NEXT_I(3,4,9) 361 #define NEXT_I_SOUND_OVRUN NEXT_I(3,5,8) 362 #define NEXT_I_PHONE NEXT_I(3,6,7) 363 #define NEXT_I_DSP_3 NEXT_I(3,7,6) 364 #define NEXT_I_VIDEO NEXT_I(3,8,5) 365 #define NEXT_I_MONITOR NEXT_I(3,9,4) 366 #define NEXT_I_KYBD_MOUSE NEXT_I(3,10,3) 367 #define NEXT_I_POWER NEXT_I(3,11,2) 368 369 #define NEXT_I_IPL2_BASE 30 370 #define NEXT_I_IPL2_BITS 1 371 #define NEXT_I_SOFTINT1 NEXT_I(2,0,1) 372 373 #define NEXT_I_IPL1_BASE 31 374 #define NEXT_I_IPL1_BITS 1 375 #define NEXT_I_SOFTINT0 NEXT_I(1,0,0) 376 377 /****************************************************************/ 378 379 /* physical memory sections */ 380 #if 0 381 #define ROMBASE (0x00000000) 382 #endif 383 384 #define INTIOBASE (0x02000000) 385 #define INTIOTOP (0x02120000) 386 #define MONOBASE (0x0b000000) 387 #define MONOTOP (0x0b03a800) 388 #define COLORBASE (0x2c000000) 389 #define COLORTOP (0x2c1D4000) 390 391 #define NEXT_INTR_BITS \ 392 "\20\40NMI\37PFAIL\36TIMER\35ENETX_DMA\34ENETR_DMA\33SCSI_DMA\32DISK_DMA\31PRINTER_DMA\30SOUND_OUT_DMA\27SOUND_IN_DMA\26SCC_DMA\25DSP_DMA\24M2R_DMA\23R2M_DMA\22SCC\21REMOTE\20BUS\17DSP_4\16DISK|C16_VIDEO\15SCSI\14PRINTER\13ENETX\12ENETR\11SOUND_OVRUN\10PHONE\07DSP_3\06VIDEO\05MONITOR\04KYBD_MOUSE\03POWER\02SOFTINT1\01SOFTINT0" 393 394 /* 395 * Internal IO space: 396 * 397 * Ranges from 0x400000 to 0x600000 (IIOMAPSIZE). 398 * 399 * Internal IO space is mapped in the kernel from ``intiobase'' to 400 * ``intiolimit'' (defined in locore.s). Since it is always mapped, 401 * conversion between physical and kernel virtual addresses is easy. 402 */ 403 #define IIOV(pa) ((int)(pa)-INTIOBASE+intiobase) 404 #define IIOP(va) ((int)(va)-intiobase+INTIOBASE) 405 #define IIOMAPSIZE btoc(INTIOTOP-INTIOBASE) /* 2mb */ 406 407 /* mono fb space */ 408 #define MONOMAPSIZE btoc(MONOTOP-MONOBASE) /* who cares */ 409 410 /* color fb space */ 411 #define COLORMAPSIZE btoc(COLORTOP-COLORBASE) /* who cares */ 412 413 #endif /* _MACHINE_CPU_H_ */ 414
Indexes created Wed Sep 24 15:09:51 GMT 2025