cpu.h revision 1.44
1 /* $NetBSD: cpu.h,v 1.44 2011/02/08 20:20:21 rmind Exp $ */ 2 3 /* 4 * Copyright (c) 1988 University of Utah. 5 * Copyright (c) 1982, 1990, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * the Systems Programming Group of the University of Utah Computer 10 * Science Department. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: Utah $Hdr: cpu.h 1.16 91/03/25$ 37 * 38 * @(#)cpu.h 8.4 (Berkeley) 1/5/94 39 */ 40 41 #ifndef _MACHINE_CPU_H_ 42 #define _MACHINE_CPU_H_ 43 44 #if defined(_KERNEL) 45 46 #if defined(_KERNEL_OPT) 47 #include "opt_lockdebug.h" 48 #include "opt_m68k_arch.h" 49 #endif 50 51 /* 52 * Exported definitions unique to next68k/68k cpu support. 53 */ 54 55 /* 56 * Get common m68k definitions. 57 */ 58 #include <m68k/cpu.h> 59 60 #define M68K_MMU_MOTOROLA 61 62 /* 63 * Get interrupt glue. 64 */ 65 #include <machine/intr.h> 66 67 /* 68 * Arguments to hardclock and gatherstats encapsulate the previous 69 * machine state in an opaque clockframe. One the hp300, we use 70 * what the hardware pushes on an interrupt (frame format 0). 71 */ 72 struct clockframe { 73 u_short sr; /* sr at time of interrupt */ 74 u_long pc; /* pc at time of interrupt */ 75 u_short fmt:4, 76 vec:12; /* vector offset (4-word frame) */ 77 } __attribute__((packed)); 78 79 #define CLKF_USERMODE(framep) (((framep)->sr & PSL_S) == 0) 80 #define CLKF_PC(framep) ((framep)->pc) 81 82 /* 83 * The clock interrupt handler can determine if it's a nested 84 * interrupt by checking for interrupt_depth > 1. 85 * (Remember, the clock interrupt handler itself will cause the 86 * depth counter to be incremented). 87 */ 88 extern volatile unsigned int interrupt_depth; 89 #define CLKF_INTR(framep) (interrupt_depth > 1) 90 91 /* 92 * Preempt the current process if in interrupt from user mode, 93 * or after the current trap/syscall if in system mode. 94 */ 95 #define cpu_need_resched(ci, flags) \ 96 do { ci->ci_want_resched = 1; aston(); } while (/* CONSTCOND */0) 97 98 /* 99 * Give a profiling tick to the current process when the user profiling 100 * buffer pages are invalid. On the sun3, request an ast to send us 101 * through trap, marking the proc as needing a profiling tick. 102 */ 103 #define cpu_need_proftick(l) ((l)->l_pflag |= LP_OWEUPC, aston()) 104 105 /* 106 * Notify the current process (p) that it has a signal pending, 107 * process as soon as possible. 108 */ 109 #define cpu_signotify(l) aston() 110 111 #define aston() (astpending++) 112 113 extern int astpending; /* need to trap before returning to user mode */ 114 115 extern void (*vectab[])(void); 116 117 struct fpframe; 118 119 /* locore.s functions */ 120 void m68881_save(struct fpframe *); 121 void m68881_restore(struct fpframe *); 122 123 int suline(void *, void *); 124 void loadustp(int); 125 126 void doboot(void) __attribute__((__noreturn__)); 127 int nmihand(void *); 128 129 /* clock.c functions */ 130 void next68k_calibrate_delay(void); 131 132 #endif /* _KERNEL */ 133 134 #define NEXT_RAMBASE (0x4000000) /* really depends on slot, but... */ 135 #define NEXT_BANKSIZE (0x1000000) /* Size of a memory bank in physical address */ 136 137 #if 0 138 /* @@@ this needs to be fixed to work on 030's */ 139 #define NEXT_SLOT_ID 0x0 140 #ifdef M68030 141 #define NEXT_SLOT_ID_BMAP 0x0 142 #endif /* M68030 */ 143 #endif 144 #ifdef M68040 145 #ifdef DISABLE_NEXT_BMAP_CHIP /* @@@ For turbo testing */ 146 #define NEXT_SLOT_ID_BMAP 0x0 147 #else 148 #define NEXT_SLOT_ID_BMAP 0x00100000 149 #endif 150 #define NEXT_SLOT_ID 0x0 151 #endif /* M68040 */ 152 153 /****************************************************************/ 154 155 /* Eventually, I'd like to move these defines off into 156 * configure somewhere 157 * Darrin B Jewell <jewell (at) mit.edu> Thu Feb 5 03:50:58 1998 158 */ 159 /* ROM */ 160 #define NEXT_P_EPROM (NEXT_SLOT_ID+0x00000000) 161 #define NEXT_P_EPROM_BMAP (NEXT_SLOT_ID+0x01000000) 162 #define NEXT_P_EPROM_SIZE (128 * 1024) 163 164 /* device space */ 165 #define NEXT_P_DEV_SPACE (NEXT_SLOT_ID+0x02000000) 166 #define NEXT_P_DEV_BMAP (NEXT_SLOT_ID+0x02100000) 167 #define NEXT_DEV_SPACE_SIZE 0x0001c000 168 169 /* DMA control/status (writes MUST be 32-bit) */ 170 #define NEXT_P_SCSI_CSR (NEXT_SLOT_ID+0x02000010) 171 #define NEXT_P_SOUNDOUT_CSR (NEXT_SLOT_ID+0x02000040) 172 #define NEXT_P_DISK_CSR (NEXT_SLOT_ID+0x02000050) 173 #define NEXT_P_SOUNDIN_CSR (NEXT_SLOT_ID+0x02000080) 174 #define NEXT_P_PRINTER_CSR (NEXT_SLOT_ID+0x02000090) 175 #define NEXT_P_SCC_CSR (NEXT_SLOT_ID+0x020000c0) 176 #define NEXT_P_DSP_CSR (NEXT_SLOT_ID+0x020000d0) 177 #define NEXT_P_ENETX_CSR (NEXT_SLOT_ID+0x02000110) 178 #define NEXT_P_ENETR_CSR (NEXT_SLOT_ID+0x02000150) 179 #define NEXT_P_VIDEO_CSR (NEXT_SLOT_ID+0x02000180) 180 #define NEXT_P_M2R_CSR (NEXT_SLOT_ID+0x020001d0) 181 #define NEXT_P_R2M_CSR (NEXT_SLOT_ID+0x020001c0) 182 183 /* DMA scratch pad (writes MUST be 32-bit) */ 184 #define NEXT_P_VIDEO_SPAD (NEXT_SLOT_ID+0x02004180) 185 #define NEXT_P_EVENT_SPAD (NEXT_SLOT_ID+0x0200418c) 186 #define NEXT_P_M2M_SPAD (NEXT_SLOT_ID+0x020041e0) 187 188 /* device registers */ 189 #define NEXT_P_ENET (NEXT_SLOT_ID_BMAP+0x02006000) 190 #define NEXT_P_DSP (NEXT_SLOT_ID_BMAP+0x02008000) 191 #define NEXT_P_MON (NEXT_SLOT_ID+0x0200e000) 192 #define NEXT_P_PRINTER (NEXT_SLOT_ID+0x0200f000) 193 #define NEXT_P_DISK (NEXT_SLOT_ID_BMAP+0x02012000) 194 #define NEXT_P_SCSI (NEXT_SLOT_ID_BMAP+0x02014000) 195 #define NEXT_P_FLOPPY (NEXT_SLOT_ID_BMAP+0x02014100) 196 #define NEXT_P_TIMER (NEXT_SLOT_ID_BMAP+0x02016000) 197 #define NEXT_P_TIMER_CSR (NEXT_SLOT_ID_BMAP+0x02016004) 198 #define NEXT_P_SCC (NEXT_SLOT_ID_BMAP+0x02018000) 199 #define NEXT_P_SCC_CLK (NEXT_SLOT_ID_BMAP+0x02018004) 200 #define NEXT_P_EVENTC (NEXT_SLOT_ID_BMAP+0x0201a000) 201 #define NEXT_P_BMAP (NEXT_SLOT_ID+0x020c0000) 202 /* All COLOR_FB registers are 1 byte wide */ 203 #define NEXT_P_C16_DAC_0 (NEXT_SLOT_ID_BMAP+0x02018100) /* COLOR_FB - RAMDAC */ 204 #define NEXT_P_C16_DAC_1 (NEXT_SLOT_ID_BMAP+0x02018101) 205 #define NEXT_P_C16_DAC_2 (NEXT_SLOT_ID_BMAP+0x02018102) 206 #define NEXT_P_C16_DAC_3 (NEXT_SLOT_ID_BMAP+0x02018103) 207 #define NEXT_P_C16_CMD_REG (NEXT_SLOT_ID_BMAP+0x02018180) /* COLOR_FB - CSR */ 208 209 /* system control registers */ 210 #define NEXT_P_MEMTIMING (NEXT_SLOT_ID_BMAP+0x02006010) 211 #define NEXT_P_INTRSTAT (NEXT_SLOT_ID+0x02007000) 212 #define NEXT_P_INTRSTAT_CON 0x02007000 213 /* #define NEXT_P_INTRSTAT_0 (NEXT_SLOT_ID+0x02008000) */ 214 #define NEXT_P_INTRMASK (NEXT_SLOT_ID+0x02007800) 215 #define NEXT_P_INTRMASK_CON 0x02007800 216 /* #define NEXT_P_INTRMASK_0 (NEXT_SLOT_ID+0x0200a000) */ 217 #define NEXT_P_SCR1 (NEXT_SLOT_ID+0x0200c000) 218 #define NEXT_P_SCR1_CON 0x0200c000 219 #define NEXT_P_SID 0x0200c800 /* NOT slot-relative */ 220 #define NEXT_P_SCR2 (NEXT_SLOT_ID+0x0200d000) 221 #define NEXT_P_SCR2_CON 0x0200d000 222 #define NEXT_P_RMTINT (NEXT_SLOT_ID+0x0200d800) 223 #define NEXT_P_BRIGHTNESS (NEXT_SLOT_ID_BMAP+0x02010000) 224 #define NEXT_P_DRAM_TIMING (NEXT_SLOT_ID_BMAP+0x02018190) /* Warp 9C memory ctlr */ 225 #define NEXT_P_VRAM_TIMING (NEXT_SLOT_ID_BMAP+0x02018198) /* Warp 9C memory ctlr */ 226 227 /* memory */ 228 #define NEXT_P_MAINMEM (NEXT_SLOT_ID+0x04000000) 229 #define NEXT_P_MEMSIZE 0x04000000 230 #define NEXT_P_VIDEOMEM (NEXT_SLOT_ID+0x0b000000) 231 #define NEXT_P_VIDEOSIZE 0x0003a800 232 #if 0 233 #define NEXT_P_C16_VIDEOMEM (NEXT_SLOT_ID+0x06000000) /* COLOR_FB */ 234 #endif 235 #define NEXT_P_C16_VIDEOMEM (0x2c000000) 236 #define NEXT_P_C16_VIDEOSIZE 0x001D4000 /* COLOR_FB */ 237 #define NEXT_P_WF4VIDEO (NEXT_SLOT_ID+0x0c000000) /* w A+B-AB function */ 238 #define NEXT_P_WF3VIDEO (NEXT_SLOT_ID+0x0d000000) /* w (1-A)B function */ 239 #define NEXT_P_WF2VIDEO (NEXT_SLOT_ID+0x0e000000) /* w ceil(A+B) function */ 240 #define NEXT_P_WF1VIDEO (NEXT_SLOT_ID+0x0f000000) /* w AB function */ 241 #define NEXT_P_WF4MEM (NEXT_SLOT_ID+0x10000000) /* w A+B-AB function */ 242 #define NEXT_P_WF3MEM (NEXT_SLOT_ID+0x14000000) /* w (1-A)B function */ 243 #define NEXT_P_WF2MEM (NEXT_SLOT_ID+0x18000000) /* w ceil(A+B) function */ 244 #define NEXT_P_WF1MEM (NEXT_SLOT_ID+0x1c000000) /* w AB function */ 245 #define NEXT_NMWF 4 /* # of memory write funcs */ 246 247 /* 248 * Interrupt structure. 249 * BASE and BITS define the origin and length of the bit field in the 250 * interrupt status/mask register for the particular interrupt level. 251 * The first component of the interrupt device name indicates the bit 252 * position in the interrupt status and mask registers; the second is the 253 * interrupt level; the third is the bit index relative to the start of the 254 * bit field. 255 */ 256 #define NEXT_I(l,i,b) (((b) << 8) | ((l) << 4) | (i)) 257 #define NEXT_I_INDEX(i) ((i) & 0xf) 258 #define NEXT_I_IPL(i) (((i) >> 4) & 7) 259 #define NEXT_I_BIT(i) ( 1 << (((i) >> 8) & 0x1f)) 260 261 #define NEXT_I_IPL7_BASE 0 262 #define NEXT_I_IPL7_BITS 2 263 #define NEXT_I_NMI NEXT_I(7,0,31) 264 #define NEXT_I_PFAIL NEXT_I(7,1,30) 265 266 #define NEXT_I_IPL6_BASE 2 267 #define NEXT_I_IPL6_BITS 12 268 #define NEXT_I_TIMER NEXT_I(6,0,29) 269 #define NEXT_I_ENETX_DMA NEXT_I(6,1,28) 270 #define NEXT_I_ENETR_DMA NEXT_I(6,2,27) 271 #define NEXT_I_SCSI_DMA NEXT_I(6,3,26) 272 #define NEXT_I_DISK_DMA NEXT_I(6,4,25) 273 #define NEXT_I_PRINTER_DMA NEXT_I(6,5,24) 274 #define NEXT_I_SOUND_OUT_DMA NEXT_I(6,6,23) 275 #define NEXT_I_SOUND_IN_DMA NEXT_I(6,7,22) 276 #define NEXT_I_SCC_DMA NEXT_I(6,8,21) 277 #define NEXT_I_DSP_DMA NEXT_I(6,9,20) 278 #define NEXT_I_M2R_DMA NEXT_I(6,10,19) 279 #define NEXT_I_R2M_DMA NEXT_I(6,11,18) 280 281 #define NEXT_I_IPL5_BASE 14 282 #define NEXT_I_IPL5_BITS 3 283 #define NEXT_I_SCC NEXT_I(5,0,17) 284 #define NEXT_I_REMOTE NEXT_I(5,1,16) 285 #define NEXT_I_BUS NEXT_I(5,2,15) 286 287 #define NEXT_I_IPL4_BASE 17 288 #define NEXT_I_IPL4_BITS 1 289 #define NEXT_I_DSP_4 NEXT_I(4,0,14) 290 291 #define NEXT_I_IPL3_BASE 18 292 #define NEXT_I_IPL3_BITS 12 293 #define NEXT_I_DISK NEXT_I(3,0,13) 294 #define NEXT_I_C16_VIDEO NEXT_I(3,0,13) /* COLOR_FB - Steals old ESDI interrupt */ 295 #define NEXT_I_SCSI NEXT_I(3,1,12) 296 #define NEXT_I_PRINTER NEXT_I(3,2,11) 297 #define NEXT_I_ENETX NEXT_I(3,3,10) 298 #define NEXT_I_ENETR NEXT_I(3,4,9) 299 #define NEXT_I_SOUND_OVRUN NEXT_I(3,5,8) 300 #define NEXT_I_PHONE NEXT_I(3,6,7) 301 #define NEXT_I_DSP_3 NEXT_I(3,7,6) 302 #define NEXT_I_VIDEO NEXT_I(3,8,5) 303 #define NEXT_I_MONITOR NEXT_I(3,9,4) 304 #define NEXT_I_KYBD_MOUSE NEXT_I(3,10,3) 305 #define NEXT_I_POWER NEXT_I(3,11,2) 306 307 #define NEXT_I_IPL2_BASE 30 308 #define NEXT_I_IPL2_BITS 1 309 #define NEXT_I_SOFTINT1 NEXT_I(2,0,1) 310 311 #define NEXT_I_IPL1_BASE 31 312 #define NEXT_I_IPL1_BITS 1 313 #define NEXT_I_SOFTINT0 NEXT_I(1,0,0) 314 315 /****************************************************************/ 316 317 /* physical memory sections */ 318 #if 0 319 #define ROMBASE (0x00000000) 320 #endif 321 322 #define INTIOBASE (0x02000000) 323 #define INTIOTOP (0x02120000) 324 #define MONOBASE (0x0b000000) 325 #define MONOTOP (0x0b03a800) 326 #define COLORBASE (0x2c000000) 327 #define COLORTOP (0x2c1D4000) 328 329 #define NEXT_INTR_BITS \ 330 "\20\40NMI\37PFAIL\36TIMER\35ENETX_DMA\34ENETR_DMA\33SCSI_DMA\32DISK_DMA\31PRINTER_DMA\30SOUND_OUT_DMA\27SOUND_IN_DMA\26SCC_DMA\25DSP_DMA\24M2R_DMA\23R2M_DMA\22SCC\21REMOTE\20BUS\17DSP_4\16DISK|C16_VIDEO\15SCSI\14PRINTER\13ENETX\12ENETR\11SOUND_OVRUN\10PHONE\07DSP_3\06VIDEO\05MONITOR\04KYBD_MOUSE\03POWER\02SOFTINT1\01SOFTINT0" 331 332 /* 333 * Internal IO space: 334 * 335 * Ranges from 0x400000 to 0x600000 (IIOMAPSIZE). 336 * 337 * Internal IO space is mapped in the kernel from ``intiobase'' to 338 * ``intiolimit'' (defined in locore.s). Since it is always mapped, 339 * conversion between physical and kernel virtual addresses is easy. 340 */ 341 #define IIOV(pa) ((int)(pa)-INTIOBASE+intiobase) 342 #define IIOP(va) ((int)(va)-intiobase+INTIOBASE) 343 #define IIOMAPSIZE btoc(INTIOTOP-INTIOBASE) /* 2mb */ 344 345 /* mono fb space */ 346 #define MONOMAPSIZE btoc(MONOTOP-MONOBASE) /* who cares */ 347 348 /* color fb space */ 349 #define COLORMAPSIZE btoc(COLORTOP-COLORBASE) /* who cares */ 350 351 #endif /* _MACHINE_CPU_H_ */ 352
Indexes created Thu Sep 25 02:09:54 GMT 2025