cpu.h revision 1.5
1 /* $NetBSD: cpu.h,v 1.5 1998/11/10 22:45:44 dbj Exp $ */ 2 3 /* 4 * Copyright (c) 1988 University of Utah. 5 * Copyright (c) 1982, 1990, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * the Systems Programming Group of the University of Utah Computer 10 * Science Department. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the University of 23 * California, Berkeley and its contributors. 24 * 4. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * from: Utah $Hdr: cpu.h 1.16 91/03/25$ 41 * 42 * @(#)cpu.h 8.4 (Berkeley) 1/5/94 43 */ 44 45 46 #ifndef _CPU_MACHINE_ 47 #define _CPU_MACHINE_ 48 49 /* 50 * Exported definitions unique to next68k/68k cpu support. 51 */ 52 53 /* 54 * Get common m68k definitions. 55 */ 56 #include <m68k/cpu.h> 57 58 #define M68K_MMU_MOTOROLA 59 60 /* 61 * Get interrupt glue. 62 */ 63 #include <machine/intr.h> 64 65 /* 66 * definitions of cpu-dependent requirements 67 * referenced in generic code 68 */ 69 #define cpu_swapin(p) /* nothing */ 70 #define cpu_wait(p) /* nothing */ 71 #define cpu_swapout(p) /* nothing */ 72 73 /* 74 * Arguments to hardclock and gatherstats encapsulate the previous 75 * machine state in an opaque clockframe. One the hp300, we use 76 * what the hardware pushes on an interrupt (frame format 0). 77 */ 78 struct clockframe { 79 u_short sr; /* sr at time of interrupt */ 80 u_long pc; /* pc at time of interrupt */ 81 u_short vo; /* vector offset (4-word frame) */ 82 }; 83 84 #define CLKF_USERMODE(framep) (((framep)->sr & PSL_S) == 0) 85 #define CLKF_BASEPRI(framep) (((framep)->sr & PSL_IPL) == 0) 86 #define CLKF_PC(framep) ((framep)->pc) 87 #if 0 88 /* We would like to do it this way... */ 89 #define CLKF_INTR(framep) (((framep)->sr & PSL_M) == 0) 90 #else 91 /* but until we start using PSL_M, we have to do this instead */ 92 #define CLKF_INTR(framep) (0) /* XXX */ 93 #endif 94 95 /* 96 * Preempt the current process if in interrupt from user mode, 97 * or after the current trap/syscall if in system mode. 98 */ 99 extern int want_resched; /* resched() was called */ 100 #define need_resched() { want_resched = 1; aston(); } 101 102 /* 103 * Give a profiling tick to the current process when the user profiling 104 * buffer pages are invalid. On the sun3, request an ast to send us 105 * through trap, marking the proc as needing a profiling tick. 106 */ 107 #define need_proftick(p) ((p)->p_flag |= P_OWEUPC, aston()) 108 109 /* 110 * Notify the current process (p) that it has a signal pending, 111 * process as soon as possible. 112 */ 113 #define signotify(p) aston() 114 115 #define aston() (astpending++) 116 117 int astpending; /* need to trap before returning to user mode */ 118 int want_resched; /* resched() was called */ 119 120 #ifdef _KERNEL 121 extern volatile char *intiobase; 122 extern volatile char *intiolimit; 123 extern void (*vectab[]) __P((void)); 124 125 struct frame; 126 struct fpframe; 127 struct pcb; 128 129 /* locore.s functions */ 130 void m68881_save __P((struct fpframe *)); 131 void m68881_restore __P((struct fpframe *)); 132 #if 0 /* it's already in m68k/m68k.h */ 133 u_long getdfc __P((void)); 134 u_long getsfc __P((void)); 135 #endif 136 137 #if 0 /* {@@@ Use cacheops.h? */ 138 139 void DCIA __P((void)); 140 void DCIS __P((void)); 141 void DCIU __P((void)); 142 void ICIA __P((void)); 143 void ICPA __P((void)); 144 void PCIA __P((void)); 145 void TBIA __P((void)); 146 void TBIS __P((vm_offset_t)); 147 void TBIAS __P((void)); 148 void TBIAU __P((void)); 149 #if defined(M68040) 150 void DCFA __P((void)); 151 void DCFP __P((vm_offset_t)); 152 void DCFL __P((vm_offset_t)); 153 void DCPL __P((vm_offset_t)); 154 void DCPP __P((vm_offset_t)); 155 void ICPL __P((vm_offset_t)); 156 void ICPP __P((vm_offset_t)); 157 #endif 158 #endif /* }@@@ use m68k/cacheops.c */ 159 160 int suline __P((caddr_t, caddr_t)); 161 void savectx __P((struct pcb *)); 162 void switch_exit __P((struct proc *)); 163 void proc_trampoline __P((void)); 164 void loadustp __P((int)); 165 166 void doboot __P((void)) __attribute__((__noreturn__)); 167 168 /* vm_machdep.c functions */ 169 void physaccess __P((caddr_t, caddr_t, int, int)); 170 void physunaccess __P((caddr_t, int)); 171 int kvtop __P((caddr_t)); 172 173 /* clock.c functions */ 174 void next68k_calibrate_delay __P((void)); 175 176 #endif /* _KERNEL */ 177 178 #define NEXT_RAMBASE (0x4000000) /* really depends on slot, but... */ 179 #define NEXT_BANKSIZE (0x1000000) /* Size of a memory bank in physical address */ 180 181 #if 0 182 /* @@@ this needs to be fixed to work on 030's */ 183 #define NEXT_SLOT_ID 0x0 184 #ifdef M68030 185 #define NEXT_SLOT_ID_BMAP 0x0 186 #endif M68030 187 #endif 188 #ifdef M68040 189 #ifdef DISABLE_NEXT_BMAP_CHIP /* @@@ For turbo testing */ 190 #define NEXT_SLOT_ID_BMAP 0x0 191 #else 192 #define NEXT_SLOT_ID_BMAP 0x00100000 193 #endif 194 #define NEXT_SLOT_ID 0x0 195 #endif M68040 196 197 /****************************************************************/ 198 199 /* Eventually, I'd like to move these defines off into 200 * configure somewhere 201 * Darrin B Jewell <jewell (at) mit.edu> Thu Feb 5 03:50:58 1998 202 */ 203 /* ROM */ 204 #define NEXT_P_EPROM (NEXT_SLOT_ID+0x00000000) 205 #define NEXT_P_EPROM_BMAP (NEXT_SLOT_ID+0x01000000) 206 #define NEXT_P_EPROM_SIZE (128 * 1024) 207 208 /* device space */ 209 #define NEXT_P_DEV_SPACE (NEXT_SLOT_ID+0x02000000) 210 #define NEXT_P_DEV_BMAP (NEXT_SLOT_ID+0x02100000) 211 #define NEXT_DEV_SPACE_SIZE 0x0001c000 212 213 /* DMA control/status (writes MUST be 32-bit) */ 214 #define NEXT_P_SCSI_CSR (NEXT_SLOT_ID+0x02000010) 215 #define NEXT_P_SOUNDOUT_CSR (NEXT_SLOT_ID+0x02000040) 216 #define NEXT_P_DISK_CSR (NEXT_SLOT_ID+0x02000050) 217 #define NEXT_P_SOUNDIN_CSR (NEXT_SLOT_ID+0x02000080) 218 #define NEXT_P_PRINTER_CSR (NEXT_SLOT_ID+0x02000090) 219 #define NEXT_P_SCC_CSR (NEXT_SLOT_ID+0x020000c0) 220 #define NEXT_P_DSP_CSR (NEXT_SLOT_ID+0x020000d0) 221 #define NEXT_P_ENETX_CSR (NEXT_SLOT_ID+0x02000110) 222 #define NEXT_P_ENETR_CSR (NEXT_SLOT_ID+0x02000150) 223 #define NEXT_P_VIDEO_CSR (NEXT_SLOT_ID+0x02000180) 224 #define NEXT_P_M2R_CSR (NEXT_SLOT_ID+0x020001d0) 225 #define NEXT_P_R2M_CSR (NEXT_SLOT_ID+0x020001c0) 226 227 /* DMA scratch pad (writes MUST be 32-bit) */ 228 #define NEXT_P_VIDEO_SPAD (NEXT_SLOT_ID+0x02004180) 229 #define NEXT_P_EVENT_SPAD (NEXT_SLOT_ID+0x0200418c) 230 #define NEXT_P_M2M_SPAD (NEXT_SLOT_ID+0x020041e0) 231 232 /* device registers */ 233 #define NEXT_P_ENET (NEXT_SLOT_ID_BMAP+0x02006000) 234 #define NEXT_P_DSP (NEXT_SLOT_ID_BMAP+0x02008000) 235 #define NEXT_P_MON (NEXT_SLOT_ID+0x0200e000) 236 #define NEXT_P_PRINTER (NEXT_SLOT_ID+0x0200f000) 237 #define NEXT_P_DISK (NEXT_SLOT_ID_BMAP+0x02012000) 238 #define NEXT_P_SCSI (NEXT_SLOT_ID_BMAP+0x02014000) 239 #define NEXT_P_FLOPPY (NEXT_SLOT_ID_BMAP+0x02014100) 240 #define NEXT_P_TIMER (NEXT_SLOT_ID_BMAP+0x02016000) 241 #define NEXT_P_TIMER_CSR (NEXT_SLOT_ID_BMAP+0x02016004) 242 #define NEXT_P_SCC (NEXT_SLOT_ID_BMAP+0x02018000) 243 #define NEXT_P_SCC_CLK (NEXT_SLOT_ID_BMAP+0x02018004) 244 #define NEXT_P_EVENTC (NEXT_SLOT_ID_BMAP+0x0201a000) 245 #define NEXT_P_BMAP (NEXT_SLOT_ID+0x020c0000) 246 /* All COLOR_FB registers are 1 byte wide */ 247 #define NEXT_P_C16_DAC_0 (NEXT_SLOT_ID_BMAP+0x02018100) /* COLOR_FB - RAMDAC */ 248 #define NEXT_P_C16_DAC_1 (NEXT_SLOT_ID_BMAP+0x02018101) 249 #define NEXT_P_C16_DAC_2 (NEXT_SLOT_ID_BMAP+0x02018102) 250 #define NEXT_P_C16_DAC_3 (NEXT_SLOT_ID_BMAP+0x02018103) 251 #define NEXT_P_C16_CMD_REG (NEXT_SLOT_ID_BMAP+0x02018180) /* COLOR_FB - CSR */ 252 253 /* system control registers */ 254 #define NEXT_P_MEMTIMING (NEXT_SLOT_ID_BMAP+0x02006010) 255 #define NEXT_P_INTRSTAT (NEXT_SLOT_ID+0x02007000) 256 #define NEXT_P_INTRSTAT_CON 0x02007000 257 #define NEXT_P_INTRMASK (NEXT_SLOT_ID+0x02007800) 258 #define NEXT_P_INTRMASK_CON 0x02007800 259 #define NEXT_P_SCR1 (NEXT_SLOT_ID+0x0200c000) 260 #define NEXT_P_SCR1_CON 0x0200c000 261 #define NEXT_P_SID 0x0200c800 /* NOT slot-relative */ 262 #define NEXT_P_SCR2 (NEXT_SLOT_ID+0x0200d000) 263 #define NEXT_P_SCR2_CON 0x0200d000 264 #define NEXT_P_RMTINT (NEXT_SLOT_ID+0x0200d800) 265 #define NEXT_P_BRIGHTNESS (NEXT_SLOT_ID_BMAP+0x02010000) 266 #define NEXT_P_DRAM_TIMING (NEXT_SLOT_ID_BMAP+0x02018190) /* Warp 9C memory ctlr */ 267 #define NEXT_P_VRAM_TIMING (NEXT_SLOT_ID_BMAP+0x02018198) /* Warp 9C memory ctlr */ 268 269 /* memory */ 270 #define NEXT_P_MAINMEM (NEXT_SLOT_ID+0x04000000) 271 #define NEXT_P_MEMSIZE 0x04000000 272 #define NEXT_P_VIDEOMEM (NEXT_SLOT_ID+0x0b000000) 273 #define NEXT_P_VIDEOSIZE 0x0003a800 274 #define NEXT_P_C16_VIDEOMEM (NEXT_SLOT_ID+0x06000000) /* COLOR_FB */ 275 #define NEXT_P_C16_VIDEOSIZE 0x001D4000 /* COLOR_FB */ 276 #define NEXT_P_WF4VIDEO (NEXT_SLOT_ID+0x0c000000) /* w A+B-AB function */ 277 #define NEXT_P_WF3VIDEO (NEXT_SLOT_ID+0x0d000000) /* w (1-A)B function */ 278 #define NEXT_P_WF2VIDEO (NEXT_SLOT_ID+0x0e000000) /* w ceil(A+B) function */ 279 #define NEXT_P_WF1VIDEO (NEXT_SLOT_ID+0x0f000000) /* w AB function */ 280 #define NEXT_P_WF4MEM (NEXT_SLOT_ID+0x10000000) /* w A+B-AB function */ 281 #define NEXT_P_WF3MEM (NEXT_SLOT_ID+0x14000000) /* w (1-A)B function */ 282 #define NEXT_P_WF2MEM (NEXT_SLOT_ID+0x18000000) /* w ceil(A+B) function */ 283 #define NEXT_P_WF1MEM (NEXT_SLOT_ID+0x1c000000) /* w AB function */ 284 #define NEXT_NMWF 4 /* # of memory write funcs */ 285 286 /* 287 * Interrupt structure. 288 * BASE and BITS define the origin and length of the bit field in the 289 * interrupt status/mask register for the particular interrupt level. 290 * The first component of the interrupt device name indicates the bit 291 * position in the interrupt status and mask registers; the second is the 292 * interrupt level; the third is the bit index relative to the start of the 293 * bit field. 294 */ 295 #define NEXT_I(l,i,b) (((b) << 8) | ((l) << 4) | (i)) 296 #define NEXT_I_INDEX(i) ((i) & 0xf) 297 #define NEXT_I_IPL(i) (((i) >> 4) & 7) 298 #define NEXT_I_BIT(i) ( 1 << (((i) >> 8) & 0x1f)) 299 300 #define NEXT_I_IPL7_BASE 0 301 #define NEXT_I_IPL7_BITS 2 302 #define NEXT_I_NMI NEXT_I(7,0,31) 303 #define NEXT_I_PFAIL NEXT_I(7,1,30) 304 305 #define NEXT_I_IPL6_BASE 2 306 #define NEXT_I_IPL6_BITS 12 307 #define NEXT_I_TIMER NEXT_I(6,0,29) 308 #define NEXT_I_ENETX_DMA NEXT_I(6,1,28) 309 #define NEXT_I_ENETR_DMA NEXT_I(6,2,27) 310 #define NEXT_I_SCSI_DMA NEXT_I(6,3,26) 311 #define NEXT_I_DISK_DMA NEXT_I(6,4,25) 312 #define NEXT_I_PRINTER_DMA NEXT_I(6,5,24) 313 #define NEXT_I_SOUND_OUT_DMA NEXT_I(6,6,23) 314 #define NEXT_I_SOUND_IN_DMA NEXT_I(6,7,22) 315 #define NEXT_I_SCC_DMA NEXT_I(6,8,21) 316 #define NEXT_I_DSP_DMA NEXT_I(6,9,20) 317 #define NEXT_I_M2R_DMA NEXT_I(6,10,19) 318 #define NEXT_I_R2M_DMA NEXT_I(6,11,18) 319 320 #define NEXT_I_IPL5_BASE 14 321 #define NEXT_I_IPL5_BITS 3 322 #define NEXT_I_SCC NEXT_I(5,0,17) 323 #define NEXT_I_REMOTE NEXT_I(5,1,16) 324 #define NEXT_I_BUS NEXT_I(5,2,15) 325 326 #define NEXT_I_IPL4_BASE 17 327 #define NEXT_I_IPL4_BITS 1 328 #define NEXT_I_DSP_4 NEXT_I(4,0,14) 329 330 #define NEXT_I_IPL3_BASE 18 331 #define NEXT_I_IPL3_BITS 12 332 #define NEXT_I_DISK NEXT_I(3,0,13) 333 #define NEXT_I_C16_VIDEO NEXT_I(3,0,13) /* COLOR_FB - Steals old ESDI interrupt */ 334 #define NEXT_I_SCSI NEXT_I(3,1,12) 335 #define NEXT_I_PRINTER NEXT_I(3,2,11) 336 #define NEXT_I_ENETX NEXT_I(3,3,10) 337 #define NEXT_I_ENETR NEXT_I(3,4,9) 338 #define NEXT_I_SOUND_OVRUN NEXT_I(3,5,8) 339 #define NEXT_I_PHONE NEXT_I(3,6,7) 340 #define NEXT_I_DSP_3 NEXT_I(3,7,6) 341 #define NEXT_I_VIDEO NEXT_I(3,8,5) 342 #define NEXT_I_MONITOR NEXT_I(3,9,4) 343 #define NEXT_I_KYBD_MOUSE NEXT_I(3,10,3) 344 #define NEXT_I_POWER NEXT_I(3,11,2) 345 346 #define NEXT_I_IPL2_BASE 30 347 #define NEXT_I_IPL2_BITS 1 348 #define NEXT_I_SOFTINT1 NEXT_I(2,0,1) 349 350 #define NEXT_I_IPL1_BASE 31 351 #define NEXT_I_IPL1_BITS 1 352 #define NEXT_I_SOFTINT0 NEXT_I(1,0,0) 353 354 /****************************************************************/ 355 356 /* physical memory sections */ 357 #if 0 358 #define ROMBASE (0x00000000) 359 #endif 360 361 #define INTIOBASE (0x02000000) 362 #define INTIOTOP (0x02120000) 363 364 #define NEXT_INTR_BITS \ 365 "\20\40NMI\37PFAIL\36TIMER\35ENETX_DMA\34ENETR_DMA\33SCSI_DMA\32DISK_DMA\31PRINTER_DMA\30SOUND_OUT_DMA\27SOUND_IN_DMA\26SCC_DMA\25DSP_DMA\24M2R_DMA\23R2M_DMA\22SCC\21REMOTE\20BUS\17DSP_4\16DISK|C16_VIDEO\15SCSI\14PRINTER\13ENETX\12ENETR\11SOUND_OVRUN\10PHONE\07DSP_3\06VIDEO\05MONITOR\04KYBD_MOUSE\03POWER\02SOFTINT1\01SOFTINT0" 366 367 /* 368 * Internal IO space: 369 * 370 * Ranges from 0x400000 to 0x600000 (IIOMAPSIZE). 371 * 372 * Internal IO space is mapped in the kernel from ``intiobase'' to 373 * ``intiolimit'' (defined in locore.s). Since it is always mapped, 374 * conversion between physical and kernel virtual addresses is easy. 375 */ 376 #define ISIIOVA(va) \ 377 ((char *)(va) >= intiobase && (char *)(va) < intiolimit) 378 #define IIOV(pa) ((int)(pa)-INTIOBASE+(int)intiobase) 379 #define IIOP(va) ((int)(va)-(int)intiobase+INTIOBASE) 380 #define IIOPOFF(pa) ((int)(pa)-INTIOBASE) 381 #define IIOMAPSIZE btoc(INTIOTOP-INTIOBASE) /* 2mb */ 382 383 #endif /* _CPU_MACHINE_ */ 384
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