cpu.h revision 1.8 1 /* $NetBSD: cpu.h,v 1.8 1999/02/26 21:34:38 is Exp $ */
2
3 /*
4 * Copyright (c) 1988 University of Utah.
5 * Copyright (c) 1982, 1990, 1993
6 * The Regents of the University of California. All rights reserved.
7 *
8 * This code is derived from software contributed to Berkeley by
9 * the Systems Programming Group of the University of Utah Computer
10 * Science Department.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. All advertising materials mentioning features or use of this software
21 * must display the following acknowledgement:
22 * This product includes software developed by the University of
23 * California, Berkeley and its contributors.
24 * 4. Neither the name of the University nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * SUCH DAMAGE.
39 *
40 * from: Utah $Hdr: cpu.h 1.16 91/03/25$
41 *
42 * @(#)cpu.h 8.4 (Berkeley) 1/5/94
43 */
44
45
46 #ifndef _CPU_MACHINE_
47 #define _CPU_MACHINE_
48
49 /*
50 * Exported definitions unique to next68k/68k cpu support.
51 */
52
53 /*
54 * Get common m68k definitions.
55 */
56 #include <m68k/cpu.h>
57
58 #define M68K_MMU_MOTOROLA
59
60 /*
61 * Get interrupt glue.
62 */
63 #include <machine/intr.h>
64
65 /*
66 * definitions of cpu-dependent requirements
67 * referenced in generic code
68 */
69 #define cpu_swapin(p) /* nothing */
70 #define cpu_wait(p) /* nothing */
71 #define cpu_swapout(p) /* nothing */
72
73 /*
74 * Arguments to hardclock and gatherstats encapsulate the previous
75 * machine state in an opaque clockframe. One the hp300, we use
76 * what the hardware pushes on an interrupt (frame format 0).
77 */
78 struct clockframe {
79 u_short sr; /* sr at time of interrupt */
80 u_long pc; /* pc at time of interrupt */
81 u_short vo; /* vector offset (4-word frame) */
82 };
83
84 #define CLKF_USERMODE(framep) (((framep)->sr & PSL_S) == 0)
85 #define CLKF_BASEPRI(framep) (((framep)->sr & PSL_IPL) == 0)
86 #define CLKF_PC(framep) ((framep)->pc)
87 #if 0
88 /* We would like to do it this way... */
89 #define CLKF_INTR(framep) (((framep)->sr & PSL_M) == 0)
90 #else
91 /* but until we start using PSL_M, we have to do this instead */
92 #define CLKF_INTR(framep) (0) /* XXX */
93 #endif
94
95 /*
96 * Preempt the current process if in interrupt from user mode,
97 * or after the current trap/syscall if in system mode.
98 */
99 extern int want_resched; /* resched() was called */
100 #define need_resched() { want_resched = 1; aston(); }
101
102 /*
103 * Give a profiling tick to the current process when the user profiling
104 * buffer pages are invalid. On the sun3, request an ast to send us
105 * through trap, marking the proc as needing a profiling tick.
106 */
107 #define need_proftick(p) ((p)->p_flag |= P_OWEUPC, aston())
108
109 /*
110 * Notify the current process (p) that it has a signal pending,
111 * process as soon as possible.
112 */
113 #define signotify(p) aston()
114
115 #define aston() (astpending++)
116
117 int astpending; /* need to trap before returning to user mode */
118 int want_resched; /* resched() was called */
119
120 #ifdef _KERNEL
121 extern volatile char *intiobase;
122 extern volatile char *intiolimit;
123 extern volatile char *videobase;
124 extern volatile char *videolimit;
125 extern void (*vectab[]) __P((void));
126
127 struct frame;
128 struct fpframe;
129 struct pcb;
130
131 /* locore.s functions */
132 void m68881_save __P((struct fpframe *));
133 void m68881_restore __P((struct fpframe *));
134 #if 0 /* it's already in m68k/m68k.h */
135 u_long getdfc __P((void));
136 u_long getsfc __P((void));
137 #endif
138
139 #if 0 /* {@@@ Use cacheops.h? */
140
141 void DCIA __P((void));
142 void DCIS __P((void));
143 void DCIU __P((void));
144 void ICIA __P((void));
145 void ICPA __P((void));
146 void PCIA __P((void));
147 void TBIA __P((void));
148 void TBIS __P((vm_offset_t));
149 void TBIAS __P((void));
150 void TBIAU __P((void));
151 #if defined(M68040)
152 void DCFA __P((void));
153 void DCFP __P((vm_offset_t));
154 void DCFL __P((vm_offset_t));
155 void DCPL __P((vm_offset_t));
156 void DCPP __P((vm_offset_t));
157 void ICPL __P((vm_offset_t));
158 void ICPP __P((vm_offset_t));
159 #endif
160 #endif /* }@@@ use m68k/cacheops.c */
161
162 int suline __P((caddr_t, caddr_t));
163 void savectx __P((struct pcb *));
164 void switch_exit __P((struct proc *));
165 void proc_trampoline __P((void));
166 void loadustp __P((int));
167
168 void doboot __P((void)) __attribute__((__noreturn__));
169
170 /* sys_machdep.c functions */
171 int cachectl1 __P((u_long, vaddr_t, size_t, struct proc *));
172
173 /* vm_machdep.c functions */
174 void physaccess __P((caddr_t, caddr_t, int, int));
175 void physunaccess __P((caddr_t, int));
176 int kvtop __P((caddr_t));
177
178 /* clock.c functions */
179 void next68k_calibrate_delay __P((void));
180
181 /* trap.c function */
182 void child_return __P((void *));
183
184 #endif /* _KERNEL */
185
186 #define NEXT_RAMBASE (0x4000000) /* really depends on slot, but... */
187 #define NEXT_BANKSIZE (0x1000000) /* Size of a memory bank in physical address */
188
189 #if 0
190 /* @@@ this needs to be fixed to work on 030's */
191 #define NEXT_SLOT_ID 0x0
192 #ifdef M68030
193 #define NEXT_SLOT_ID_BMAP 0x0
194 #endif M68030
195 #endif
196 #ifdef M68040
197 #ifdef DISABLE_NEXT_BMAP_CHIP /* @@@ For turbo testing */
198 #define NEXT_SLOT_ID_BMAP 0x0
199 #else
200 #define NEXT_SLOT_ID_BMAP 0x00100000
201 #endif
202 #define NEXT_SLOT_ID 0x0
203 #endif M68040
204
205 /****************************************************************/
206
207 /* Eventually, I'd like to move these defines off into
208 * configure somewhere
209 * Darrin B Jewell <jewell (at) mit.edu> Thu Feb 5 03:50:58 1998
210 */
211 /* ROM */
212 #define NEXT_P_EPROM (NEXT_SLOT_ID+0x00000000)
213 #define NEXT_P_EPROM_BMAP (NEXT_SLOT_ID+0x01000000)
214 #define NEXT_P_EPROM_SIZE (128 * 1024)
215
216 /* device space */
217 #define NEXT_P_DEV_SPACE (NEXT_SLOT_ID+0x02000000)
218 #define NEXT_P_DEV_BMAP (NEXT_SLOT_ID+0x02100000)
219 #define NEXT_DEV_SPACE_SIZE 0x0001c000
220
221 /* DMA control/status (writes MUST be 32-bit) */
222 #define NEXT_P_SCSI_CSR (NEXT_SLOT_ID+0x02000010)
223 #define NEXT_P_SOUNDOUT_CSR (NEXT_SLOT_ID+0x02000040)
224 #define NEXT_P_DISK_CSR (NEXT_SLOT_ID+0x02000050)
225 #define NEXT_P_SOUNDIN_CSR (NEXT_SLOT_ID+0x02000080)
226 #define NEXT_P_PRINTER_CSR (NEXT_SLOT_ID+0x02000090)
227 #define NEXT_P_SCC_CSR (NEXT_SLOT_ID+0x020000c0)
228 #define NEXT_P_DSP_CSR (NEXT_SLOT_ID+0x020000d0)
229 #define NEXT_P_ENETX_CSR (NEXT_SLOT_ID+0x02000110)
230 #define NEXT_P_ENETR_CSR (NEXT_SLOT_ID+0x02000150)
231 #define NEXT_P_VIDEO_CSR (NEXT_SLOT_ID+0x02000180)
232 #define NEXT_P_M2R_CSR (NEXT_SLOT_ID+0x020001d0)
233 #define NEXT_P_R2M_CSR (NEXT_SLOT_ID+0x020001c0)
234
235 /* DMA scratch pad (writes MUST be 32-bit) */
236 #define NEXT_P_VIDEO_SPAD (NEXT_SLOT_ID+0x02004180)
237 #define NEXT_P_EVENT_SPAD (NEXT_SLOT_ID+0x0200418c)
238 #define NEXT_P_M2M_SPAD (NEXT_SLOT_ID+0x020041e0)
239
240 /* device registers */
241 #define NEXT_P_ENET (NEXT_SLOT_ID_BMAP+0x02006000)
242 #define NEXT_P_DSP (NEXT_SLOT_ID_BMAP+0x02008000)
243 #define NEXT_P_MON (NEXT_SLOT_ID+0x0200e000)
244 #define NEXT_P_PRINTER (NEXT_SLOT_ID+0x0200f000)
245 #define NEXT_P_DISK (NEXT_SLOT_ID_BMAP+0x02012000)
246 #define NEXT_P_SCSI (NEXT_SLOT_ID_BMAP+0x02014000)
247 #define NEXT_P_FLOPPY (NEXT_SLOT_ID_BMAP+0x02014100)
248 #define NEXT_P_TIMER (NEXT_SLOT_ID_BMAP+0x02016000)
249 #define NEXT_P_TIMER_CSR (NEXT_SLOT_ID_BMAP+0x02016004)
250 #define NEXT_P_SCC (NEXT_SLOT_ID_BMAP+0x02018000)
251 #define NEXT_P_SCC_CLK (NEXT_SLOT_ID_BMAP+0x02018004)
252 #define NEXT_P_EVENTC (NEXT_SLOT_ID_BMAP+0x0201a000)
253 #define NEXT_P_BMAP (NEXT_SLOT_ID+0x020c0000)
254 /* All COLOR_FB registers are 1 byte wide */
255 #define NEXT_P_C16_DAC_0 (NEXT_SLOT_ID_BMAP+0x02018100) /* COLOR_FB - RAMDAC */
256 #define NEXT_P_C16_DAC_1 (NEXT_SLOT_ID_BMAP+0x02018101)
257 #define NEXT_P_C16_DAC_2 (NEXT_SLOT_ID_BMAP+0x02018102)
258 #define NEXT_P_C16_DAC_3 (NEXT_SLOT_ID_BMAP+0x02018103)
259 #define NEXT_P_C16_CMD_REG (NEXT_SLOT_ID_BMAP+0x02018180) /* COLOR_FB - CSR */
260
261 /* system control registers */
262 #define NEXT_P_MEMTIMING (NEXT_SLOT_ID_BMAP+0x02006010)
263 #define NEXT_P_INTRSTAT (NEXT_SLOT_ID+0x02007000)
264 #define NEXT_P_INTRSTAT_CON 0x02007000
265 #define NEXT_P_INTRMASK (NEXT_SLOT_ID+0x02007800)
266 #define NEXT_P_INTRMASK_CON 0x02007800
267 #define NEXT_P_SCR1 (NEXT_SLOT_ID+0x0200c000)
268 #define NEXT_P_SCR1_CON 0x0200c000
269 #define NEXT_P_SID 0x0200c800 /* NOT slot-relative */
270 #define NEXT_P_SCR2 (NEXT_SLOT_ID+0x0200d000)
271 #define NEXT_P_SCR2_CON 0x0200d000
272 #define NEXT_P_RMTINT (NEXT_SLOT_ID+0x0200d800)
273 #define NEXT_P_BRIGHTNESS (NEXT_SLOT_ID_BMAP+0x02010000)
274 #define NEXT_P_DRAM_TIMING (NEXT_SLOT_ID_BMAP+0x02018190) /* Warp 9C memory ctlr */
275 #define NEXT_P_VRAM_TIMING (NEXT_SLOT_ID_BMAP+0x02018198) /* Warp 9C memory ctlr */
276
277 /* memory */
278 #define NEXT_P_MAINMEM (NEXT_SLOT_ID+0x04000000)
279 #define NEXT_P_MEMSIZE 0x04000000
280 #define NEXT_P_VIDEOMEM (NEXT_SLOT_ID+0x0b000000)
281 #define NEXT_P_VIDEOSIZE 0x0003a800
282 #define NEXT_P_C16_VIDEOMEM (NEXT_SLOT_ID+0x06000000) /* COLOR_FB */
283 #define NEXT_P_C16_VIDEOSIZE 0x001D4000 /* COLOR_FB */
284 #define NEXT_P_WF4VIDEO (NEXT_SLOT_ID+0x0c000000) /* w A+B-AB function */
285 #define NEXT_P_WF3VIDEO (NEXT_SLOT_ID+0x0d000000) /* w (1-A)B function */
286 #define NEXT_P_WF2VIDEO (NEXT_SLOT_ID+0x0e000000) /* w ceil(A+B) function */
287 #define NEXT_P_WF1VIDEO (NEXT_SLOT_ID+0x0f000000) /* w AB function */
288 #define NEXT_P_WF4MEM (NEXT_SLOT_ID+0x10000000) /* w A+B-AB function */
289 #define NEXT_P_WF3MEM (NEXT_SLOT_ID+0x14000000) /* w (1-A)B function */
290 #define NEXT_P_WF2MEM (NEXT_SLOT_ID+0x18000000) /* w ceil(A+B) function */
291 #define NEXT_P_WF1MEM (NEXT_SLOT_ID+0x1c000000) /* w AB function */
292 #define NEXT_NMWF 4 /* # of memory write funcs */
293
294 /*
295 * Interrupt structure.
296 * BASE and BITS define the origin and length of the bit field in the
297 * interrupt status/mask register for the particular interrupt level.
298 * The first component of the interrupt device name indicates the bit
299 * position in the interrupt status and mask registers; the second is the
300 * interrupt level; the third is the bit index relative to the start of the
301 * bit field.
302 */
303 #define NEXT_I(l,i,b) (((b) << 8) | ((l) << 4) | (i))
304 #define NEXT_I_INDEX(i) ((i) & 0xf)
305 #define NEXT_I_IPL(i) (((i) >> 4) & 7)
306 #define NEXT_I_BIT(i) ( 1 << (((i) >> 8) & 0x1f))
307
308 #define NEXT_I_IPL7_BASE 0
309 #define NEXT_I_IPL7_BITS 2
310 #define NEXT_I_NMI NEXT_I(7,0,31)
311 #define NEXT_I_PFAIL NEXT_I(7,1,30)
312
313 #define NEXT_I_IPL6_BASE 2
314 #define NEXT_I_IPL6_BITS 12
315 #define NEXT_I_TIMER NEXT_I(6,0,29)
316 #define NEXT_I_ENETX_DMA NEXT_I(6,1,28)
317 #define NEXT_I_ENETR_DMA NEXT_I(6,2,27)
318 #define NEXT_I_SCSI_DMA NEXT_I(6,3,26)
319 #define NEXT_I_DISK_DMA NEXT_I(6,4,25)
320 #define NEXT_I_PRINTER_DMA NEXT_I(6,5,24)
321 #define NEXT_I_SOUND_OUT_DMA NEXT_I(6,6,23)
322 #define NEXT_I_SOUND_IN_DMA NEXT_I(6,7,22)
323 #define NEXT_I_SCC_DMA NEXT_I(6,8,21)
324 #define NEXT_I_DSP_DMA NEXT_I(6,9,20)
325 #define NEXT_I_M2R_DMA NEXT_I(6,10,19)
326 #define NEXT_I_R2M_DMA NEXT_I(6,11,18)
327
328 #define NEXT_I_IPL5_BASE 14
329 #define NEXT_I_IPL5_BITS 3
330 #define NEXT_I_SCC NEXT_I(5,0,17)
331 #define NEXT_I_REMOTE NEXT_I(5,1,16)
332 #define NEXT_I_BUS NEXT_I(5,2,15)
333
334 #define NEXT_I_IPL4_BASE 17
335 #define NEXT_I_IPL4_BITS 1
336 #define NEXT_I_DSP_4 NEXT_I(4,0,14)
337
338 #define NEXT_I_IPL3_BASE 18
339 #define NEXT_I_IPL3_BITS 12
340 #define NEXT_I_DISK NEXT_I(3,0,13)
341 #define NEXT_I_C16_VIDEO NEXT_I(3,0,13) /* COLOR_FB - Steals old ESDI interrupt */
342 #define NEXT_I_SCSI NEXT_I(3,1,12)
343 #define NEXT_I_PRINTER NEXT_I(3,2,11)
344 #define NEXT_I_ENETX NEXT_I(3,3,10)
345 #define NEXT_I_ENETR NEXT_I(3,4,9)
346 #define NEXT_I_SOUND_OVRUN NEXT_I(3,5,8)
347 #define NEXT_I_PHONE NEXT_I(3,6,7)
348 #define NEXT_I_DSP_3 NEXT_I(3,7,6)
349 #define NEXT_I_VIDEO NEXT_I(3,8,5)
350 #define NEXT_I_MONITOR NEXT_I(3,9,4)
351 #define NEXT_I_KYBD_MOUSE NEXT_I(3,10,3)
352 #define NEXT_I_POWER NEXT_I(3,11,2)
353
354 #define NEXT_I_IPL2_BASE 30
355 #define NEXT_I_IPL2_BITS 1
356 #define NEXT_I_SOFTINT1 NEXT_I(2,0,1)
357
358 #define NEXT_I_IPL1_BASE 31
359 #define NEXT_I_IPL1_BITS 1
360 #define NEXT_I_SOFTINT0 NEXT_I(1,0,0)
361
362 /****************************************************************/
363
364 /* physical memory sections */
365 #if 0
366 #define ROMBASE (0x00000000)
367 #endif
368
369 #define INTIOBASE (0x02000000)
370 #define INTIOTOP (0x02120000)
371 #define VIDEOBASE (0x0b000000)
372 #define VIDEOTOP (0x0b03a800)
373
374 #define NEXT_INTR_BITS \
375 "\20\40NMI\37PFAIL\36TIMER\35ENETX_DMA\34ENETR_DMA\33SCSI_DMA\32DISK_DMA\31PRINTER_DMA\30SOUND_OUT_DMA\27SOUND_IN_DMA\26SCC_DMA\25DSP_DMA\24M2R_DMA\23R2M_DMA\22SCC\21REMOTE\20BUS\17DSP_4\16DISK|C16_VIDEO\15SCSI\14PRINTER\13ENETX\12ENETR\11SOUND_OVRUN\10PHONE\07DSP_3\06VIDEO\05MONITOR\04KYBD_MOUSE\03POWER\02SOFTINT1\01SOFTINT0"
376
377 /*
378 * Internal IO space:
379 *
380 * Ranges from 0x400000 to 0x600000 (IIOMAPSIZE).
381 *
382 * Internal IO space is mapped in the kernel from ``intiobase'' to
383 * ``intiolimit'' (defined in locore.s). Since it is always mapped,
384 * conversion between physical and kernel virtual addresses is easy.
385 */
386 #define ISIIOVA(va) \
387 ((char *)(va) >= intiobase && (char *)(va) < intiolimit)
388 #define IIOV(pa) ((int)(pa)-INTIOBASE+(int)intiobase)
389 #define IIOP(va) ((int)(va)-(int)intiobase+INTIOBASE)
390 #define IIOPOFF(pa) ((int)(pa)-INTIOBASE)
391 #define IIOMAPSIZE btoc(INTIOTOP-INTIOBASE) /* 2mb */
392
393 /* video fb space */
394 #define ISVIDEOVA(va) \
395 ((char *)(va) >= videobase && (char *)(va) < videolimit)
396 #define VIDEOV(pa) ((int)(pa)-VIDEOBASE+(int)videobase)
397 #define VIDEOP(va) ((int)(va)-(int)videobase+VIDEOBASE)
398 #define VIDEOPOFF(pa) ((int)(pa)-VIDEOBASE)
399 #define VIDEOMAPSIZE btoc(VIDEOTOP-VIDEOBASE) /* who cares */
400
401 #endif /* _CPU_MACHINE_ */
402