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intr.h revision 1.11 
      1 /*	$NetBSD: intr.h,v 1.11 2002/09/11 01:46:33 mycroft Exp $	*/
      2 
      3 /*
      4  * Copyright (C) 1997 Scott Reynolds
      5  * Copyright (C) 1998 Darrin Jewell
      6  * All rights reserved.
      7  *
      8  * Redistribution and use in source and binary forms, with or without
      9  * modification, are permitted provided that the following conditions
     10  * are met:
     11  * 1. Redistributions of source code must retain the above copyright
     12  *    notice, this list of conditions and the following disclaimer.
     13  * 2. Redistributions in binary form must reproduce the above copyright
     14  *    notice, this list of conditions and the following disclaimer in the
     15  *    documentation and/or other materials provided with the distribution.
     16  * 3. The name of the author may not be used to endorse or promote products
     17  *    derived from this software without specific prior written permission.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     20  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     21  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     22  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     23  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     24  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     25  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     26  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     27  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     28  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     29  */
     30 
     31 #ifndef _NEXT68K_INTR_H_
     32 #define _NEXT68K_INTR_H_
     33 
     34 #include <sys/device.h>
     35 #include <sys/queue.h>
     36 #include <machine/psl.h>
     37 
     38 /* Probably want to dealwith IPL's here @@@ */
     39 
     40 #ifdef _KERNEL
     41 
     42 /* spl0 requires checking for software interrupts */
     43 
     44 /* watch out for side effects */
     45 #define splx(s)         ((s) & PSL_IPL ? _spl(s) : spl0())
     46 
     47 /****************************************************************/
     48 
     49 #define splhigh()       spl7()
     50 #define splserial()     _splraise(PSL_S|PSL_IPL5)
     51 #define splsched()      spl7()
     52 #define spllock()	spl7()
     53 #define splclock()      _splraise(PSL_S|PSL_IPL3)
     54 #define splstatclock()  splclock()
     55 #define splvm()         _splraise(PSL_S|PSL_IPL6)
     56 #define spltty()        _splraise(PSL_S|PSL_IPL3)
     57 #define splbio()        _splraise(PSL_S|PSL_IPL3)
     58 #define splnet()        _splraise(PSL_S|PSL_IPL3)
     59 #define splsoftnet()    _splraise(PSL_S|PSL_IPL2)
     60 #define	splsoftclock()	splraise1()
     61 #define spllowersoftclock() spl1()
     62 
     63 #define spldma()        _splraise(PSL_S|PSL_IPL6)
     64 
     65 /****************************************************************/
     66 
     67 /*
     68  * simulated software interrupt register
     69  */
     70 extern volatile u_int8_t ssir;
     71 
     72 #define	SIR_NET		0x01
     73 #define	SIR_CLOCK	0x02
     74 #define	SIR_SERIAL	0x04
     75 #define SIR_DTMGR	0x08
     76 #define SIR_ADB		0x10
     77 
     78 #define	siron(mask)	\
     79 	__asm __volatile ( "orb %1,%0" : "=m" (ssir) : "i" (mask))
     80 #define	siroff(mask)	\
     81 	__asm __volatile ( "andb %1,%0" : "=m" (ssir) : "ir" (~(mask)));
     82 
     83 #define	setsoftnet()	siron(SIR_NET)
     84 #define	setsoftclock()	siron(SIR_CLOCK)
     85 #define	setsoftserial()	siron(SIR_SERIAL)
     86 #define	setsoftdtmgr()	siron(SIR_DTMGR)
     87 #define	setsoftadb()	siron(SIR_ADB)
     88 
     89 extern u_long allocate_sir __P((void (*)(void *),void *));
     90 extern void init_sir __P((void));
     91 
     92 /* locore.s */
     93 int	spl0 __P((void));
     94 
     95 extern volatile u_long *intrstat;
     96 extern volatile u_long *intrmask;
     97 #define INTR_SETMASK(x)		(*intrmask = (x))
     98 #define INTR_ENABLE(x)		(*intrmask |= NEXT_I_BIT(x))
     99 #define INTR_DISABLE(x)		(*intrmask &= (~NEXT_I_BIT(x)))
    100 #define INTR_OCCURRED(x)	(*intrstat & NEXT_I_BIT(x))
    101 
    102 #endif /* _KERNEL */
    103 
    104 #endif /* _NEXT68K_INTR_H_ */
    105