pte.h revision 1.2 1 1.2 dbj /* $NetBSD: pte.h,v 1.2 1998/08/28 23:05:54 dbj Exp $ */
2 1.2 dbj
3 1.2 dbj /*
4 1.2 dbj * This file was taken from from mvme68k/include/pte.h and
5 1.2 dbj * should probably be re-synced when needed.
6 1.2 dbj * Darrin B Jewell <jewell (at) mit.edu> Fri Aug 28 03:22:07 1998
7 1.2 dbj * original cvs id: NetBSD: pte.h,v 1.1.1.1 1995/07/25 23:12:17 chuck Exp
8 1.2 dbj */
9 1.2 dbj
10 1.1 dbj
11 1.1 dbj /*
12 1.1 dbj * Copyright (c) 1988 University of Utah.
13 1.1 dbj * Copyright (c) 1982, 1986, 1990, 1993
14 1.1 dbj * The Regents of the University of California. All rights reserved.
15 1.1 dbj *
16 1.1 dbj * This code is derived from software contributed to Berkeley by
17 1.1 dbj * the Systems Programming Group of the University of Utah Computer
18 1.1 dbj * Science Department.
19 1.1 dbj *
20 1.1 dbj * Redistribution and use in source and binary forms, with or without
21 1.1 dbj * modification, are permitted provided that the following conditions
22 1.1 dbj * are met:
23 1.1 dbj * 1. Redistributions of source code must retain the above copyright
24 1.1 dbj * notice, this list of conditions and the following disclaimer.
25 1.1 dbj * 2. Redistributions in binary form must reproduce the above copyright
26 1.1 dbj * notice, this list of conditions and the following disclaimer in the
27 1.1 dbj * documentation and/or other materials provided with the distribution.
28 1.1 dbj * 3. All advertising materials mentioning features or use of this software
29 1.1 dbj * must display the following acknowledgement:
30 1.1 dbj * This product includes software developed by the University of
31 1.1 dbj * California, Berkeley and its contributors.
32 1.1 dbj * 4. Neither the name of the University nor the names of its contributors
33 1.1 dbj * may be used to endorse or promote products derived from this software
34 1.1 dbj * without specific prior written permission.
35 1.1 dbj *
36 1.1 dbj * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
37 1.1 dbj * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
38 1.1 dbj * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
39 1.1 dbj * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
40 1.1 dbj * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
41 1.1 dbj * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
42 1.1 dbj * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
43 1.1 dbj * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
44 1.1 dbj * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
45 1.1 dbj * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
46 1.1 dbj * SUCH DAMAGE.
47 1.1 dbj *
48 1.1 dbj * from: Utah $Hdr: pte.h 1.13 92/01/20$
49 1.1 dbj *
50 1.1 dbj * @(#)pte.h 8.1 (Berkeley) 6/10/93
51 1.1 dbj */
52 1.1 dbj
53 1.2 dbj #ifndef _MACHINE_PTE_H_
54 1.2 dbj #define _MACHINE_PTE_H_
55 1.1 dbj
56 1.1 dbj /*
57 1.2 dbj * m68k hardware segment/page table entries
58 1.1 dbj */
59 1.1 dbj
60 1.1 dbj #if 0
61 1.1 dbj struct ste {
62 1.1 dbj unsigned int sg_pfnum:20; /* page table frame number */
63 1.1 dbj unsigned int :8; /* reserved at 0 */
64 1.1 dbj unsigned int :1; /* reserved at 1 */
65 1.1 dbj unsigned int sg_prot:1; /* write protect bit */
66 1.1 dbj unsigned int sg_v:2; /* valid bits */
67 1.1 dbj };
68 1.1 dbj
69 1.1 dbj struct ste40 {
70 1.1 dbj unsigned int sg_ptaddr:24; /* page table page addr */
71 1.1 dbj unsigned int :4; /* reserved at 0 */
72 1.1 dbj unsigned int sg_u; /* hardware modified (dirty) bit */
73 1.1 dbj unsigned int sg_prot:1; /* write protect bit */
74 1.1 dbj unsigned int sg_v:2; /* valid bits */
75 1.1 dbj };
76 1.1 dbj
77 1.1 dbj struct pte {
78 1.1 dbj unsigned int pg_pfnum:20; /* page frame number or 0 */
79 1.1 dbj unsigned int :3;
80 1.1 dbj unsigned int pg_w:1; /* is wired */
81 1.1 dbj unsigned int :1; /* reserved at zero */
82 1.1 dbj unsigned int pg_ci:1; /* cache inhibit bit */
83 1.1 dbj unsigned int :1; /* reserved at zero */
84 1.1 dbj unsigned int pg_m:1; /* hardware modified (dirty) bit */
85 1.1 dbj unsigned int pg_u:1; /* hardware used (reference) bit */
86 1.1 dbj unsigned int pg_prot:1; /* write protect bit */
87 1.1 dbj unsigned int pg_v:2; /* valid bit */
88 1.1 dbj };
89 1.1 dbj #endif
90 1.1 dbj
91 1.1 dbj typedef int st_entry_t; /* segment table entry */
92 1.1 dbj typedef int pt_entry_t; /* Mach page table entry */
93 1.1 dbj
94 1.1 dbj #define PT_ENTRY_NULL ((pt_entry_t *) 0)
95 1.1 dbj #define ST_ENTRY_NULL ((st_entry_t *) 0)
96 1.1 dbj
97 1.1 dbj #define SG_V 0x00000002 /* segment is valid */
98 1.1 dbj #define SG_NV 0x00000000
99 1.1 dbj #define SG_PROT 0x00000004 /* access protection mask */
100 1.1 dbj #define SG_RO 0x00000004
101 1.1 dbj #define SG_RW 0x00000000
102 1.1 dbj #define SG_U 0x00000008 /* modified bit (68040) */
103 1.1 dbj #define SG_FRAME 0xfffff000
104 1.1 dbj #define SG_IMASK 0xffc00000
105 1.1 dbj #define SG_ISHIFT 22
106 1.1 dbj #define SG_PMASK 0x003ff000
107 1.1 dbj #define SG_PSHIFT 12
108 1.1 dbj
109 1.1 dbj /* 68040 additions */
110 1.1 dbj #define SG4_MASK1 0xfe000000
111 1.1 dbj #define SG4_SHIFT1 25
112 1.1 dbj #define SG4_MASK2 0x01fc0000
113 1.1 dbj #define SG4_SHIFT2 18
114 1.1 dbj #define SG4_MASK3 0x0003f000
115 1.1 dbj #define SG4_SHIFT3 12
116 1.1 dbj #define SG4_ADDR1 0xfffffe00
117 1.1 dbj #define SG4_ADDR2 0xffffff00
118 1.1 dbj #define SG4_LEV1SIZE 128
119 1.1 dbj #define SG4_LEV2SIZE 128
120 1.1 dbj #define SG4_LEV3SIZE 64
121 1.1 dbj
122 1.1 dbj #define PG_V 0x00000001
123 1.1 dbj #define PG_NV 0x00000000
124 1.1 dbj #define PG_PROT 0x00000004
125 1.1 dbj #define PG_U 0x00000008
126 1.1 dbj #define PG_M 0x00000010
127 1.1 dbj #define PG_W 0x00000100
128 1.1 dbj #define PG_RO 0x00000004
129 1.1 dbj #define PG_RW 0x00000000
130 1.1 dbj #define PG_FRAME 0xfffff000
131 1.1 dbj #define PG_CI 0x00000040
132 1.1 dbj #define PG_SHIFT 12
133 1.1 dbj #define PG_PFNUM(x) (((x) & PG_FRAME) >> PG_SHIFT)
134 1.1 dbj
135 1.1 dbj /* 68040 additions */
136 1.1 dbj #define PG_CMASK 0x00000060 /* cache mode mask */
137 1.1 dbj #define PG_CWT 0x00000000 /* writethrough caching */
138 1.1 dbj #define PG_CCB 0x00000020 /* copyback caching */
139 1.1 dbj #define PG_CIS 0x00000040 /* cache inhibited serialized */
140 1.1 dbj #define PG_CIN 0x00000060 /* cache inhibited nonserialized */
141 1.1 dbj #define PG_SO 0x00000080 /* supervisor only */
142 1.1 dbj
143 1.1 dbj #define HP_STSIZE (MAXUL2SIZE*SG4_LEV2SIZE*sizeof(st_entry_t))
144 1.1 dbj /* user process segment table size */
145 1.1 dbj #define HP_MAX_PTSIZE 0x400000 /* max size of UPT */
146 1.1 dbj #define HP_MAX_KPTSIZE 0x100000 /* max memory to allocate to KPT */
147 1.1 dbj #define HP_PTBASE 0x10000000 /* UPT map base address */
148 1.1 dbj #define HP_PTMAXSIZE 0x70000000 /* UPT map maximum size */
149 1.1 dbj
150 1.1 dbj /*
151 1.1 dbj * Kernel virtual address to page table entry and to physical address.
152 1.1 dbj */
153 1.1 dbj #define kvtopte(va) \
154 1.1 dbj (&Sysmap[((unsigned)(va) - VM_MIN_KERNEL_ADDRESS) >> PGSHIFT])
155 1.1 dbj #define ptetokv(pt) \
156 1.1 dbj ((((pt_entry_t *)(pt) - Sysmap) << PGSHIFT) + VM_MIN_KERNEL_ADDRESS)
157 1.1 dbj #define kvtophys(va) \
158 1.1 dbj ((kvtopte(va)->pg_pfnum << PGSHIFT) | ((int)(va) & PGOFSET))
159 1.1 dbj
160 1.2 dbj #endif /* !_MACHINE_PTE_H_ */
161