gt_mainbus.c revision 1.2.2.2
1 /* $NetBSD: gt_mainbus.c,v 1.2.2.2 2010/07/03 01:19:25 rmind Exp $ */ 2 /* 3 * Copyright (c) 2010 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: gt_mainbus.c,v 1.2.2.2 2010/07/03 01:19:25 rmind Exp $"); 30 31 #include "opt_pci.h" 32 #include "opt_marvell.h" 33 #include "gtpci.h" 34 #include "pci.h" 35 #include "isa.h" 36 37 #define _POWERPC_BUS_DMA_PRIVATE 38 39 #include <sys/param.h> 40 #include <sys/device.h> 41 #include <sys/errno.h> 42 #include <sys/extent.h> 43 #include <sys/malloc.h> 44 45 #include <machine/autoconf.h> 46 #include <machine/bus.h> 47 #include <machine/isa_machdep.h> 48 #include <machine/pegasosreg.h> 49 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pciconf.h> 52 53 #include <dev/marvell/gtreg.h> 54 #include <dev/marvell/gtvar.h> 55 #include <dev/marvell/gtpcireg.h> 56 #include <dev/marvell/gtpcivar.h> 57 #include <dev/marvell/marvellvar.h> 58 #include <dev/ofw/openfirm.h> 59 60 61 static int gt_match(device_t, cfdata_t, void *); 62 static void gt_attach(device_t, device_t, void *); 63 64 #if NGTPCI > 0 65 static void gtpci_md_attach_hook(device_t, device_t, 66 struct pcibus_attach_args *); 67 void gtpci_md_conf_interrupt(void *, int, int, int, int, int *); 68 int gtpci_md_conf_hook(void *, int, int, int, pcireg_t); 69 #endif 70 71 CFATTACH_DECL_NEW(gt, sizeof(struct gt_softc), gt_match, gt_attach, NULL, NULL); 72 73 static struct powerpc_bus_space pegasosii_gt_bs_tag = { 74 .pbs_offset = PEGASOS2_GT_REGBASE, 75 .pbs_base = 0x00000000, 76 .pbs_limit = GT_SIZE, 77 }; 78 static char ex_storage[EXTENT_FIXED_STORAGE_SIZE(8)] 79 __attribute__((aligned(8))); 80 81 struct powerpc_bus_dma_tag pegasosii_bus_dma_tag = { 82 0, /* _bounce_thresh */ 83 _bus_dmamap_create, 84 _bus_dmamap_destroy, 85 _bus_dmamap_load, 86 _bus_dmamap_load_mbuf, 87 _bus_dmamap_load_uio, 88 _bus_dmamap_load_raw, 89 _bus_dmamap_unload, 90 _bus_dmamap_sync, 91 _bus_dmamem_alloc, 92 _bus_dmamem_free, 93 _bus_dmamem_map, 94 _bus_dmamem_unmap, 95 _bus_dmamem_mmap, 96 }; 97 98 #if NGTPCI > 0 99 struct powerpc_bus_space 100 gtpci0_io_bs_tag, gtpci0_mem_bs_tag, 101 gtpci1_io_bs_tag, gtpci1_mem_bs_tag; 102 #endif 103 104 struct gtpci_prot gtpci0_prot = { 105 GTPCI_ACBL_RDSIZE_32BYTE | 106 GTPCI_ACBL_RDMBURST_32BYTE | 107 GTPCI_ACBL_PCISWAP_BYTESWAP | 108 GTPCI_ACBL_SNOOP_WB | 109 GTPCI_ACBL_EN, 110 0, 111 }, gtpci1_prot = { 112 GTPCI_ACBL_RDSIZE_128BYTE | 113 GTPCI_ACBL_RDMBURST_32BYTE | 114 GTPCI_ACBL_PCISWAP_BYTESWAP | 115 GTPCI_ACBL_SNOOP_WB | 116 GTPCI_ACBL_EN, 117 0, 118 }; 119 120 121 int 122 gt_match(device_t parent, cfdata_t cf, void *aux) 123 { 124 struct confargs *ca = aux; 125 int node, pci, ethernet; 126 char name[32]; 127 128 if (strcmp(ca->ca_name, "gt") != 0 || 129 strcmp(model_name, "Pegasos2") != 0) 130 return 0; 131 132 /* Paranoid check... */ 133 134 pci = ethernet = 0; 135 for (node = OF_child(OF_finddevice("/")); node; node = OF_peer(node)) { 136 memset(name, 0, sizeof(name)); 137 if (OF_getprop(node, "name", name, sizeof(name)) == -1) 138 continue; 139 if (strcmp(name, "pci") == 0) 140 pci++; 141 else if (strcmp(name, "ethernet") == 0) 142 ethernet++; 143 144 } 145 if (pci == 2 && (ethernet == 1 || ethernet == 0)) 146 return 1; 147 return 0; 148 } 149 150 /* ARGSUSED */ 151 void 152 gt_attach(device_t parent, device_t self, void *aux) 153 { 154 struct gt_softc *sc = device_private(self); 155 #if NGTPCI > 0 156 uint32_t busrange[2]; 157 int node; 158 extern struct genppc_pci_chipset 159 genppc_gtpci0_chipset, genppc_gtpci1_chipset; 160 #endif 161 162 bus_space_init(&pegasosii_gt_bs_tag, "gt", 163 ex_storage, sizeof(ex_storage)); 164 165 sc->sc_dev = self; 166 sc->sc_addr = 0x00000000; 167 sc->sc_iot = &pegasosii_gt_bs_tag; 168 sc->sc_dmat = &pegasosii_bus_dma_tag; 169 170 if (bus_space_map(sc->sc_iot, sc->sc_addr, GT_SIZE, 0, &sc->sc_ioh) != 171 0) { 172 aprint_error(": registers map failed\n"); 173 return; 174 } 175 176 init_ofppc_interrupt(); 177 178 #if NGTPCI > 0 179 /* bus space map the I/O and Memory ranges of PCI unit 1(PCI bus) */ 180 node = of_find_firstchild_byname(OF_finddevice("/"), "pci"); 181 if (node != -1) { 182 gtpci1_io_bs_tag.pbs_flags = 183 _BUS_SPACE_LITTLE_ENDIAN | _BUS_SPACE_IO_TYPE; 184 gtpci1_io_bs_tag.pbs_base = 0x00000000; 185 if (ofwoea_map_space(RANGE_TYPE_PCI, RANGE_IO, node, 186 >pci1_io_bs_tag, "gtpci 1 io-space") != 0) 187 panic("Can't init gtpci 1 io tag"); 188 gtpci1_mem_bs_tag.pbs_flags = 189 _BUS_SPACE_LITTLE_ENDIAN | _BUS_SPACE_MEM_TYPE; 190 gtpci1_mem_bs_tag.pbs_base = 0x00000000; 191 if (ofwoea_map_space(RANGE_TYPE_PCI, RANGE_MEM, node, 192 >pci1_mem_bs_tag, "gtpci 1 mem-space") != 0) 193 panic("Can't init gtpci 1 mem tag"); 194 195 /* PCI bus number */ 196 if (OF_getprop(node, "bus-range", busrange, sizeof(busrange)) != 197 sizeof(busrange)) { 198 aprint_error(": PCI bus range failed\n"); 199 return; 200 } 201 202 /* Override some functions */ 203 genppc_gtpci1_chipset.pc_attach_hook = gtpci_md_attach_hook; 204 genppc_gtpci1_chipset.pc_intr_map = genofw_pci_intr_map; 205 genppc_gtpci1_chipset.pc_node = node; 206 genppc_gtpci1_chipset.pc_bus = busrange[0]; 207 genppc_gtpci1_chipset.pc_iot = >pci1_io_bs_tag; 208 genppc_gtpci1_chipset.pc_memt = >pci1_mem_bs_tag; 209 210 #if NISA > 0 211 genppc_isa_io_space_tag = gtpci1_io_bs_tag; 212 genppc_isa_mem_space_tag = gtpci1_mem_bs_tag; 213 map_isa_ioregs(); 214 ofppc_init_comcons(of_find_firstchild_byname(node, "isa")); 215 #endif 216 } 217 218 /* bus space map the I/O and Memory ranges of PCI unit 0(AGP bus) */ 219 if (node != -1) 220 node = of_getnode_byname(OF_peer(node), "pci"); 221 if (node != -1 && node != 0) { 222 gtpci0_io_bs_tag.pbs_flags = 223 _BUS_SPACE_LITTLE_ENDIAN | _BUS_SPACE_IO_TYPE; 224 gtpci0_io_bs_tag.pbs_base = 0x00000000; 225 if (ofwoea_map_space(RANGE_TYPE_PCI, RANGE_IO, node, 226 >pci0_io_bs_tag, "gtpci 0 io-space") != 0) 227 panic("Can't init gtpci 0 io tag"); 228 gtpci0_mem_bs_tag.pbs_flags = 229 _BUS_SPACE_LITTLE_ENDIAN | _BUS_SPACE_MEM_TYPE; 230 gtpci0_mem_bs_tag.pbs_base = 0x00000000; 231 if (ofwoea_map_space(RANGE_TYPE_PCI, RANGE_MEM, node, 232 >pci0_mem_bs_tag, "gtpci 0 mem-space") != 0) 233 panic("Can't init gtpci 0 mem tag"); 234 235 /* PCI bus number */ 236 if (OF_getprop(node, "bus-range", busrange, sizeof(busrange)) != 237 sizeof(busrange)) { 238 aprint_error(": AGP bus range failed\n"); 239 return; 240 } 241 242 genppc_gtpci0_chipset.pc_node = node; 243 genppc_gtpci0_chipset.pc_bus = busrange[0]; 244 genppc_gtpci0_chipset.pc_iot = >pci0_io_bs_tag; 245 genppc_gtpci0_chipset.pc_memt = >pci0_mem_bs_tag; 246 247 /* Enable access to space of configuration for AGP. */ 248 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GT_GPP_Value_Set, 249 (1 << 23)); 250 } 251 #endif 252 253 gt_attach_common(sc); 254 255 #if NGTPCI > 0 256 /* Disable access to space of configuration for AGP. */ 257 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GT_GPP_Value_Clear, 258 (1 << 23)); 259 #endif 260 } 261 262 263 #if NGTPCI > 0 264 static void 265 gtpci_md_attach_hook(device_t parent, device_t self, 266 struct pcibus_attach_args *pba) 267 { 268 extern struct genppc_pci_chipset genppc_gtpci1_chipset; 269 270 if (device_is_a(parent, "gtpci") && 271 pba->pba_pc == &genppc_gtpci1_chipset) { 272 /* Setup interrupts for PCI bus */ 273 struct genppc_pci_chipset_businfo *pbi; 274 275 pbi = malloc(sizeof(struct genppc_pci_chipset_businfo), 276 M_DEVBUF, M_NOWAIT); 277 KASSERT(pbi != NULL); 278 pbi->pbi_properties = prop_dictionary_create(); 279 KASSERT(pbi->pbi_properties != NULL); 280 SIMPLEQ_INIT(&genppc_gtpci1_chipset.pc_pbi); 281 SIMPLEQ_INSERT_TAIL(&genppc_gtpci1_chipset.pc_pbi, pbi, next); 282 283 genofw_setup_pciintr_map(&genppc_gtpci1_chipset, pbi, 284 genppc_gtpci1_chipset.pc_node); 285 } 286 gtpci_attach_hook(parent, self, pba); 287 } 288 289 /* ARGSUSED */ 290 void 291 gtpci_md_conf_interrupt(void * v, int bus, int dev, int pin, int swiz, 292 int *iline) 293 { 294 295 /* do nothing */ 296 } 297 298 int 299 gtpci_md_conf_hook(void *v, int bus, int dev, int func, pcireg_t id) 300 { 301 struct gtpci_softc *sc = v; 302 303 if (gtpci_conf_hook(sc->sc_pc, bus, dev, func, id) == 0) 304 return 0; 305 return genofw_pci_conf_hook(sc->sc_pc, bus, dev, func, id); 306 } 307 #endif 308 309 310 void * 311 marvell_intr_establish(int irq, int ipl, int (*func)(void *), void *arg) 312 { 313 314 /* pass through */ 315 return intr_establish(irq, IST_LEVEL, ipl, func, arg); 316 } 317
Indexes created Mon Oct 20 05:10:11 GMT 2025