1 1.3 pooka /* $NetBSD: spdreg.h,v 1.4 2014/03/31 11:25:49 martin Exp $ */ 2 1.1 uch 3 1.1 uch /*- 4 1.1 uch * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 1.1 uch * All rights reserved. 6 1.1 uch * 7 1.1 uch * This code is derived from software contributed to The NetBSD Foundation 8 1.1 uch * by UCHIYAMA Yasushi. 9 1.1 uch * 10 1.1 uch * Redistribution and use in source and binary forms, with or without 11 1.1 uch * modification, are permitted provided that the following conditions 12 1.1 uch * are met: 13 1.1 uch * 1. Redistributions of source code must retain the above copyright 14 1.1 uch * notice, this list of conditions and the following disclaimer. 15 1.1 uch * 2. Redistributions in binary form must reproduce the above copyright 16 1.1 uch * notice, this list of conditions and the following disclaimer in the 17 1.1 uch * documentation and/or other materials provided with the distribution. 18 1.1 uch * 19 1.1 uch * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 1.1 uch * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 1.1 uch * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 1.1 uch * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 1.1 uch * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 1.1 uch * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 1.1 uch * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 1.1 uch * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 1.1 uch * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 1.1 uch * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 1.1 uch * POSSIBILITY OF SUCH DAMAGE. 30 1.1 uch */ 31 1.1 uch 32 1.1 uch /* 33 1.1 uch * spd (PlayStation 2 HDD UNIT) common register define. 34 1.1 uch */ 35 1.1 uch 36 1.1 uch /* interrupt */ 37 1.1 uch #define SPD_INTR_ENABLE_REG16 MIPS_PHYS_TO_KSEG1(0x1400002a) 38 1.1 uch #define SPD_INTR_STATUS_REG16 MIPS_PHYS_TO_KSEG1(0x14000028) 39 1.1 uch #define SPD_INTR_CLEAR_REG16 MIPS_PHYS_TO_KSEG1(0x14000128) 40 1.1 uch #define SPD_INTR_EMAC3 0x0040 41 1.1 uch #define SPD_INTR_RXEND 0x0020 42 1.1 uch #define SPD_INTR_TXEND 0x0010 43 1.1 uch #define SPD_INTR_RXDNV 0x0008 44 1.1 uch #define SPD_INTR_TXDNV 0x0004 45 1.1 uch #define SPD_INTR_HDD 0x0001 46 1.1 uch 47 1.1 uch /* I/O port */ 48 1.1 uch #define SPD_IO_DIR_REG8 MIPS_PHYS_TO_KSEG1(0x1400002c) 49 1.1 uch #define SPD_IO_DATA_REG8 MIPS_PHYS_TO_KSEG1(0x1400002e) 50 1.1 uch /* HDD LED */ 51 1.1 uch #define SPD_IO_LED 0x0001 52 1.1 uch /* EEPROM (ethernet address) */ 53 1.1 uch #define SPD_IO_OUT 0x0010 54 1.1 uch #define SPD_IO_IN 0x0020 55 1.1 uch #define SPD_IO_CLK 0x0040 56 1.1 uch #define SPD_IO_CS 0x0080 57 1.1 uch 58 1.1 uch /* HDD interface */ 59 1.1 uch #define SPD_XFR_CTRL_REG8 MIPS_PHYS_TO_KSEG1(0x14000032) 60 1.1 uch #define SPD_HDD_IO_BASE MIPS_PHYS_TO_KSEG1(0x14000040) 61 1.1 uch #define SPD_IF_CTRL_REG8 MIPS_PHYS_TO_KSEG1(0x14000064) 62 1.1 uch #define SPD_IF_CTRL_ATA_RST 0x80 63 1.1 uch #define SPD_IF_CTRL_DMA_EN 0x04 64 1.1 uch 65
Indexes created Thu Sep 25 02:09:54 GMT 2025