wdc_spd.c revision 1.25
1 /* $NetBSD: wdc_spd.c,v 1.25 2009/03/18 10:22:33 cegger Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: wdc_spd.c,v 1.25 2009/03/18 10:22:33 cegger Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 39 #define __read_1(a) \ 40 ({ \ 41 u_int32_t ra_ = (a); \ 42 u_int8_t r = (*(volatile u_int8_t *)ra_); \ 43 \ 44 if (ra_ == 0xb400004e) /* (wdc)STAT LED off */ \ 45 SPD_LED_OFF(); \ 46 \ 47 (r); \ 48 }) 49 #define __write_1(a, v) \ 50 { \ 51 u_int32_t wa_ = (a); \ 52 (*(volatile u_int8_t *)wa_) = (v); \ 53 \ 54 if (wa_ == 0xb400004e) /* (wdc)CMD LED on */ \ 55 SPD_LED_ON(); \ 56 } 57 #define _PLAYSTATION2_BUS_SPACE_PRIVATE 58 #include <machine/bus.h> 59 60 #include <dev/ata/atavar.h> 61 #include <dev/ic/wdcvar.h> 62 63 #include <playstation2/ee/eevar.h> 64 #include <playstation2/dev/spdvar.h> 65 #include <playstation2/dev/spdreg.h> 66 67 #define WDC_SPD_HDD_AUXREG_OFFSET 0x1c 68 69 struct wdc_spd_softc { 70 struct wdc_softc sc_wdcdev; 71 struct ata_channel *sc_chanlist[1]; 72 struct ata_channel sc_channel; 73 struct ata_queue sc_chqueue; 74 struct wdc_regs sc_wdc_regs; 75 void *sc_ih; 76 }; 77 78 #ifdef DEBUG 79 #define STATIC 80 #else 81 #define STATIC static 82 #endif 83 84 STATIC int wdc_spd_match(device_t, cfdata_t, void *); 85 STATIC void wdc_spd_attach(device_t, device_t, void *); 86 87 CFATTACH_DECL_NEW(wdc_spd, sizeof (struct wdc_spd_softc), 88 wdc_spd_match, wdc_spd_attach, NULL, NULL); 89 90 extern struct cfdriver wdc_cd; 91 92 STATIC void __wdc_spd_enable(void); 93 STATIC void __wdc_spd_disable(void) __attribute__((__unused__)); 94 STATIC void __wdc_spd_bus_space(struct ata_channel *); 95 96 /* 97 * wdc register is 16 bit wide. 98 */ 99 #define VADDR(h, o) ((h) + (o)) 100 _BUS_SPACE_READ(_wdc_spd, 1, 8) 101 _BUS_SPACE_READ(_wdc_spd, 2, 16) 102 _BUS_SPACE_READ_MULTI(_wdc_spd, 1, 8) 103 _BUS_SPACE_READ_MULTI(_wdc_spd, 2, 16) 104 _BUS_SPACE_READ_REGION(_wdc_spd, 1, 8) 105 _BUS_SPACE_READ_REGION(_wdc_spd, 2, 16) 106 _BUS_SPACE_WRITE(_wdc_spd, 1, 8) 107 _BUS_SPACE_WRITE(_wdc_spd, 2, 16) 108 _BUS_SPACE_WRITE_MULTI(_wdc_spd, 1, 8) 109 _BUS_SPACE_WRITE_MULTI(_wdc_spd, 2, 16) 110 _BUS_SPACE_WRITE_REGION(_wdc_spd, 1, 8) 111 _BUS_SPACE_WRITE_REGION(_wdc_spd, 2, 16) 112 _BUS_SPACE_SET_MULTI(_wdc_spd, 1, 8) 113 _BUS_SPACE_SET_MULTI(_wdc_spd, 2, 16) 114 _BUS_SPACE_SET_REGION(_wdc_spd, 1, 8) 115 _BUS_SPACE_SET_REGION(_wdc_spd, 2, 16) 116 _BUS_SPACE_COPY_REGION(_wdc_spd, 1, 8) 117 _BUS_SPACE_COPY_REGION(_wdc_spd, 2, 16) 118 #undef VADDR 119 120 STATIC const struct playstation2_bus_space _wdc_spd_space = { 121 pbs_map : _BUS_SPACE_NO_MAP, 122 pbs_unmap : _BUS_SPACE_NO_UNMAP, 123 pbs_subregion : _BUS_SPACE_NO_SUBREGION, 124 pbs_alloc : _BUS_SPACE_NO_ALLOC, 125 pbs_free : _BUS_SPACE_NO_FREE, 126 pbs_vaddr : _BUS_SPACE_NO_VADDR, 127 pbs_r_1 : _wdc_spd_read_1, 128 pbs_r_2 : _wdc_spd_read_2, 129 pbs_r_4 : _BUS_SPACE_NO_READ(4, 32), 130 pbs_r_8 : _BUS_SPACE_NO_READ(8, 64), 131 pbs_rm_1 : _wdc_spd_read_multi_1, 132 pbs_rm_2 : _wdc_spd_read_multi_2, 133 pbs_rm_4 : _BUS_SPACE_NO_READ_MULTI(4, 32), 134 pbs_rm_8 : _BUS_SPACE_NO_READ_MULTI(8, 64), 135 pbs_rr_1 : _wdc_spd_read_region_1, 136 pbs_rr_2 : _wdc_spd_read_region_2, 137 pbs_rr_4 : _BUS_SPACE_NO_READ_REGION(4, 32), 138 pbs_rr_8 : _BUS_SPACE_NO_READ_REGION(8, 64), 139 pbs_w_1 : _wdc_spd_write_1, 140 pbs_w_2 : _wdc_spd_write_2, 141 pbs_w_4 : _BUS_SPACE_NO_WRITE(4, 32), 142 pbs_w_8 : _BUS_SPACE_NO_WRITE(8, 64), 143 pbs_wm_1 : _wdc_spd_write_multi_1, 144 pbs_wm_2 : _wdc_spd_write_multi_2, 145 pbs_wm_4 : _BUS_SPACE_NO_WRITE_MULTI(4, 32), 146 pbs_wm_8 : _BUS_SPACE_NO_WRITE_MULTI(8, 64), 147 pbs_wr_1 : _wdc_spd_write_region_1, 148 pbs_wr_2 : _wdc_spd_write_region_2, 149 pbs_wr_4 : _BUS_SPACE_NO_WRITE_REGION(4, 32), 150 pbs_wr_8 : _BUS_SPACE_NO_WRITE_REGION(8, 64), 151 pbs_sm_1 : _wdc_spd_set_multi_1, 152 pbs_sm_2 : _wdc_spd_set_multi_2, 153 pbs_sm_4 : _BUS_SPACE_NO_SET_MULTI(4, 32), 154 pbs_sm_8 : _BUS_SPACE_NO_SET_MULTI(8, 64), 155 pbs_sr_1 : _wdc_spd_set_region_1, 156 pbs_sr_2 : _wdc_spd_set_region_2, 157 pbs_sr_4 : _BUS_SPACE_NO_SET_REGION(4, 32), 158 pbs_sr_8 : _BUS_SPACE_NO_SET_REGION(8, 64), 159 pbs_c_1 : _wdc_spd_copy_region_1, 160 pbs_c_2 : _wdc_spd_copy_region_2, 161 pbs_c_4 : _BUS_SPACE_NO_COPY_REGION(4, 32), 162 pbs_c_8 : _BUS_SPACE_NO_COPY_REGION(8, 64), 163 }; 164 165 int 166 wdc_spd_match(device_t parent, cfdata_t cf, void *aux) 167 { 168 struct spd_attach_args *spa = aux; 169 struct ata_channel ch; 170 struct wdc_softc wdc; 171 struct wdc_regs wdr; 172 int i, result; 173 174 if (spa->spa_slot != SPD_HDD) 175 return (0); 176 177 memset(&wdc, 0, sizeof(wdc)); 178 memset(&ch, 0, sizeof(ch)); 179 ch.ch_atac = &wdc.sc_atac; 180 wdc.regs = &wdr; 181 182 __wdc_spd_bus_space(&ch); 183 184 for (i = 0, result = 0; i < 8; i++) { /* 8 sec */ 185 if (result == 0) 186 result = wdcprobe(&ch); 187 delay(1000000); 188 } 189 190 return (result); 191 } 192 193 void 194 wdc_spd_attach(device_t parent, device_t self, void *aux) 195 { 196 struct spd_attach_args *spa = aux; 197 struct wdc_spd_softc *sc = device_private(self); 198 struct wdc_softc *wdc = &sc->sc_wdcdev; 199 struct ata_channel *ch = &sc->sc_channel; 200 201 aprint_normal(": %s\n", spa->spa_product_name); 202 203 sc->sc_wdcdev.sc_atac.atac_dev = self; 204 sc->sc_wdcdev.regs = &sc->sc_wdc_regs; 205 206 wdc->sc_atac.atac_cap = 207 ATAC_CAP_DMA | ATAC_CAP_UDMA | ATAC_CAP_DATA16; 208 wdc->sc_atac.atac_pio_cap = 0; 209 sc->sc_chanlist[0] = &sc->sc_channel; 210 wdc->sc_atac.atac_channels = sc->sc_chanlist; 211 wdc->sc_atac.atac_nchannels = 1; 212 ch->ch_channel = 0; 213 ch->ch_atac = &sc->sc_wdcdev.sc_atac; 214 ch->ch_queue = &sc->sc_chqueue; 215 ch->ch_ndrive = 2; 216 217 __wdc_spd_bus_space(ch); 218 219 spd_intr_establish(SPD_HDD, wdcintr, &sc->sc_channel); 220 221 __wdc_spd_enable(); 222 223 wdcattach(&sc->sc_channel); 224 } 225 226 void 227 __wdc_spd_bus_space(struct ata_channel *ch) 228 { 229 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(ch); 230 int i; 231 232 wdr->cmd_iot = &_wdc_spd_space; 233 for (i = 0; i < 8; i++) 234 wdr->cmd_iohs[i] = SPD_HDD_IO_BASE + i * 2; /* wdc register is 16 bit wide. */ 235 wdc_init_shadow_regs(ch); 236 wdr->ctl_iot = &_wdc_spd_space; 237 wdr->ctl_ioh = SPD_HDD_IO_BASE + WDC_SPD_HDD_AUXREG_OFFSET; 238 wdr->data32iot = wdr->cmd_iot; 239 wdr->data32ioh = SPD_HDD_IO_BASE; 240 } 241 242 void 243 __wdc_spd_enable(void) 244 { 245 u_int16_t r; 246 247 r = _reg_read_2(SPD_INTR_ENABLE_REG16); 248 r |= SPD_INTR_HDD; 249 _reg_write_2(SPD_INTR_ENABLE_REG16, r); 250 } 251 252 void 253 __wdc_spd_disable(void) 254 { 255 u_int16_t r; 256 257 r = _reg_read_2(SPD_INTR_ENABLE_REG16); 258 r &= ~SPD_INTR_HDD; 259 _reg_write_2(SPD_INTR_ENABLE_REG16, r); 260 } 261
Indexes created Mon Sep 29 21:09:56 GMT 2025