dmac.c revision 1.1
1 /* $NetBSD: dmac.c,v 1.1 2001/10/16 15:38:36 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include "debug_playstation2.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 44 #include <playstation2/ee/eevar.h> 45 #include <playstation2/ee/dmacvar.h> 46 #include <playstation2/ee/dmacreg.h> 47 #include <playstation2/ee/gsvar.h> /* debug monitor */ 48 49 #include <playstation2/playstation2/interrupt.h> 50 51 #ifdef DEBUG 52 #define LEGAL_CHANNEL(x) ((x) >= 0 && (x) <= 15) 53 #define STATIC 54 #else 55 #define STATIC static 56 #endif 57 58 #define _DMAC_NINTR 10 59 60 STATIC vaddr_t __dmac_channel_base[_DMAC_NINTR] = { 61 D0_REGBASE, 62 D1_REGBASE, 63 D2_REGBASE, 64 D3_REGBASE, 65 D4_REGBASE, 66 D5_REGBASE, 67 D6_REGBASE, 68 D7_REGBASE, 69 D8_REGBASE, 70 D9_REGBASE 71 }; 72 73 u_int32_t __dmac_enabled_channel; 74 75 STATIC int __dmac_intialized; 76 STATIC struct _ipl_dispatcher __dmac_dispatcher[_DMAC_NINTR]; 77 STATIC struct _ipl_holder __dmac_ipl_holder[_IPL_N]; 78 STATIC SLIST_HEAD(, _ipl_dispatcher) __dmac_dispatcher_head = 79 SLIST_HEAD_INITIALIZER(__dmac_dispatcher_head); 80 81 void 82 dmac_init() 83 { 84 int i; 85 86 if (__dmac_intialized++) 87 return; 88 89 /* disable DMAC */ 90 _reg_write_4(D_ENABLEW_REG, D_ENABLE_SUSPEND); 91 92 /* disable all interrupt */ 93 for (i = 0; i < _DMAC_NINTR; i++) 94 dmac_intr_disable(i); 95 96 for (i = 0; i < _IPL_N; i++) 97 __dmac_ipl_holder[i].mask = 0xffffffff; 98 99 if (_reg_read_4(D_STAT_REG) & D_STAT_SIM) 100 _reg_write_4(D_STAT_REG, D_STAT_SIM); 101 if (_reg_read_4(D_STAT_REG) & D_STAT_MEIM) 102 _reg_write_4(D_STAT_REG, D_STAT_MEIM); 103 104 /* clear all status */ 105 _reg_write_4(D_STAT_REG, _reg_read_4(D_STAT_REG) & D_STAT_CIS_MASK); 106 107 /* enable DMAC */ 108 _reg_write_4(D_ENABLEW_REG, 0); 109 _reg_write_4(D_CTRL_REG, D_CTRL_DMAE); 110 } 111 112 /* 113 * Interrupt 114 */ 115 int 116 dmac_intr(u_int32_t mask) 117 { 118 struct _ipl_dispatcher *dispatcher; 119 u_int32_t r, dispatch, pending; 120 121 r = _reg_read_4(D_STAT_REG); 122 mask = D_STAT_CIM(mask); 123 dispatch = r & ~mask & __dmac_enabled_channel; 124 pending = r & mask & __dmac_enabled_channel; 125 #if 0 126 __gsfb_print(2, 127 "DMAC stat=%08x, mask=%08x, pend=%08x, disp=%08x enable=%08x\n", 128 r, mask, pending, dispatch, __dmac_enabled_channel); 129 #endif 130 if (dispatch == 0) 131 return (pending == 0 ? 1 : 0); 132 133 /* clear interrupt */ 134 _reg_write_4(D_STAT_REG, dispatch); 135 136 /* dispatch interrupt handler */ 137 SLIST_FOREACH(dispatcher, &__dmac_dispatcher_head, link) { 138 if (dispatcher->bit & dispatch) { 139 KDASSERT(dispatcher->func); 140 (*dispatcher->func)(dispatcher->arg); 141 dispatch &= ~dispatcher->bit; 142 } 143 } 144 145 /* disable spurious interrupt source */ 146 if (dispatch) { 147 int i, bit; 148 for (i = 0, bit = 1; i < _DMAC_NINTR; i++, bit <<= 1) { 149 if (bit & dispatch) { 150 dmac_intr_disable(i); 151 printf("%s: spurious interrupt %d disabled.\n", 152 __FUNCTION__, i); 153 } 154 } 155 } 156 157 158 return (pending == 0 ? 1 : 0); 159 } 160 161 void 162 dmac_intr_enable(enum dmac_channel ch) 163 { 164 u_int32_t mask; 165 166 KDASSERT(LEGAL_CHANNEL(ch)); 167 168 mask = D_STAT_CIM_BIT(ch); 169 _reg_write_4(D_STAT_REG, (_reg_read_4(D_STAT_REG) & mask) ^ mask); 170 } 171 172 void 173 dmac_intr_disable(enum dmac_channel ch) 174 { 175 KDASSERT(LEGAL_CHANNEL(ch)); 176 177 _reg_write_4(D_STAT_REG, _reg_read_4(D_STAT_REG) & D_STAT_CIM_BIT(ch)); 178 } 179 180 void 181 dmac_update_mask(u_int32_t mask) 182 { 183 u_int32_t cur_mask; 184 185 mask = D_STAT_CIM(mask); 186 cur_mask = _reg_read_4(D_STAT_REG); 187 188 _reg_write_4(D_STAT_REG, ((cur_mask ^ ~mask) | (cur_mask & mask)) & 189 D_STAT_CIM(__dmac_enabled_channel)); 190 } 191 192 void * 193 dmac_intr_establish(enum dmac_channel ch, int ipl, int (*func)(void *), 194 void *arg) 195 { 196 struct _ipl_dispatcher *dispatcher = &__dmac_dispatcher[ch]; 197 struct _ipl_dispatcher *d; 198 int i, s; 199 200 KDASSERT(dispatcher->func == NULL); 201 202 s = _intr_suspend(); 203 dispatcher->func = func; 204 dispatcher->arg = arg; 205 dispatcher->ipl = ipl; 206 dispatcher->channel = ch; 207 dispatcher->bit = D_STAT_CIS_BIT(ch); 208 209 for (i = 0; i < _IPL_N; i++) { 210 if (i < ipl) 211 __dmac_ipl_holder[i].mask &= ~D_STAT_CIM_BIT(ch); 212 else 213 __dmac_ipl_holder[i].mask |= D_STAT_CIM_BIT(ch); 214 } 215 216 /* insert queue IPL order */ 217 if (SLIST_EMPTY(&__dmac_dispatcher_head)) { 218 SLIST_INSERT_HEAD(&__dmac_dispatcher_head, dispatcher, link); 219 } else { 220 SLIST_FOREACH(d, &__dmac_dispatcher_head, link) { 221 if (SLIST_NEXT(d, link) == 0 || 222 SLIST_NEXT(d, link)->ipl < ipl) { 223 SLIST_INSERT_AFTER(d, dispatcher, link); 224 break; 225 } 226 } 227 } 228 229 md_ipl_register(IPL_DMAC, __dmac_ipl_holder); 230 231 dmac_intr_enable(ch); 232 __dmac_enabled_channel |= D_STAT_CIS_BIT(ch); 233 234 _intr_resume(s); 235 236 return ((void *)ch); 237 } 238 239 void 240 dmac_intr_disestablish(void *handle) 241 { 242 int ch = (int)(handle); 243 struct _ipl_dispatcher *dispatcher = &__dmac_dispatcher[ch]; 244 int i, s; 245 246 s = _intr_suspend(); 247 248 dmac_intr_disable(ch); 249 dispatcher->func = NULL; 250 251 SLIST_REMOVE(&__dmac_dispatcher_head, dispatcher, 252 _ipl_dispatcher, link); 253 254 for (i = 0; i < _IPL_N; i++) 255 __dmac_ipl_holder[i].mask |= D_STAT_CIM_BIT(ch); 256 257 md_ipl_register(IPL_DMAC, __dmac_ipl_holder); 258 __dmac_enabled_channel &= ~D_STAT_CIS_BIT(ch); 259 260 _intr_resume(s); 261 } 262 263 /* 264 * Start/Stop 265 */ 266 void 267 dmac_start_channel(enum dmac_channel ch) 268 { 269 bus_addr_t chcr = D_CHCR_REG(__dmac_channel_base[ch]); 270 u_int32_t r; 271 int s; 272 273 /* suspend all channels */ 274 s = _intr_suspend(); 275 r = _reg_read_4(D_ENABLER_REG); 276 _reg_write_4(D_ENABLEW_REG, r | D_ENABLE_SUSPEND); 277 278 /* access CHCR */ 279 _reg_write_4(chcr, (_reg_read_4(chcr) | D_CHCR_STR)); 280 281 /* start all channels */ 282 _reg_write_4(D_ENABLEW_REG, r & ~D_ENABLE_SUSPEND); 283 _intr_resume(s); 284 } 285 286 void 287 dmac_stop_channel(enum dmac_channel ch) 288 { 289 bus_addr_t chcr = D_CHCR_REG(__dmac_channel_base[ch]); 290 u_int32_t r; 291 int s; 292 293 /* suspend all channels */ 294 s = _intr_suspend(); 295 r = _reg_read_4(D_ENABLER_REG); 296 _reg_write_4(D_ENABLEW_REG, r | D_ENABLE_SUSPEND); 297 298 /* access CHCR */ 299 _reg_write_4(chcr, (_reg_read_4(chcr) & ~D_CHCR_STR)); 300 301 /* resume all chanells */ 302 _reg_write_4(D_ENABLEW_REG, r); 303 _intr_resume(s); 304 } 305 306 void 307 dmac_sync_buffer() 308 { 309 extern void r5900_FlushCache(void); 310 311 r5900_FlushCache(); 312 __asm__ __volatile("sync.l"); 313 } 314 315 /* 316 * Polling 317 * DMAC status connected to CPCOND[0]. 318 */ 319 void 320 dmac_cpc_set(enum dmac_channel ch) 321 { 322 u_int32_t r; 323 324 r = _reg_read_4(D_PCR_REG); 325 KDASSERT((D_PCR_CPC(r) & ~D_PCR_CPC_BIT(ch)) == 0); 326 327 /* clear interrupt status */ 328 _reg_write_4(D_STAT_REG, D_STAT_CIS_BIT(ch)); 329 330 _reg_write_4(D_PCR_REG, r | D_PCR_CPC_BIT(ch)); 331 } 332 333 void 334 dmac_cpc_clear(enum dmac_channel ch) 335 { 336 337 _reg_write_4(D_PCR_REG, _reg_read_4(D_PCR_REG) & ~D_PCR_CPC_BIT(ch)) 338 } 339 340 void 341 dmac_cpc_poll() 342 { 343 __asm__ __volatile__( 344 ".set noreorder;" 345 "1: nop;" 346 "nop;" 347 "nop;" 348 "nop;" 349 "nop;" 350 "bc0f 1b;" 351 " nop;" 352 ".set reorder"); 353 } 354 355 /* not recommended. use dmac_cpc_poll as possible */ 356 void 357 dmac_bus_poll(enum dmac_channel ch) 358 { 359 bus_addr_t chcr = D_CHCR_REG(__dmac_channel_base[ch]); 360 361 while (_reg_read_4(chcr) & D_CHCR_STR) 362 ; 363 } 364 365 /* 366 * Misc 367 */ 368 void 369 dmac_chcr_write(enum dmac_channel ch, u_int32_t v) 370 { 371 u_int32_t r; 372 int s; 373 374 /* suspend all channels */ 375 s = _intr_suspend(); 376 r = _reg_read_4(D_ENABLER_REG); 377 _reg_write_4(D_ENABLEW_REG, r | D_ENABLE_SUSPEND); 378 379 /* write CHCR reg */ 380 _reg_write_4(D_CHCR_REG(__dmac_channel_base[ch]), v); 381 382 /* resume all chanells */ 383 _reg_write_4(D_ENABLEW_REG, r); 384 _intr_resume(s); 385 } 386 387
Indexes created Tue Sep 30 17:09:57 GMT 2025