dmac.c revision 1.3
1 /* $NetBSD: dmac.c,v 1.3 2003/07/15 02:54:36 lukem Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: dmac.c,v 1.3 2003/07/15 02:54:36 lukem Exp $"); 41 42 #include "debug_playstation2.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 47 #include <mips/cache.h> 48 49 #include <playstation2/ee/eevar.h> 50 #include <playstation2/ee/dmacvar.h> 51 #include <playstation2/ee/dmacreg.h> 52 #include <playstation2/ee/gsvar.h> /* debug monitor */ 53 54 #include <playstation2/playstation2/interrupt.h> 55 56 #ifdef DEBUG 57 #define LEGAL_CHANNEL(x) ((x) >= 0 && (x) <= 15) 58 #define STATIC 59 #else 60 #define STATIC static 61 #endif 62 63 #define _DMAC_NINTR 10 64 65 STATIC vaddr_t __dmac_channel_base[_DMAC_NINTR] = { 66 D0_REGBASE, 67 D1_REGBASE, 68 D2_REGBASE, 69 D3_REGBASE, 70 D4_REGBASE, 71 D5_REGBASE, 72 D6_REGBASE, 73 D7_REGBASE, 74 D8_REGBASE, 75 D9_REGBASE 76 }; 77 78 u_int32_t __dmac_enabled_channel; 79 80 STATIC int __dmac_intialized; 81 STATIC struct _ipl_dispatcher __dmac_dispatcher[_DMAC_NINTR]; 82 STATIC struct _ipl_holder __dmac_ipl_holder[_IPL_N]; 83 STATIC SLIST_HEAD(, _ipl_dispatcher) __dmac_dispatcher_head = 84 SLIST_HEAD_INITIALIZER(__dmac_dispatcher_head); 85 86 void 87 dmac_init() 88 { 89 int i; 90 91 if (__dmac_intialized++) 92 return; 93 94 /* disable DMAC */ 95 _reg_write_4(D_ENABLEW_REG, D_ENABLE_SUSPEND); 96 97 /* disable all interrupt */ 98 for (i = 0; i < _DMAC_NINTR; i++) 99 dmac_intr_disable(i); 100 101 for (i = 0; i < _IPL_N; i++) 102 __dmac_ipl_holder[i].mask = 0xffffffff; 103 104 if (_reg_read_4(D_STAT_REG) & D_STAT_SIM) 105 _reg_write_4(D_STAT_REG, D_STAT_SIM); 106 if (_reg_read_4(D_STAT_REG) & D_STAT_MEIM) 107 _reg_write_4(D_STAT_REG, D_STAT_MEIM); 108 109 /* clear all status */ 110 _reg_write_4(D_STAT_REG, _reg_read_4(D_STAT_REG) & D_STAT_CIS_MASK); 111 112 /* enable DMAC */ 113 _reg_write_4(D_ENABLEW_REG, 0); 114 _reg_write_4(D_CTRL_REG, D_CTRL_DMAE); 115 } 116 117 /* 118 * Interrupt 119 */ 120 int 121 dmac_intr(u_int32_t mask) 122 { 123 struct _ipl_dispatcher *dispatcher; 124 u_int32_t r, dispatch, pending; 125 126 r = _reg_read_4(D_STAT_REG); 127 mask = D_STAT_CIM(mask); 128 dispatch = r & ~mask & __dmac_enabled_channel; 129 pending = r & mask & __dmac_enabled_channel; 130 #if 0 131 __gsfb_print(2, 132 "DMAC stat=%08x, mask=%08x, pend=%08x, disp=%08x enable=%08x\n", 133 r, mask, pending, dispatch, __dmac_enabled_channel); 134 #endif 135 if (dispatch == 0) 136 return (pending == 0 ? 1 : 0); 137 138 /* clear interrupt */ 139 _reg_write_4(D_STAT_REG, dispatch); 140 141 /* dispatch interrupt handler */ 142 SLIST_FOREACH(dispatcher, &__dmac_dispatcher_head, link) { 143 if (dispatcher->bit & dispatch) { 144 KDASSERT(dispatcher->func); 145 (*dispatcher->func)(dispatcher->arg); 146 dispatch &= ~dispatcher->bit; 147 } 148 } 149 150 /* disable spurious interrupt source */ 151 if (dispatch) { 152 int i, bit; 153 for (i = 0, bit = 1; i < _DMAC_NINTR; i++, bit <<= 1) { 154 if (bit & dispatch) { 155 dmac_intr_disable(i); 156 printf("%s: spurious interrupt %d disabled.\n", 157 __FUNCTION__, i); 158 } 159 } 160 } 161 162 163 return (pending == 0 ? 1 : 0); 164 } 165 166 void 167 dmac_intr_enable(enum dmac_channel ch) 168 { 169 u_int32_t mask; 170 171 KDASSERT(LEGAL_CHANNEL(ch)); 172 173 mask = D_STAT_CIM_BIT(ch); 174 _reg_write_4(D_STAT_REG, (_reg_read_4(D_STAT_REG) & mask) ^ mask); 175 } 176 177 void 178 dmac_intr_disable(enum dmac_channel ch) 179 { 180 KDASSERT(LEGAL_CHANNEL(ch)); 181 182 _reg_write_4(D_STAT_REG, _reg_read_4(D_STAT_REG) & D_STAT_CIM_BIT(ch)); 183 } 184 185 void 186 dmac_update_mask(u_int32_t mask) 187 { 188 u_int32_t cur_mask; 189 190 mask = D_STAT_CIM(mask); 191 cur_mask = _reg_read_4(D_STAT_REG); 192 193 _reg_write_4(D_STAT_REG, ((cur_mask ^ ~mask) | (cur_mask & mask)) & 194 D_STAT_CIM(__dmac_enabled_channel)); 195 } 196 197 void * 198 dmac_intr_establish(enum dmac_channel ch, int ipl, int (*func)(void *), 199 void *arg) 200 { 201 struct _ipl_dispatcher *dispatcher = &__dmac_dispatcher[ch]; 202 struct _ipl_dispatcher *d; 203 int i, s; 204 205 KDASSERT(dispatcher->func == NULL); 206 207 s = _intr_suspend(); 208 dispatcher->func = func; 209 dispatcher->arg = arg; 210 dispatcher->ipl = ipl; 211 dispatcher->channel = ch; 212 dispatcher->bit = D_STAT_CIS_BIT(ch); 213 214 for (i = 0; i < _IPL_N; i++) { 215 if (i < ipl) 216 __dmac_ipl_holder[i].mask &= ~D_STAT_CIM_BIT(ch); 217 else 218 __dmac_ipl_holder[i].mask |= D_STAT_CIM_BIT(ch); 219 } 220 221 /* insert queue IPL order */ 222 if (SLIST_EMPTY(&__dmac_dispatcher_head)) { 223 SLIST_INSERT_HEAD(&__dmac_dispatcher_head, dispatcher, link); 224 } else { 225 SLIST_FOREACH(d, &__dmac_dispatcher_head, link) { 226 if (SLIST_NEXT(d, link) == 0 || 227 SLIST_NEXT(d, link)->ipl < ipl) { 228 SLIST_INSERT_AFTER(d, dispatcher, link); 229 break; 230 } 231 } 232 } 233 234 md_ipl_register(IPL_DMAC, __dmac_ipl_holder); 235 236 dmac_intr_enable(ch); 237 __dmac_enabled_channel |= D_STAT_CIS_BIT(ch); 238 239 _intr_resume(s); 240 241 return ((void *)ch); 242 } 243 244 void 245 dmac_intr_disestablish(void *handle) 246 { 247 int ch = (int)(handle); 248 struct _ipl_dispatcher *dispatcher = &__dmac_dispatcher[ch]; 249 int i, s; 250 251 s = _intr_suspend(); 252 253 dmac_intr_disable(ch); 254 dispatcher->func = NULL; 255 256 SLIST_REMOVE(&__dmac_dispatcher_head, dispatcher, 257 _ipl_dispatcher, link); 258 259 for (i = 0; i < _IPL_N; i++) 260 __dmac_ipl_holder[i].mask |= D_STAT_CIM_BIT(ch); 261 262 md_ipl_register(IPL_DMAC, __dmac_ipl_holder); 263 __dmac_enabled_channel &= ~D_STAT_CIS_BIT(ch); 264 265 _intr_resume(s); 266 } 267 268 /* 269 * Start/Stop 270 */ 271 void 272 dmac_start_channel(enum dmac_channel ch) 273 { 274 bus_addr_t chcr = D_CHCR_REG(__dmac_channel_base[ch]); 275 u_int32_t r; 276 int s; 277 278 /* suspend all channels */ 279 s = _intr_suspend(); 280 r = _reg_read_4(D_ENABLER_REG); 281 _reg_write_4(D_ENABLEW_REG, r | D_ENABLE_SUSPEND); 282 283 /* access CHCR */ 284 _reg_write_4(chcr, (_reg_read_4(chcr) | D_CHCR_STR)); 285 286 /* start all channels */ 287 _reg_write_4(D_ENABLEW_REG, r & ~D_ENABLE_SUSPEND); 288 _intr_resume(s); 289 } 290 291 void 292 dmac_stop_channel(enum dmac_channel ch) 293 { 294 bus_addr_t chcr = D_CHCR_REG(__dmac_channel_base[ch]); 295 u_int32_t r; 296 int s; 297 298 /* suspend all channels */ 299 s = _intr_suspend(); 300 r = _reg_read_4(D_ENABLER_REG); 301 _reg_write_4(D_ENABLEW_REG, r | D_ENABLE_SUSPEND); 302 303 /* access CHCR */ 304 _reg_write_4(chcr, (_reg_read_4(chcr) & ~D_CHCR_STR)); 305 306 /* resume all chanells */ 307 _reg_write_4(D_ENABLEW_REG, r); 308 _intr_resume(s); 309 } 310 311 void 312 dmac_sync_buffer() 313 { 314 315 mips_dcache_wbinv_all(); 316 __asm__ __volatile("sync.l"); 317 } 318 319 /* 320 * Polling 321 * DMAC status connected to CPCOND[0]. 322 */ 323 void 324 dmac_cpc_set(enum dmac_channel ch) 325 { 326 u_int32_t r; 327 328 r = _reg_read_4(D_PCR_REG); 329 KDASSERT((D_PCR_CPC(r) & ~D_PCR_CPC_BIT(ch)) == 0); 330 331 /* clear interrupt status */ 332 _reg_write_4(D_STAT_REG, D_STAT_CIS_BIT(ch)); 333 334 _reg_write_4(D_PCR_REG, r | D_PCR_CPC_BIT(ch)); 335 } 336 337 void 338 dmac_cpc_clear(enum dmac_channel ch) 339 { 340 341 _reg_write_4(D_PCR_REG, _reg_read_4(D_PCR_REG) & ~D_PCR_CPC_BIT(ch)) 342 } 343 344 void 345 dmac_cpc_poll() 346 { 347 __asm__ __volatile__( 348 ".set noreorder;" 349 "1: nop;" 350 "nop;" 351 "nop;" 352 "nop;" 353 "nop;" 354 "bc0f 1b;" 355 " nop;" 356 ".set reorder"); 357 } 358 359 /* not recommended. use dmac_cpc_poll as possible */ 360 void 361 dmac_bus_poll(enum dmac_channel ch) 362 { 363 bus_addr_t chcr = D_CHCR_REG(__dmac_channel_base[ch]); 364 365 while (_reg_read_4(chcr) & D_CHCR_STR) 366 ; 367 } 368 369 /* 370 * Misc 371 */ 372 void 373 dmac_chcr_write(enum dmac_channel ch, u_int32_t v) 374 { 375 u_int32_t r; 376 int s; 377 378 /* suspend all channels */ 379 s = _intr_suspend(); 380 r = _reg_read_4(D_ENABLER_REG); 381 _reg_write_4(D_ENABLEW_REG, r | D_ENABLE_SUSPEND); 382 383 /* write CHCR reg */ 384 _reg_write_4(D_CHCR_REG(__dmac_channel_base[ch]), v); 385 386 /* resume all chanells */ 387 _reg_write_4(D_ENABLEW_REG, r); 388 _intr_resume(s); 389 } 390 391
Indexes created Tue Sep 30 11:09:46 GMT 2025