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gs.c revision 1.1
      1  1.1  uch /*	$NetBSD: gs.c,v 1.1 2001/10/16 15:38:37 uch Exp $	*/
      2  1.1  uch 
      3  1.1  uch /*-
      4  1.1  uch  * Copyright (c) 2001 The NetBSD Foundation, Inc.
      5  1.1  uch  * All rights reserved.
      6  1.1  uch  *
      7  1.1  uch  * This code is derived from software contributed to The NetBSD Foundation
      8  1.1  uch  * by UCHIYAMA Yasushi.
      9  1.1  uch  *
     10  1.1  uch  * Redistribution and use in source and binary forms, with or without
     11  1.1  uch  * modification, are permitted provided that the following conditions
     12  1.1  uch  * are met:
     13  1.1  uch  * 1. Redistributions of source code must retain the above copyright
     14  1.1  uch  *    notice, this list of conditions and the following disclaimer.
     15  1.1  uch  * 2. Redistributions in binary form must reproduce the above copyright
     16  1.1  uch  *    notice, this list of conditions and the following disclaimer in the
     17  1.1  uch  *    documentation and/or other materials provided with the distribution.
     18  1.1  uch  * 3. All advertising materials mentioning features or use of this software
     19  1.1  uch  *    must display the following acknowledgement:
     20  1.1  uch  *        This product includes software developed by the NetBSD
     21  1.1  uch  *        Foundation, Inc. and its contributors.
     22  1.1  uch  * 4. Neither the name of The NetBSD Foundation nor the names of its
     23  1.1  uch  *    contributors may be used to endorse or promote products derived
     24  1.1  uch  *    from this software without specific prior written permission.
     25  1.1  uch  *
     26  1.1  uch  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     27  1.1  uch  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     28  1.1  uch  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     29  1.1  uch  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     30  1.1  uch  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     31  1.1  uch  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     32  1.1  uch  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     33  1.1  uch  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     34  1.1  uch  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     35  1.1  uch  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     36  1.1  uch  * POSSIBILITY OF SUCH DAMAGE.
     37  1.1  uch  */
     38  1.1  uch 
     39  1.1  uch #include <sys/param.h>
     40  1.1  uch 
     41  1.1  uch #include <playstation2/playstation2/sifbios.h>
     42  1.1  uch #include <playstation2/ee/eevar.h>
     43  1.1  uch #include <playstation2/ee/gsvar.h>
     44  1.1  uch #include <playstation2/ee/gsreg.h>
     45  1.1  uch #include <playstation2/ee/gifreg.h>
     46  1.1  uch 
     47  1.1  uch #ifdef DEBUG
     48  1.1  uch #define STATIC
     49  1.1  uch #else
     50  1.1  uch #define STATIC	static
     51  1.1  uch #endif
     52  1.1  uch 
     53  1.1  uch STATIC const struct gs_crt_param {
     54  1.1  uch 	int w, h, dvemode;
     55  1.1  uch 	u_int64_t smode1, smode2, srfsh, synch1, synch2, syncv, display;
     56  1.1  uch } gs_crt_param[] = {
     57  1.1  uch 	[NTSC_NONINTER] = {
     58  1.1  uch 		.w	= 640,
     59  1.1  uch 		.h	= 240,
     60  1.1  uch 		.dvemode= 0,
     61  1.1  uch 		.smode1	= SMODE1(0, 1, 1, 1, 1, 0, 0, 0, 0, 0,
     62  1.1  uch 		    4, 0, 0, 1, 1, 0, 2, 0, 1, 32, 4),
     63  1.1  uch 		.smode2 = SMODE2(0, 0, 0),
     64  1.1  uch 		.srfsh	= SRFSH(8),
     65  1.1  uch 		.synch1	= SYNCH1(254, 1462, 124, 222, 64),
     66  1.1  uch 		.synch2	= SYNCH2(1652, 1240),
     67  1.1  uch 		.syncv	= SYNCV(6, 480, 6, 26, 6, 2),
     68  1.1  uch 		.display=DISPLAY(239, 2559, 0, 3, 25, 632)
     69  1.1  uch 	},
     70  1.1  uch 	[NTSC_INTER] = {
     71  1.1  uch 		.w	= 640,
     72  1.1  uch 		.h	= 480,
     73  1.1  uch 		.dvemode= 0,
     74  1.1  uch 		.smode1	= SMODE1(0, 1, 1, 1, 1, 0, 0, 0, 0, 0,
     75  1.1  uch 		    4, 0, 0, 1, 1, 0, 2, 0, 1, 32, 4),
     76  1.1  uch 		.smode2	= SMODE2(0, 0, 1),
     77  1.1  uch 		.srfsh	= SRFSH(8),
     78  1.1  uch 		.synch1	= SYNCH1(254, 1462, 124, 222, 64),
     79  1.1  uch 		.synch2	= SYNCH2(1652, 1240),
     80  1.1  uch 		.syncv	= SYNCV(6, 480, 6, 26, 6, 1),
     81  1.1  uch 		.display= DISPLAY(479, 2559, 0, 3, 50, 632)
     82  1.1  uch 	},
     83  1.1  uch 	[PAL_NONINTER] = {
     84  1.1  uch 		.w	= 640,
     85  1.1  uch 		.h	= 288,
     86  1.1  uch 		.dvemode= 1,
     87  1.1  uch 		.smode1	= SMODE1(0, 1, 1, 1, 1, 0, 0, 0, 0, 0,
     88  1.1  uch 		    4, 0, 0, 1, 1, 0, 3, 0, 1, 32, 4),
     89  1.1  uch 		.smode2	= SMODE2(0, 0, 0),
     90  1.1  uch 		.srfsh	= SRFSH(8),
     91  1.1  uch 		.synch1	= SYNCH1(254, 1474, 127, 262, 48),
     92  1.1  uch 		.synch2	= SYNCH2(1680, 1212),
     93  1.1  uch 		.syncv	= SYNCV(5, 576, 5, 33, 5, 4),
     94  1.1  uch 		.display= DISPLAY(287, 2559, 0, 3, 36, 652)
     95  1.1  uch 	},
     96  1.1  uch 	[PAL_INTER] = {
     97  1.1  uch 		.w	= 640,
     98  1.1  uch 		.h	= 576,
     99  1.1  uch 		.dvemode= 1,
    100  1.1  uch 		.smode1	= SMODE1(0, 1, 1, 1, 1, 0, 0, 0, 0, 0,
    101  1.1  uch 		    4, 0, 0, 1, 1, 0, 3, 0, 1, 32, 4),
    102  1.1  uch 		.smode2	= SMODE2(0, 0, 1),
    103  1.1  uch 		.srfsh	= SRFSH(8),
    104  1.1  uch 		.synch1	= SYNCH1(254, 1474, 127, 262, 48),
    105  1.1  uch 		.synch2	= SYNCH2(1680, 1212),
    106  1.1  uch 		.syncv	= SYNCV(5, 576, 5, 33, 5, 4),
    107  1.1  uch 		.display= DISPLAY(575,2559,0,3,72,652)
    108  1.1  uch 	},
    109  1.1  uch 	[VESA_1A] = {
    110  1.1  uch 		.w	= 640,
    111  1.1  uch 		.h	= 480,
    112  1.1  uch 		.dvemode= 2,
    113  1.1  uch 		.smode1	= SMODE1(1, 0, 1, 1, 1, 0, 0, 0, 0, 0,
    114  1.1  uch 		    2, 0, 0, 1, 0, 0, 0, 0, 1, 15, 2),
    115  1.1  uch 		.smode2	= SMODE2(0, 0, 0),
    116  1.1  uch 		.srfsh	= SRFSH(4),
    117  1.1  uch 		.synch1	= SYNCH1(192, 608, 192, 84, 32),
    118  1.1  uch 		.synch2	= SYNCH2(768, 524),
    119  1.1  uch 		.syncv	= SYNCV(2, 480, 0, 33, 0, 10),
    120  1.1  uch 		.display= DISPLAY(479, 1279, 0, 1, 34, 276)
    121  1.1  uch 	}
    122  1.1  uch };
    123  1.1  uch 
    124  1.1  uch void
    125  1.1  uch gs_init(enum gs_crt_type type)
    126  1.1  uch {
    127  1.1  uch 	const struct gs_crt_param *p = &gs_crt_param[type];
    128  1.1  uch 	u_int64_t smode1 = p->smode1;
    129  1.1  uch 
    130  1.1  uch 	/* GS reset */
    131  1.1  uch 	_reg_write_8(GS_S_CSR_REG, 1 << 9);
    132  1.1  uch 
    133  1.1  uch 	/* setup PCRTC */
    134  1.1  uch 	_reg_write_8(GS_S_PMODE_REG, 0); /* disable circuit 1/2 */
    135  1.1  uch 
    136  1.1  uch 	_reg_write_8(GS_S_SMODE1_REG, smode1 | ((u_int64_t)1 << 16));
    137  1.1  uch 	_reg_write_8(GS_S_SYNCH1_REG, p->synch1);
    138  1.1  uch 	_reg_write_8(GS_S_SYNCH2_REG, p->synch2);
    139  1.1  uch 	_reg_write_8(GS_S_SYNCV_REG, p->syncv);
    140  1.1  uch 	_reg_write_8(GS_S_SMODE2_REG, p->smode2);
    141  1.1  uch 	_reg_write_8(GS_S_SRFSH_REG, p->srfsh);
    142  1.1  uch 
    143  1.1  uch 	if (p->dvemode == 2) { /* PLL on */
    144  1.1  uch 		_reg_write_8(GS_S_SMODE1_REG, smode1 & ~((u_int64_t)1 << 16));
    145  1.1  uch 		delay(2500);
    146  1.1  uch 	}
    147  1.1  uch 
    148  1.1  uch 	/* start sync */
    149  1.1  uch 	_reg_write_8(GS_S_SMODE1_REG,
    150  1.1  uch 	    smode1 & ~((u_int64_t)1 << 16) & ~((u_int64_t)1 << 17));
    151  1.1  uch 
    152  1.1  uch 	sifbios_setdve(p->dvemode);
    153  1.1  uch 
    154  1.1  uch 	/* enable circuit */
    155  1.1  uch 	_reg_write_8(GS_S_PMODE_REG, 0x66);
    156  1.1  uch 
    157  1.1  uch 	/* display environment */
    158  1.1  uch 	_reg_write_8(GS_S_DISPLAY2_REG, p->display);
    159  1.1  uch 	_reg_write_8(GS_S_DISPFB2_REG, (p->w >> 6) << 9);
    160  1.1  uch 	_reg_write_8(GS_S_SMODE2_REG, p->smode2);
    161  1.1  uch 	_reg_write_8(GS_S_BGCOLOR_REG, 0);
    162  1.1  uch 
    163  1.1  uch 	/* Flush GS FIFO */
    164  1.1  uch 	_reg_write_8(GS_S_CSR_REG, 1 << 8);
    165  1.1  uch 
    166  1.1  uch 	/* GIF reset */
    167  1.1  uch 	_reg_write_4(GIF_CTRL_REG, 1);
    168  1.1  uch }
    169