timerreg.h revision 1.5
1 /* $NetBSD: timerreg.h,v 1.5 2006/03/08 23:46:24 lukem Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * 16bit timer 0:3 41 * source: BUSCLK, H-BLNK 42 */ 43 44 #define EE_TIMER_MIN 0 45 #define EE_TIMER_MAX 3 46 #define LEGAL_TIMER(x) \ 47 (((x) >= EE_TIMER_MIN) && ((x) <= EE_TIMER_MAX)) 48 49 /* Register address. all registers are 32bit wide */ 50 #define TIMER_REGBASE 0x10000000 51 #define TIMER_REGSIZE 0x2000 52 #define TIMER_OFS 0x800 53 54 #define T_COUNT_REG(x) MIPS_PHYS_TO_KSEG1((TIMER_REGBASE + TIMER_OFS * (x))) 55 #define T_MODE_REG(x) MIPS_PHYS_TO_KSEG1((TIMER_REGBASE + \ 56 TIMER_OFS * (x) + 0x10)) 57 #define T_COMP_REG(x) MIPS_PHYS_TO_KSEG1((TIMER_REGBASE + \ 58 TIMER_OFS * (x) + 0x20)) 59 /* 60 * timer0, timer1 have `hold register'. 61 * (save T_COUNT when SBUS interrupt occurred) 62 */ 63 #define T_HOLD_REG(x) (TIMER_REGBASE + TIMER_OFS * (x) + 0x30) 64 65 #define T0_COUNT_REG MIPS_PHYS_TO_KSEG1(0x10000000) 66 #define T0_MODE_REG MIPS_PHYS_TO_KSEG1(0x10000010) 67 #define T0_COMP_REG MIPS_PHYS_TO_KSEG1(0x10000020) 68 #define T0_HOLD_REG MIPS_PHYS_TO_KSEG1(0x10000030) 69 #define T1_COUNT_REG MIPS_PHYS_TO_KSEG1(0x10000800) 70 #define T1_MODE_REG MIPS_PHYS_TO_KSEG1(0x10000810) 71 #define T1_COMP_REG MIPS_PHYS_TO_KSEG1(0x10000820) 72 #define T1_HOLD_REG MIPS_PHYS_TO_KSEG1(0x10000830) 73 #define T2_COUNT_REG MIPS_PHYS_TO_KSEG1(0x10001000) 74 #define T2_MODE_REG MIPS_PHYS_TO_KSEG1(0x10001010) 75 #define T2_COMP_REG MIPS_PHYS_TO_KSEG1(0x10001020) 76 #define T3_COUNT_REG MIPS_PHYS_TO_KSEG1(0x10001800) 77 #define T3_MODE_REG MIPS_PHYS_TO_KSEG1(0x10001810) 78 #define T3_COMP_REG MIPS_PHYS_TO_KSEG1(0x10001820) 79 80 /* 81 * Tn_MODE: mode, status register. 82 */ 83 #define T_MODE_CLKS_MASK 0x3 84 #define T_MODE_CLKS(x) ((x) & T_MODE_CLKS_MASK) 85 #define T_MODE_CLKS_CLR(x) ((x) & ~T_MODE_CLKS_MASK) 86 87 #define T_MODE_CLKS_BUSCLK1 0 /* 150 MHz */ 88 #define T_MODE_CLKS_BUSCLK16 1 /* 150 / 16 */ 89 #define T_MODE_CLKS_BUSCLK256 2 /* 150 / 256 */ 90 #define T_MODE_CLKS_HBLNK 3 /* H-Blank */ 91 92 /* Gate Function Enabled */ 93 #define T_MODE_GATE 0x00000004 94 /* Gate Selection */ 95 #define T_MODE_GATS_VBLNK 0x00000008 96 /* Gate Mode */ 97 #define T_MODE_GATM_MASK 0x3 98 #define T_MODE_GATM_SHIFT 4 99 #define T_MODE_GATM(x) (((x) >> T_MODE_GATM_SHIFT) & T_MODE_GATM_MASK) 100 #define T_MODE_GATM_CLR(x) \ 101 ((x) & ~(T_MODE_GATM_MASK << T_MODE_GATM_SHIFT)) 102 #define T_MODE_GATM_SET(x, val) \ 103 ((x) | (((val) << T_MODE_GATM_SHIFT) & \ 104 (T_MODE_GATM_MASK << T_MODE_GATM_SHIFT))) 105 #define T_MODE_GATM_LOW 0x0 106 #define T_MODE_GATM_POSEDGE 0x1 107 #define T_MODE_GATM_NEGEDGE 0x2 108 #define T_MODE_GATM_EDGE 0x3 109 110 /* Zero Return */ 111 #define T_MODE_ZRET 0x00000040 112 /* Count Up Enable */ 113 #define T_MODE_CUE 0x00000080 114 /* Compare-Interrupt Enable */ 115 #define T_MODE_CMPE 0x00000100 116 /* Overflow-Interrupt Enable */ 117 #define T_MODE_OVFE 0x00000200 118 /* Equal Flag (write clear) */ 119 #define T_MODE_EQUF 0x00000400 120 /* Overflow Flag (write clear) */ 121 #define T_MODE_OVFF 0x00000800 122 123 /* 124 * Tn_COUNT: counter register 125 */ 126 #define T_COUNT_MASK 0x0000ffff 127 #define T_COUNT(x) ((x) & T_COUNT_MASK) 128 129 /* 130 * Tn_COMP: compare register 131 */ 132 #define T_COMP_MASK 0x0000ffff 133 #define T_COMP(x) ((x) & T_COMP_MASK) 134 135 /* 136 * Tn_HOLD: hold register 137 */ 138 #define T_HOLD_MASK 0x0000ffff 139 #define T_HOLD(x) ((x) & T_HOLD_MASK) 140
Indexes created Wed Oct 01 19:09:53 GMT 2025