bus.h revision 1.15.4.2
1 1.15.4.2 tls /* $NetBSD: bus.h,v 1.15.4.2 2014/08/20 00:03:18 tls Exp $ */ 2 1.15.4.2 tls 3 1.15.4.2 tls /*- 4 1.15.4.2 tls * Copyright (c) 1997, 1998, 2000, 2001 The NetBSD Foundation, Inc. 5 1.15.4.2 tls * All rights reserved. 6 1.15.4.2 tls * 7 1.15.4.2 tls * This code is derived from software contributed to The NetBSD Foundation 8 1.15.4.2 tls * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 1.15.4.2 tls * NASA Ames Research Center. 10 1.15.4.2 tls * 11 1.15.4.2 tls * Redistribution and use in source and binary forms, with or without 12 1.15.4.2 tls * modification, are permitted provided that the following conditions 13 1.15.4.2 tls * are met: 14 1.15.4.2 tls * 1. Redistributions of source code must retain the above copyright 15 1.15.4.2 tls * notice, this list of conditions and the following disclaimer. 16 1.15.4.2 tls * 2. Redistributions in binary form must reproduce the above copyright 17 1.15.4.2 tls * notice, this list of conditions and the following disclaimer in the 18 1.15.4.2 tls * documentation and/or other materials provided with the distribution. 19 1.15.4.2 tls * 20 1.15.4.2 tls * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 1.15.4.2 tls * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 1.15.4.2 tls * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 1.15.4.2 tls * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 1.15.4.2 tls * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 1.15.4.2 tls * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 1.15.4.2 tls * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 1.15.4.2 tls * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 1.15.4.2 tls * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 1.15.4.2 tls * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 1.15.4.2 tls * POSSIBILITY OF SUCH DAMAGE. 31 1.15.4.2 tls */ 32 1.15.4.2 tls 33 1.15.4.2 tls /* 34 1.15.4.2 tls * Copyright (c) 1996 Carnegie-Mellon University. 35 1.15.4.2 tls * All rights reserved. 36 1.15.4.2 tls * 37 1.15.4.2 tls * Author: Chris G. Demetriou 38 1.15.4.2 tls * 39 1.15.4.2 tls * Permission to use, copy, modify and distribute this software and 40 1.15.4.2 tls * its documentation is hereby granted, provided that both the copyright 41 1.15.4.2 tls * notice and this permission notice appear in all copies of the 42 1.15.4.2 tls * software, derivative works or modified versions, and any portions 43 1.15.4.2 tls * thereof, and that both notices appear in supporting documentation. 44 1.15.4.2 tls * 45 1.15.4.2 tls * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 46 1.15.4.2 tls * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 47 1.15.4.2 tls * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 48 1.15.4.2 tls * 49 1.15.4.2 tls * Carnegie Mellon requests users of this software to return to 50 1.15.4.2 tls * 51 1.15.4.2 tls * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 52 1.15.4.2 tls * School of Computer Science 53 1.15.4.2 tls * Carnegie Mellon University 54 1.15.4.2 tls * Pittsburgh PA 15213-3890 55 1.15.4.2 tls * 56 1.15.4.2 tls * any improvements or extensions that they make and grant Carnegie the 57 1.15.4.2 tls * rights to redistribute these changes. 58 1.15.4.2 tls */ 59 1.15.4.2 tls 60 1.15.4.2 tls #ifndef _PLAYSTATION2_BUS_H_ 61 1.15.4.2 tls #define _PLAYSTATION2_BUS_H_ 62 1.15.4.2 tls 63 1.15.4.2 tls #include <sys/types.h> 64 1.15.4.2 tls 65 1.15.4.2 tls #ifdef _KERNEL 66 1.15.4.2 tls /* 67 1.15.4.2 tls * Turn on BUS_SPACE_DEBUG if the global DEBUG option is enabled. 68 1.15.4.2 tls */ 69 1.15.4.2 tls #if defined(DEBUG) && !defined(BUS_SPACE_DEBUG) 70 1.15.4.2 tls #define BUS_SPACE_DEBUG 71 1.15.4.2 tls #endif 72 1.15.4.2 tls 73 1.15.4.2 tls #ifdef BUS_SPACE_DEBUG 74 1.15.4.2 tls #include <sys/systm.h> /* for printf() prototype */ 75 1.15.4.2 tls /* 76 1.15.4.2 tls * Macros for checking the aligned-ness of pointers passed to bus 77 1.15.4.2 tls * space ops. Strict alignment is required by the MIPS architecture, 78 1.15.4.2 tls * and a trap will occur if unaligned access is performed. These 79 1.15.4.2 tls * may aid in the debugging of a broken device driver by displaying 80 1.15.4.2 tls * useful information about the problem. 81 1.15.4.2 tls */ 82 1.15.4.2 tls #define __BUS_SPACE_ALIGNED_ADDRESS(p, t) \ 83 1.15.4.2 tls ((((u_int32_t)(p)) & (sizeof(t)-1)) == 0) 84 1.15.4.2 tls 85 1.15.4.2 tls #define __BUS_SPACE_ADDRESS_SANITY(p, t, d) \ 86 1.15.4.2 tls ({ \ 87 1.15.4.2 tls if (__BUS_SPACE_ALIGNED_ADDRESS((p), t) == 0) { \ 88 1.15.4.2 tls printf("%s 0x%x not aligned to %u bytes %s:%d\n", \ 89 1.15.4.2 tls d, (u_int32_t)(p), (u_int32_t)sizeof(t), __FILE__, \ 90 1.15.4.2 tls __LINE__); \ 91 1.15.4.2 tls } \ 92 1.15.4.2 tls (void) 0; \ 93 1.15.4.2 tls }) 94 1.15.4.2 tls 95 1.15.4.2 tls #define BUS_SPACE_ALIGNED_POINTER(p, t) __BUS_SPACE_ALIGNED_ADDRESS(p, t) 96 1.15.4.2 tls #else 97 1.15.4.2 tls #define __BUS_SPACE_ADDRESS_SANITY(p, t, d) (void) 0 98 1.15.4.2 tls #define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t) 99 1.15.4.2 tls #endif /* BUS_SPACE_DEBUG */ 100 1.15.4.2 tls #endif /* _KERNEL */ 101 1.15.4.2 tls 102 1.15.4.2 tls /* 103 1.15.4.2 tls * Addresses (in bus space). 104 1.15.4.2 tls */ 105 1.15.4.2 tls typedef long bus_addr_t; 106 1.15.4.2 tls typedef long bus_size_t; 107 1.15.4.2 tls 108 1.15.4.2 tls /* 109 1.15.4.2 tls * Access methods for bus space. 110 1.15.4.2 tls */ 111 1.15.4.2 tls typedef const struct playstation2_bus_space *bus_space_tag_t; 112 1.15.4.2 tls typedef bus_addr_t bus_space_handle_t; 113 1.15.4.2 tls 114 1.15.4.2 tls struct extent; /* forward declaration */ 115 1.15.4.2 tls 116 1.15.4.2 tls struct playstation2_bus_space { 117 1.15.4.2 tls struct extent *pbs_extent; 118 1.15.4.2 tls bus_addr_t pbs_base_addr; 119 1.15.4.2 tls 120 1.15.4.2 tls /* cookie */ 121 1.15.4.2 tls void *pbs_cookie; 122 1.15.4.2 tls 123 1.15.4.2 tls /* mapping/unmapping */ 124 1.15.4.2 tls int (*pbs_map)(void *, bus_addr_t, bus_size_t, 125 1.15.4.2 tls int, bus_space_handle_t *); 126 1.15.4.2 tls void (*pbs_unmap)(void *, bus_space_handle_t, 127 1.15.4.2 tls bus_size_t); 128 1.15.4.2 tls int (*pbs_subregion)(void *, bus_space_handle_t, 129 1.15.4.2 tls bus_size_t, bus_size_t, bus_space_handle_t *); 130 1.15.4.2 tls 131 1.15.4.2 tls /* allocation/deallocation */ 132 1.15.4.2 tls int (*pbs_alloc)(void *, bus_addr_t, bus_addr_t, 133 1.15.4.2 tls bus_size_t, bus_size_t, bus_size_t, int, 134 1.15.4.2 tls bus_addr_t *, bus_space_handle_t *); 135 1.15.4.2 tls void (*pbs_free)(void *, bus_space_handle_t, 136 1.15.4.2 tls bus_size_t); 137 1.15.4.2 tls 138 1.15.4.2 tls /* get kernel virtual address */ 139 1.15.4.2 tls void * (*pbs_vaddr)(void *, bus_space_handle_t); 140 1.15.4.2 tls 141 1.15.4.2 tls /* read (single) */ 142 1.15.4.2 tls u_int8_t (*pbs_r_1)(void *, bus_space_handle_t, 143 1.15.4.2 tls bus_size_t); 144 1.15.4.2 tls u_int16_t (*pbs_r_2)(void *, bus_space_handle_t, 145 1.15.4.2 tls bus_size_t); 146 1.15.4.2 tls u_int32_t (*pbs_r_4)(void *, bus_space_handle_t, 147 1.15.4.2 tls bus_size_t); 148 1.15.4.2 tls u_int64_t (*pbs_r_8)(void *, bus_space_handle_t, 149 1.15.4.2 tls bus_size_t); 150 1.15.4.2 tls 151 1.15.4.2 tls /* read multiple */ 152 1.15.4.2 tls void (*pbs_rm_1)(void *, bus_space_handle_t, 153 1.15.4.2 tls bus_size_t, u_int8_t *, bus_size_t); 154 1.15.4.2 tls void (*pbs_rm_2)(void *, bus_space_handle_t, 155 1.15.4.2 tls bus_size_t, u_int16_t *, bus_size_t); 156 1.15.4.2 tls void (*pbs_rm_4)(void *, bus_space_handle_t, 157 1.15.4.2 tls bus_size_t, u_int32_t *, bus_size_t); 158 1.15.4.2 tls void (*pbs_rm_8)(void *, bus_space_handle_t, 159 1.15.4.2 tls bus_size_t, u_int64_t *, bus_size_t); 160 1.15.4.2 tls 161 1.15.4.2 tls /* read region */ 162 1.15.4.2 tls void (*pbs_rr_1)(void *, bus_space_handle_t, 163 1.15.4.2 tls bus_size_t, u_int8_t *, bus_size_t); 164 1.15.4.2 tls void (*pbs_rr_2)(void *, bus_space_handle_t, 165 1.15.4.2 tls bus_size_t, u_int16_t *, bus_size_t); 166 1.15.4.2 tls void (*pbs_rr_4)(void *, bus_space_handle_t, 167 1.15.4.2 tls bus_size_t, u_int32_t *, bus_size_t); 168 1.15.4.2 tls void (*pbs_rr_8)(void *, bus_space_handle_t, 169 1.15.4.2 tls bus_size_t, u_int64_t *, bus_size_t); 170 1.15.4.2 tls 171 1.15.4.2 tls /* write (single) */ 172 1.15.4.2 tls void (*pbs_w_1)(void *, bus_space_handle_t, 173 1.15.4.2 tls bus_size_t, u_int8_t); 174 1.15.4.2 tls void (*pbs_w_2)(void *, bus_space_handle_t, 175 1.15.4.2 tls bus_size_t, u_int16_t); 176 1.15.4.2 tls void (*pbs_w_4)(void *, bus_space_handle_t, 177 1.15.4.2 tls bus_size_t, u_int32_t); 178 1.15.4.2 tls void (*pbs_w_8)(void *, bus_space_handle_t, 179 1.15.4.2 tls bus_size_t, u_int64_t); 180 1.15.4.2 tls 181 1.15.4.2 tls /* write multiple */ 182 1.15.4.2 tls void (*pbs_wm_1)(void *, bus_space_handle_t, 183 1.15.4.2 tls bus_size_t, const u_int8_t *, bus_size_t); 184 1.15.4.2 tls void (*pbs_wm_2)(void *, bus_space_handle_t, 185 1.15.4.2 tls bus_size_t, const u_int16_t *, bus_size_t); 186 1.15.4.2 tls void (*pbs_wm_4)(void *, bus_space_handle_t, 187 1.15.4.2 tls bus_size_t, const u_int32_t *, bus_size_t); 188 1.15.4.2 tls void (*pbs_wm_8)(void *, bus_space_handle_t, 189 1.15.4.2 tls bus_size_t, const u_int64_t *, bus_size_t); 190 1.15.4.2 tls 191 1.15.4.2 tls /* write region */ 192 1.15.4.2 tls void (*pbs_wr_1)(void *, bus_space_handle_t, 193 1.15.4.2 tls bus_size_t, const u_int8_t *, bus_size_t); 194 1.15.4.2 tls void (*pbs_wr_2)(void *, bus_space_handle_t, 195 1.15.4.2 tls bus_size_t, const u_int16_t *, bus_size_t); 196 1.15.4.2 tls void (*pbs_wr_4)(void *, bus_space_handle_t, 197 1.15.4.2 tls bus_size_t, const u_int32_t *, bus_size_t); 198 1.15.4.2 tls void (*pbs_wr_8)(void *, bus_space_handle_t, 199 1.15.4.2 tls bus_size_t, const u_int64_t *, bus_size_t); 200 1.15.4.2 tls 201 1.15.4.2 tls /* set multiple */ 202 1.15.4.2 tls void (*pbs_sm_1)(void *, bus_space_handle_t, 203 1.15.4.2 tls bus_size_t, u_int8_t, bus_size_t); 204 1.15.4.2 tls void (*pbs_sm_2)(void *, bus_space_handle_t, 205 1.15.4.2 tls bus_size_t, u_int16_t, bus_size_t); 206 1.15.4.2 tls void (*pbs_sm_4)(void *, bus_space_handle_t, 207 1.15.4.2 tls bus_size_t, u_int32_t, bus_size_t); 208 1.15.4.2 tls void (*pbs_sm_8)(void *, bus_space_handle_t, 209 1.15.4.2 tls bus_size_t, u_int64_t, bus_size_t); 210 1.15.4.2 tls 211 1.15.4.2 tls /* set region */ 212 1.15.4.2 tls void (*pbs_sr_1)(void *, bus_space_handle_t, 213 1.15.4.2 tls bus_size_t, u_int8_t, bus_size_t); 214 1.15.4.2 tls void (*pbs_sr_2)(void *, bus_space_handle_t, 215 1.15.4.2 tls bus_size_t, u_int16_t, bus_size_t); 216 1.15.4.2 tls void (*pbs_sr_4)(void *, bus_space_handle_t, 217 1.15.4.2 tls bus_size_t, u_int32_t, bus_size_t); 218 1.15.4.2 tls void (*pbs_sr_8)(void *, bus_space_handle_t, 219 1.15.4.2 tls bus_size_t, u_int64_t, bus_size_t); 220 1.15.4.2 tls 221 1.15.4.2 tls /* copy */ 222 1.15.4.2 tls void (*pbs_c_1)(void *, bus_space_handle_t, bus_size_t, 223 1.15.4.2 tls bus_space_handle_t, bus_size_t, bus_size_t); 224 1.15.4.2 tls void (*pbs_c_2)(void *, bus_space_handle_t, bus_size_t, 225 1.15.4.2 tls bus_space_handle_t, bus_size_t, bus_size_t); 226 1.15.4.2 tls void (*pbs_c_4)(void *, bus_space_handle_t, bus_size_t, 227 1.15.4.2 tls bus_space_handle_t, bus_size_t, bus_size_t); 228 1.15.4.2 tls void (*pbs_c_8)(void *, bus_space_handle_t, bus_size_t, 229 1.15.4.2 tls bus_space_handle_t, bus_size_t, bus_size_t); 230 1.15.4.2 tls }; 231 1.15.4.2 tls 232 1.15.4.2 tls #ifdef _KERNEL 233 1.15.4.2 tls #define _wbflush() __asm volatile("sync.l") 234 1.15.4.2 tls #ifdef _PLAYSTATION2_BUS_SPACE_PRIVATE 235 1.15.4.2 tls 236 1.15.4.2 tls #ifndef __read_1 237 1.15.4.2 tls #define __read_1(a) (*(volatile u_int8_t *)(a)) 238 1.15.4.2 tls #endif 239 1.15.4.2 tls #ifndef __read_2 240 1.15.4.2 tls #define __read_2(a) (*(volatile u_int16_t *)(a)) 241 1.15.4.2 tls #endif 242 1.15.4.2 tls #ifndef __read_4 243 1.15.4.2 tls #define __read_4(a) (*(volatile u_int32_t *)(a)) 244 1.15.4.2 tls #endif 245 1.15.4.2 tls #ifndef __read_8 246 1.15.4.2 tls #define __read_8(a) \ 247 1.15.4.2 tls ({ \ 248 1.15.4.2 tls u_int32_t lo, hi; \ 249 1.15.4.2 tls __asm volatile( \ 250 1.15.4.2 tls ".set noreorder;" \ 251 1.15.4.2 tls ".set push;" \ 252 1.15.4.2 tls ".set mips3;" \ 253 1.15.4.2 tls "ld $8, (%2);" \ 254 1.15.4.2 tls "dsra %1, $8, 32;" \ 255 1.15.4.2 tls "dsll %0, $8, 32;" \ 256 1.15.4.2 tls "dsra %0, %0, 32;" \ 257 1.15.4.2 tls ".set pop;" \ 258 1.15.4.2 tls ".set reorder;" \ 259 1.15.4.2 tls : "=r"(lo), "=r"(hi) : "r"(a) : "$8"); \ 260 1.15.4.2 tls ((u_int64_t)hi << 32) | lo; \ 261 1.15.4.2 tls }) 262 1.15.4.2 tls #endif 263 1.15.4.2 tls #define __read_16(a) "error. not yet" 264 1.15.4.2 tls 265 1.15.4.2 tls #ifndef __write_1 266 1.15.4.2 tls #define __write_1(a, v) { \ 267 1.15.4.2 tls *(volatile u_int8_t *)(a) = (v); \ 268 1.15.4.2 tls _wbflush(); \ 269 1.15.4.2 tls } 270 1.15.4.2 tls #endif 271 1.15.4.2 tls #ifndef __write_2 272 1.15.4.2 tls #define __write_2(a, v) { \ 273 1.15.4.2 tls *(volatile u_int16_t *)(a) = (v); \ 274 1.15.4.2 tls _wbflush(); \ 275 1.15.4.2 tls } 276 1.15.4.2 tls #endif 277 1.15.4.2 tls #ifndef __write_4 278 1.15.4.2 tls #define __write_4(a, v) { \ 279 1.15.4.2 tls *(volatile u_int32_t *)(a) = (v); \ 280 1.15.4.2 tls _wbflush(); \ 281 1.15.4.2 tls } 282 1.15.4.2 tls #endif 283 1.15.4.2 tls #ifdef EE_GCC 284 1.15.4.2 tls #ifndef __write_8 285 1.15.4.2 tls #define __write_8(a, v) (*(volatile u_int64_t *)(a) = (v)) { \ 286 1.15.4.2 tls _wbflush(); \ 287 1.15.4.2 tls } 288 1.15.4.2 tls #endif 289 1.15.4.2 tls #ifndef __write_16 290 1.15.4.2 tls #define __write_16(a, v) (*(volatile u_int128_t *)(a) = (v)) { \ 291 1.15.4.2 tls _wbflush(); \ 292 1.15.4.2 tls } 293 1.15.4.2 tls #endif 294 1.15.4.2 tls #else /* EE_GCC */ 295 1.15.4.2 tls #ifdef __write_8 296 1.15.4.2 tls #error "can't override __write_8" 297 1.15.4.2 tls #endif 298 1.15.4.2 tls static __inline void 299 1.15.4.2 tls __write_8(bus_addr_t a, u_int64_t v) 300 1.15.4.2 tls { 301 1.15.4.2 tls __asm volatile( 302 1.15.4.2 tls ".set noreorder;" 303 1.15.4.2 tls ".set push;" 304 1.15.4.2 tls ".set arch = r5900;" 305 1.15.4.2 tls "pextlw $8, %0, %1;" 306 1.15.4.2 tls "sd $8, 0(%2);" 307 1.15.4.2 tls "sync.l;" 308 1.15.4.2 tls ".set pop;" 309 1.15.4.2 tls ".set reorder;" 310 1.15.4.2 tls : : "r"((u_int32_t)((u_int64_t)(v) >> 32)), 311 1.15.4.2 tls "r"((u_int32_t)(v)), "r"((u_int32_t)(a)) : "$8"); 312 1.15.4.2 tls } 313 1.15.4.2 tls #define _write_16(a) "error. not yet" 314 1.15.4.2 tls #endif /* EE_GCC */ 315 1.15.4.2 tls 316 1.15.4.2 tls #define __TYPENAME(BITS) u_int##BITS##_t 317 1.15.4.2 tls 318 1.15.4.2 tls #define _BUS_SPACE_READ(PREFIX, BYTES, BITS) \ 319 1.15.4.2 tls static __TYPENAME(BITS) \ 320 1.15.4.2 tls PREFIX##_read_##BYTES(void *, bus_space_handle_t, bus_size_t); \ 321 1.15.4.2 tls static __TYPENAME(BITS) \ 322 1.15.4.2 tls PREFIX##_read_##BYTES(void *tag, bus_space_handle_t bsh, \ 323 1.15.4.2 tls bus_size_t offset) \ 324 1.15.4.2 tls { \ 325 1.15.4.2 tls return __read_##BYTES(VADDR(bsh, offset)); \ 326 1.15.4.2 tls } 327 1.15.4.2 tls 328 1.15.4.2 tls #define _BUS_SPACE_READ_MULTI(PREFIX, BYTES, BITS) \ 329 1.15.4.2 tls static void \ 330 1.15.4.2 tls PREFIX##_read_multi_##BYTES(void *, bus_space_handle_t, bus_size_t, \ 331 1.15.4.2 tls __TYPENAME(BITS) *, bus_size_t); \ 332 1.15.4.2 tls static void \ 333 1.15.4.2 tls PREFIX##_read_multi_##BYTES(void *tag, bus_space_handle_t bsh, \ 334 1.15.4.2 tls bus_size_t offset, __TYPENAME(BITS) *addr, bus_size_t count) \ 335 1.15.4.2 tls { \ 336 1.15.4.2 tls bus_addr_t a = VADDR(bsh, offset); \ 337 1.15.4.2 tls while (count--) \ 338 1.15.4.2 tls *addr++ = __read_##BYTES(a); \ 339 1.15.4.2 tls } 340 1.15.4.2 tls 341 1.15.4.2 tls #define _BUS_SPACE_READ_REGION(PREFIX, BYTES, BITS) \ 342 1.15.4.2 tls static void \ 343 1.15.4.2 tls PREFIX##_read_region_##BYTES(void *, bus_space_handle_t, bus_size_t, \ 344 1.15.4.2 tls __TYPENAME(BITS) *, bus_size_t); \ 345 1.15.4.2 tls static void \ 346 1.15.4.2 tls PREFIX##_read_region_##BYTES(void *tag, bus_space_handle_t bsh, \ 347 1.15.4.2 tls bus_size_t offset, __TYPENAME(BITS) *addr, bus_size_t count) \ 348 1.15.4.2 tls { \ 349 1.15.4.2 tls while (count--) { \ 350 1.15.4.2 tls *addr++ = __read_##BYTES(VADDR(bsh, offset)); \ 351 1.15.4.2 tls offset += BYTES; \ 352 1.15.4.2 tls } \ 353 1.15.4.2 tls } 354 1.15.4.2 tls 355 1.15.4.2 tls #define _BUS_SPACE_WRITE(PREFIX, BYTES, BITS) \ 356 1.15.4.2 tls static void \ 357 1.15.4.2 tls PREFIX##_write_##BYTES(void *, bus_space_handle_t, bus_size_t, \ 358 1.15.4.2 tls __TYPENAME(BITS)); \ 359 1.15.4.2 tls static void \ 360 1.15.4.2 tls PREFIX##_write_##BYTES(void *tag, bus_space_handle_t bsh, \ 361 1.15.4.2 tls bus_size_t offset, __TYPENAME(BITS) value) \ 362 1.15.4.2 tls { \ 363 1.15.4.2 tls __write_##BYTES(VADDR(bsh, offset), value); \ 364 1.15.4.2 tls } 365 1.15.4.2 tls 366 1.15.4.2 tls #define _BUS_SPACE_WRITE_MULTI(PREFIX, BYTES, BITS) \ 367 1.15.4.2 tls static void \ 368 1.15.4.2 tls PREFIX##_write_multi_##BYTES(void *, bus_space_handle_t, bus_size_t, \ 369 1.15.4.2 tls const __TYPENAME(BITS) *, bus_size_t); \ 370 1.15.4.2 tls static void \ 371 1.15.4.2 tls PREFIX##_write_multi_##BYTES(void *tag, bus_space_handle_t bsh, \ 372 1.15.4.2 tls bus_size_t offset, const __TYPENAME(BITS) *addr, bus_size_t count) \ 373 1.15.4.2 tls { \ 374 1.15.4.2 tls bus_addr_t a = VADDR(bsh, offset); \ 375 1.15.4.2 tls while (count--) { \ 376 1.15.4.2 tls __write_##BYTES(a, *addr++); \ 377 1.15.4.2 tls } \ 378 1.15.4.2 tls } 379 1.15.4.2 tls 380 1.15.4.2 tls #define _BUS_SPACE_WRITE_REGION(PREFIX, BYTES, BITS) \ 381 1.15.4.2 tls static void \ 382 1.15.4.2 tls PREFIX##_write_region_##BYTES(void *, bus_space_handle_t, bus_size_t, \ 383 1.15.4.2 tls const __TYPENAME(BITS) *, bus_size_t); \ 384 1.15.4.2 tls static void \ 385 1.15.4.2 tls PREFIX##_write_region_##BYTES(void *tag, bus_space_handle_t bsh, \ 386 1.15.4.2 tls bus_size_t offset, const __TYPENAME(BITS) *addr, bus_size_t count) \ 387 1.15.4.2 tls { \ 388 1.15.4.2 tls while (count--) { \ 389 1.15.4.2 tls __write_##BYTES(VADDR(bsh, offset), *addr++); \ 390 1.15.4.2 tls offset += BYTES; \ 391 1.15.4.2 tls } \ 392 1.15.4.2 tls } 393 1.15.4.2 tls 394 1.15.4.2 tls #define _BUS_SPACE_SET_MULTI(PREFIX, BYTES, BITS) \ 395 1.15.4.2 tls static void \ 396 1.15.4.2 tls PREFIX##_set_multi_##BYTES(void *, bus_space_handle_t, bus_size_t, \ 397 1.15.4.2 tls __TYPENAME(BITS), bus_size_t); \ 398 1.15.4.2 tls static void \ 399 1.15.4.2 tls PREFIX##_set_multi_##BYTES(void *tag, bus_space_handle_t bsh, \ 400 1.15.4.2 tls bus_size_t offset, __TYPENAME(BITS) value, bus_size_t count) \ 401 1.15.4.2 tls { \ 402 1.15.4.2 tls bus_addr_t a = VADDR(bsh, offset); \ 403 1.15.4.2 tls while (count--) { \ 404 1.15.4.2 tls __write_##BYTES(a, value); \ 405 1.15.4.2 tls } \ 406 1.15.4.2 tls } 407 1.15.4.2 tls 408 1.15.4.2 tls #define _BUS_SPACE_SET_REGION(PREFIX, BYTES, BITS) \ 409 1.15.4.2 tls static void \ 410 1.15.4.2 tls PREFIX##_set_region_##BYTES(void *, bus_space_handle_t, bus_size_t, \ 411 1.15.4.2 tls __TYPENAME(BITS), bus_size_t); \ 412 1.15.4.2 tls static void \ 413 1.15.4.2 tls PREFIX##_set_region_##BYTES(void *tag, bus_space_handle_t bsh, \ 414 1.15.4.2 tls bus_size_t offset, __TYPENAME(BITS) value, bus_size_t count) \ 415 1.15.4.2 tls { \ 416 1.15.4.2 tls while (count--) { \ 417 1.15.4.2 tls __write_##BYTES(VADDR(bsh, offset), value); \ 418 1.15.4.2 tls offset += BYTES; \ 419 1.15.4.2 tls } \ 420 1.15.4.2 tls } 421 1.15.4.2 tls 422 1.15.4.2 tls #define _BUS_SPACE_COPY_REGION(PREFIX, BYTES, BITS) \ 423 1.15.4.2 tls static void \ 424 1.15.4.2 tls PREFIX##_copy_region_##BYTES(void *, bus_space_handle_t, bus_size_t, \ 425 1.15.4.2 tls bus_space_handle_t, bus_size_t, bus_size_t); \ 426 1.15.4.2 tls static void \ 427 1.15.4.2 tls PREFIX##_copy_region_##BYTES(void *t, bus_space_handle_t h1, \ 428 1.15.4.2 tls bus_size_t o1, bus_space_handle_t h2, bus_size_t o2, bus_size_t c) \ 429 1.15.4.2 tls { \ 430 1.15.4.2 tls bus_size_t o; \ 431 1.15.4.2 tls if ((h1 + o1) >= (h2 + o2)) { \ 432 1.15.4.2 tls /* src after dest: copy forward */ \ 433 1.15.4.2 tls for (o = 0; c != 0; c--, o += BYTES) \ 434 1.15.4.2 tls __write_##BYTES(VADDR(h2, o2 + o), \ 435 1.15.4.2 tls __read_##BYTES(VADDR(h1, o1 + o))); \ 436 1.15.4.2 tls } else { \ 437 1.15.4.2 tls /* dest after src: copy backwards */ \ 438 1.15.4.2 tls for (o = (c - 1) * BYTES; c != 0; c--, o -= BYTES) \ 439 1.15.4.2 tls __write_##BYTES(VADDR(h2, o2 + o), \ 440 1.15.4.2 tls __read_##BYTES(VADDR(h1, o1 + o))); \ 441 1.15.4.2 tls } \ 442 1.15.4.2 tls } 443 1.15.4.2 tls 444 1.15.4.2 tls #define _BUS_SPACE_NO_MAP \ 445 1.15.4.2 tls (int (*)(void *, bus_addr_t, bus_size_t, int, \ 446 1.15.4.2 tls bus_space_handle_t *))_bus_space_invalid_access 447 1.15.4.2 tls #define _BUS_SPACE_NO_UNMAP \ 448 1.15.4.2 tls (void (*)(void *, bus_space_handle_t, bus_size_t)) \ 449 1.15.4.2 tls _bus_space_invalid_access 450 1.15.4.2 tls #define _BUS_SPACE_NO_SUBREGION \ 451 1.15.4.2 tls (int (*)(void *, bus_space_handle_t, bus_size_t, bus_size_t, \ 452 1.15.4.2 tls bus_space_handle_t *))_bus_space_invalid_access 453 1.15.4.2 tls #define _BUS_SPACE_NO_ALLOC \ 454 1.15.4.2 tls (int (*)(void *, bus_addr_t, bus_addr_t, bus_size_t, bus_size_t,\ 455 1.15.4.2 tls bus_size_t, int, bus_addr_t *, bus_space_handle_t *)) \ 456 1.15.4.2 tls _bus_space_invalid_access 457 1.15.4.2 tls #define _BUS_SPACE_NO_FREE \ 458 1.15.4.2 tls (void (*)(void *, bus_space_handle_t, bus_size_t)) \ 459 1.15.4.2 tls _bus_space_invalid_access 460 1.15.4.2 tls #define _BUS_SPACE_NO_VADDR \ 461 1.15.4.2 tls (void *(*)(void *, bus_space_handle_t))_bus_space_invalid_access 462 1.15.4.2 tls #define _BUS_SPACE_NO_READ(BYTES, BITS) \ 463 1.15.4.2 tls (u_int##BITS##_t (*)(void *, bus_space_handle_t, bus_size_t)) \ 464 1.15.4.2 tls _bus_space_invalid_access 465 1.15.4.2 tls #define _BUS_SPACE_NO_READ_MULTI(BYTES, BITS) \ 466 1.15.4.2 tls (void (*)(void *, bus_space_handle_t, bus_size_t, \ 467 1.15.4.2 tls u_int##BITS##_t *, bus_size_t))_bus_space_invalid_access 468 1.15.4.2 tls #define _BUS_SPACE_NO_READ_REGION(BYTES, BITS) \ 469 1.15.4.2 tls (void (*)(void *, bus_space_handle_t, bus_size_t, \ 470 1.15.4.2 tls u_int##BITS##_t *, bus_size_t))_bus_space_invalid_access 471 1.15.4.2 tls #define _BUS_SPACE_NO_WRITE(BYTES, BITS) \ 472 1.15.4.2 tls (void (*)(void *, bus_space_handle_t, bus_size_t, \ 473 1.15.4.2 tls u_int##BITS##_t))_bus_space_invalid_access 474 1.15.4.2 tls #define _BUS_SPACE_NO_WRITE_MULTI(BYTES, BITS) \ 475 1.15.4.2 tls (void (*)(void *, bus_space_handle_t, bus_size_t, \ 476 1.15.4.2 tls const u_int##BITS##_t *, bus_size_t))_bus_space_invalid_access 477 1.15.4.2 tls #define _BUS_SPACE_NO_WRITE_REGION(BYTES, BITS) \ 478 1.15.4.2 tls (void (*)(void *, bus_space_handle_t, bus_size_t, \ 479 1.15.4.2 tls const u_int##BITS##_t *, bus_size_t))_bus_space_invalid_access 480 1.15.4.2 tls #define _BUS_SPACE_NO_SET_MULTI(BYTES, BITS) \ 481 1.15.4.2 tls (void (*)(void *, bus_space_handle_t, bus_size_t, \ 482 1.15.4.2 tls u_int##BITS##_t, bus_size_t))_bus_space_invalid_access 483 1.15.4.2 tls #define _BUS_SPACE_NO_SET_REGION(BYTES, BITS) \ 484 1.15.4.2 tls (void (*)(void *, bus_space_handle_t, bus_size_t, \ 485 1.15.4.2 tls u_int##BITS##_t, bus_size_t))_bus_space_invalid_access 486 1.15.4.2 tls #define _BUS_SPACE_NO_COPY_REGION(BYTES, BITS) \ 487 1.15.4.2 tls (void (*)(void *, bus_space_handle_t, bus_size_t, \ 488 1.15.4.2 tls bus_space_handle_t, bus_size_t, bus_size_t))_bus_space_invalid_access 489 1.15.4.2 tls 490 1.15.4.2 tls void _bus_space_invalid_access(void); 491 1.15.4.2 tls #endif /* _PLAYSTATION2_BUS_SPACE_PRIVATE */ 492 1.15.4.2 tls 493 1.15.4.2 tls #define __pbs_c(a,b) __CONCAT(a,b) 494 1.15.4.2 tls #define __pbs_opname(op,size) __pbs_c(__pbs_c(__pbs_c(pbs_,op),_),size) 495 1.15.4.2 tls 496 1.15.4.2 tls #define __pbs_rs(sz, tn, t, h, o) \ 497 1.15.4.2 tls (__BUS_SPACE_ADDRESS_SANITY((h) + (o), tn, "bus addr"), \ 498 1.15.4.2 tls (*(t)->__pbs_opname(r,sz))((t)->pbs_cookie, h, o)) 499 1.15.4.2 tls 500 1.15.4.2 tls #define __pbs_ws(sz, tn, t, h, o, v) \ 501 1.15.4.2 tls ({ \ 502 1.15.4.2 tls __BUS_SPACE_ADDRESS_SANITY((h) + (o), tn, "bus addr"); \ 503 1.15.4.2 tls (*(t)->__pbs_opname(w,sz))((t)->pbs_cookie, h, o, v); \ 504 1.15.4.2 tls }) 505 1.15.4.2 tls 506 1.15.4.2 tls #define __pbs_nonsingle(type, sz, tn, t, h, o, a, c) \ 507 1.15.4.2 tls ({ \ 508 1.15.4.2 tls __BUS_SPACE_ADDRESS_SANITY((a), tn, "buffer"); \ 509 1.15.4.2 tls __BUS_SPACE_ADDRESS_SANITY((h) + (o), tn, "bus addr"); \ 510 1.15.4.2 tls (*(t)->__pbs_opname(type,sz))((t)->pbs_cookie, h, o, a, c); \ 511 1.15.4.2 tls }) 512 1.15.4.2 tls 513 1.15.4.2 tls #define __pbs_set(type, sz, tn, t, h, o, v, c) \ 514 1.15.4.2 tls ({ \ 515 1.15.4.2 tls __BUS_SPACE_ADDRESS_SANITY((h) + (o), tn, "bus addr"); \ 516 1.15.4.2 tls (*(t)->__pbs_opname(type,sz))((t)->pbs_cookie, h, o, v, c); \ 517 1.15.4.2 tls }) 518 1.15.4.2 tls 519 1.15.4.2 tls #define __pbs_copy(sz, tn, t, h1, o1, h2, o2, cnt) \ 520 1.15.4.2 tls ({ \ 521 1.15.4.2 tls __BUS_SPACE_ADDRESS_SANITY((h1) + (o1), tn, "bus addr 1"); \ 522 1.15.4.2 tls __BUS_SPACE_ADDRESS_SANITY((h2) + (o2), tn, "bus addr 2"); \ 523 1.15.4.2 tls (*(t)->__pbs_opname(c,sz))((t)->pbs_cookie, h1, o1, h2, o2, cnt); \ 524 1.15.4.2 tls }) 525 1.15.4.2 tls 526 1.15.4.2 tls /* 527 1.15.4.2 tls * Create default bus_space tag. 528 1.15.4.2 tls */ 529 1.15.4.2 tls bus_space_tag_t bus_space_create(bus_space_tag_t, const char *, bus_addr_t, 530 1.15.4.2 tls bus_size_t); 531 1.15.4.2 tls void bus_space_destroy(bus_space_tag_t); 532 1.15.4.2 tls 533 1.15.4.2 tls /* 534 1.15.4.2 tls * Mapping and unmapping operations. 535 1.15.4.2 tls */ 536 1.15.4.2 tls #define bus_space_map(t, a, s, f, hp) \ 537 1.15.4.2 tls (*(t)->pbs_map)((t)->pbs_cookie, (a), (s), (f), (hp)) 538 1.15.4.2 tls #define bus_space_unmap(t, h, s) \ 539 1.15.4.2 tls (*(t)->pbs_unmap)((t)->pbs_cookie, (h), (s)) 540 1.15.4.2 tls #define bus_space_subregion(t, h, o, s, hp) \ 541 1.15.4.2 tls (*(t)->pbs_subregion)((t)->pbs_cookie, (h), (o), (s), (hp)) 542 1.15.4.2 tls 543 1.15.4.2 tls #endif /* _KERNEL */ 544 1.15.4.2 tls 545 1.15.4.2 tls #define BUS_SPACE_MAP_CACHEABLE 0x01 546 1.15.4.2 tls #define BUS_SPACE_MAP_LINEAR 0x02 547 1.15.4.2 tls #define BUS_SPACE_MAP_PREFETCHABLE 0x04 548 1.15.4.2 tls 549 1.15.4.2 tls #ifdef _KERNEL 550 1.15.4.2 tls /* 551 1.15.4.2 tls * Allocation and deallocation operations. 552 1.15.4.2 tls */ 553 1.15.4.2 tls #define bus_space_alloc(t, rs, re, s, a, b, f, ap, hp) \ 554 1.15.4.2 tls (*(t)->pbs_alloc)((t)->pbs_cookie, (rs), (re), (s), (a), (b), \ 555 1.15.4.2 tls (f), (ap), (hp)) 556 1.15.4.2 tls #define bus_space_free(t, h, s) \ 557 1.15.4.2 tls (*(t)->pbs_free)((t)->pbs_cookie, (h), (s)) 558 1.15.4.2 tls 559 1.15.4.2 tls /* 560 1.15.4.2 tls * Get kernel virtual address for ranges mapped BUS_SPACE_MAP_LINEAR. 561 1.15.4.2 tls */ 562 1.15.4.2 tls #define bus_space_vaddr(t, h) \ 563 1.15.4.2 tls (*(t)->pbs_vaddr)((t)->pbs_cookie, (h)) 564 1.15.4.2 tls 565 1.15.4.2 tls /* 566 1.15.4.2 tls * Bus barrier operations. The playstation2 does not currently require 567 1.15.4.2 tls * barriers, but we must provide the flags to MI code. 568 1.15.4.2 tls */ 569 1.15.4.2 tls #define bus_space_barrier(t, h, o, l, f) \ 570 1.15.4.2 tls ({ \ 571 1.15.4.2 tls _wbflush(); \ 572 1.15.4.2 tls }) 573 1.15.4.2 tls 574 1.15.4.2 tls 575 1.15.4.2 tls #define BUS_SPACE_BARRIER_READ 0x01 576 1.15.4.2 tls #define BUS_SPACE_BARRIER_WRITE 0x02 577 1.15.4.2 tls 578 1.15.4.2 tls 579 1.15.4.2 tls /* 580 1.15.4.2 tls * Bus read (single) operations. 581 1.15.4.2 tls */ 582 1.15.4.2 tls #define bus_space_read_1(t, h, o) __pbs_rs(1,u_int8_t,(t),(h),(o)) 583 1.15.4.2 tls #define bus_space_read_2(t, h, o) __pbs_rs(2,u_int16_t,(t),(h),(o)) 584 1.15.4.2 tls #define bus_space_read_4(t, h, o) __pbs_rs(4,u_int32_t,(t),(h),(o)) 585 1.15.4.2 tls #define bus_space_read_8(t, h, o) __pbs_rs(8,u_int64_t,(t),(h),(o)) 586 1.15.4.2 tls 587 1.15.4.2 tls 588 1.15.4.2 tls /* 589 1.15.4.2 tls * Bus read multiple operations. 590 1.15.4.2 tls */ 591 1.15.4.2 tls #define bus_space_read_multi_1(t, h, o, a, c) \ 592 1.15.4.2 tls __pbs_nonsingle(rm,1,u_int8_t,(t),(h),(o),(a),(c)) 593 1.15.4.2 tls #define bus_space_read_multi_2(t, h, o, a, c) \ 594 1.15.4.2 tls __pbs_nonsingle(rm,2,u_int16_t,(t),(h),(o),(a),(c)) 595 1.15.4.2 tls #define bus_space_read_multi_4(t, h, o, a, c) \ 596 1.15.4.2 tls __pbs_nonsingle(rm,4,u_int32_t,(t),(h),(o),(a),(c)) 597 1.15.4.2 tls #define bus_space_read_multi_8(t, h, o, a, c) \ 598 1.15.4.2 tls __pbs_nonsingle(rm,8,u_int64_t,(t),(h),(o),(a),(c)) 599 1.15.4.2 tls 600 1.15.4.2 tls 601 1.15.4.2 tls /* 602 1.15.4.2 tls * Bus read region operations. 603 1.15.4.2 tls */ 604 1.15.4.2 tls #define bus_space_read_region_1(t, h, o, a, c) \ 605 1.15.4.2 tls __pbs_nonsingle(rr,1,u_int8_t,(t),(h),(o),(a),(c)) 606 1.15.4.2 tls #define bus_space_read_region_2(t, h, o, a, c) \ 607 1.15.4.2 tls __pbs_nonsingle(rr,2,u_int16_t,(t),(h),(o),(a),(c)) 608 1.15.4.2 tls #define bus_space_read_region_4(t, h, o, a, c) \ 609 1.15.4.2 tls __pbs_nonsingle(rr,4,u_int32_t,(t),(h),(o),(a),(c)) 610 1.15.4.2 tls #define bus_space_read_region_8(t, h, o, a, c) \ 611 1.15.4.2 tls __pbs_nonsingle(rr,8,u_int64_t,(t),(h),(o),(a),(c)) 612 1.15.4.2 tls 613 1.15.4.2 tls 614 1.15.4.2 tls /* 615 1.15.4.2 tls * Bus write (single) operations. 616 1.15.4.2 tls */ 617 1.15.4.2 tls #define bus_space_write_1(t, h, o, v) __pbs_ws(1,u_int8_t,(t),(h),(o),(v)) 618 1.15.4.2 tls #define bus_space_write_2(t, h, o, v) __pbs_ws(2,u_int16_t,(t),(h),(o),(v)) 619 1.15.4.2 tls #define bus_space_write_4(t, h, o, v) __pbs_ws(4,u_int32_t,(t),(h),(o),(v)) 620 1.15.4.2 tls #define bus_space_write_8(t, h, o, v) __pbs_ws(8,u_int64_t,(t),(h),(o),(v)) 621 1.15.4.2 tls 622 1.15.4.2 tls 623 1.15.4.2 tls /* 624 1.15.4.2 tls * Bus write multiple operations. 625 1.15.4.2 tls */ 626 1.15.4.2 tls #define bus_space_write_multi_1(t, h, o, a, c) \ 627 1.15.4.2 tls __pbs_nonsingle(wm,1,u_int8_t,(t),(h),(o),(a),(c)) 628 1.15.4.2 tls #define bus_space_write_multi_2(t, h, o, a, c) \ 629 1.15.4.2 tls __pbs_nonsingle(wm,2,u_int16_t,(t),(h),(o),(a),(c)) 630 1.15.4.2 tls #define bus_space_write_multi_4(t, h, o, a, c) \ 631 1.15.4.2 tls __pbs_nonsingle(wm,4,u_int32_t,(t),(h),(o),(a),(c)) 632 1.15.4.2 tls #define bus_space_write_multi_8(t, h, o, a, c) \ 633 1.15.4.2 tls __pbs_nonsingle(wm,8,u_int64_t,(t),(h),(o),(a),(c)) 634 1.15.4.2 tls 635 1.15.4.2 tls 636 1.15.4.2 tls /* 637 1.15.4.2 tls * Bus write region operations. 638 1.15.4.2 tls */ 639 1.15.4.2 tls #define bus_space_write_region_1(t, h, o, a, c) \ 640 1.15.4.2 tls __pbs_nonsingle(wr,1,u_int8_t,(t),(h),(o),(a),(c)) 641 1.15.4.2 tls #define bus_space_write_region_2(t, h, o, a, c) \ 642 1.15.4.2 tls __pbs_nonsingle(wr,2,u_int16_t,(t),(h),(o),(a),(c)) 643 1.15.4.2 tls #define bus_space_write_region_4(t, h, o, a, c) \ 644 1.15.4.2 tls __pbs_nonsingle(wr,4,u_int32_t,(t),(h),(o),(a),(c)) 645 1.15.4.2 tls #define bus_space_write_region_8(t, h, o, a, c) \ 646 1.15.4.2 tls __pbs_nonsingle(wr,8,u_int64_t,(t),(h),(o),(a),(c)) 647 1.15.4.2 tls 648 1.15.4.2 tls 649 1.15.4.2 tls /* 650 1.15.4.2 tls * Set multiple operations. 651 1.15.4.2 tls */ 652 1.15.4.2 tls #define bus_space_set_multi_1(t, h, o, v, c) \ 653 1.15.4.2 tls __pbs_set(sm,1,u_int8_t,(t),(h),(o),(v),(c)) 654 1.15.4.2 tls #define bus_space_set_multi_2(t, h, o, v, c) \ 655 1.15.4.2 tls __pbs_set(sm,2,u_int16_t,(t),(h),(o),(v),(c)) 656 1.15.4.2 tls #define bus_space_set_multi_4(t, h, o, v, c) \ 657 1.15.4.2 tls __pbs_set(sm,4,u_int32_t,(t),(h),(o),(v),(c)) 658 1.15.4.2 tls #define bus_space_set_multi_8(t, h, o, v, c) \ 659 1.15.4.2 tls __pbs_set(sm,8,u_int64_t,(t),(h),(o),(v),(c)) 660 1.15.4.2 tls 661 1.15.4.2 tls 662 1.15.4.2 tls /* 663 1.15.4.2 tls * Set region operations. 664 1.15.4.2 tls */ 665 1.15.4.2 tls #define bus_space_set_region_1(t, h, o, v, c) \ 666 1.15.4.2 tls __pbs_set(sr,1,u_int8_t,(t),(h),(o),(v),(c)) 667 1.15.4.2 tls #define bus_space_set_region_2(t, h, o, v, c) \ 668 1.15.4.2 tls __pbs_set(sr,2,u_int16_t,(t),(h),(o),(v),(c)) 669 1.15.4.2 tls #define bus_space_set_region_4(t, h, o, v, c) \ 670 1.15.4.2 tls __pbs_set(sr,4,u_int32_t,(t),(h),(o),(v),(c)) 671 1.15.4.2 tls #define bus_space_set_region_8(t, h, o, v, c) \ 672 1.15.4.2 tls __pbs_set(sr,8,u_int64_t,(t),(h),(o),(v),(c)) 673 1.15.4.2 tls 674 1.15.4.2 tls 675 1.15.4.2 tls /* 676 1.15.4.2 tls * Copy region operations. 677 1.15.4.2 tls */ 678 1.15.4.2 tls #define bus_space_copy_region_1(t, h1, o1, h2, o2, c) \ 679 1.15.4.2 tls __pbs_copy(1, u_int8_t, (t), (h1), (o1), (h2), (o2), (c)) 680 1.15.4.2 tls #define bus_space_copy_region_2(t, h1, o1, h2, o2, c) \ 681 1.15.4.2 tls __pbs_copy(2, u_int16_t, (t), (h1), (o1), (h2), (o2), (c)) 682 1.15.4.2 tls #define bus_space_copy_region_4(t, h1, o1, h2, o2, c) \ 683 1.15.4.2 tls __pbs_copy(4, u_int32_t, (t), (h1), (o1), (h2), (o2), (c)) 684 1.15.4.2 tls #define bus_space_copy_region_8(t, h1, o1, h2, o2, c) \ 685 1.15.4.2 tls __pbs_copy(8, u_int64_t, (t), (h1), (o1), (h2), (o2), (c)) 686 1.15.4.2 tls 687 1.15.4.2 tls /* 688 1.15.4.2 tls * Bus stream operations--defined in terms of non-stream counterparts 689 1.15.4.2 tls */ 690 1.15.4.2 tls #define __BUS_SPACE_HAS_STREAM_METHODS 1 691 1.15.4.2 tls #define bus_space_read_stream_1 bus_space_read_1 692 1.15.4.2 tls #define bus_space_read_stream_2 bus_space_read_2 693 1.15.4.2 tls #define bus_space_read_stream_4 bus_space_read_4 694 1.15.4.2 tls #define bus_space_read_stream_8 bus_space_read_8 695 1.15.4.2 tls #define bus_space_read_multi_stream_1 bus_space_read_multi_1 696 1.15.4.2 tls #define bus_space_read_multi_stream_2 bus_space_read_multi_2 697 1.15.4.2 tls #define bus_space_read_multi_stream_4 bus_space_read_multi_4 698 1.15.4.2 tls #define bus_space_read_multi_stream_8 bus_space_read_multi_8 699 1.15.4.2 tls #define bus_space_read_region_stream_1 bus_space_read_region_1 700 1.15.4.2 tls #define bus_space_read_region_stream_2 bus_space_read_region_2 701 1.15.4.2 tls #define bus_space_read_region_stream_4 bus_space_read_region_4 702 1.15.4.2 tls #define bus_space_read_region_stream_8 bus_space_read_region_8 703 1.15.4.2 tls #define bus_space_write_stream_1 bus_space_write_1 704 1.15.4.2 tls #define bus_space_write_stream_2 bus_space_write_2 705 1.15.4.2 tls #define bus_space_write_stream_4 bus_space_write_4 706 1.15.4.2 tls #define bus_space_write_stream_8 bus_space_write_8 707 1.15.4.2 tls #define bus_space_write_multi_stream_1 bus_space_write_multi_1 708 1.15.4.2 tls #define bus_space_write_multi_stream_2 bus_space_write_multi_2 709 1.15.4.2 tls #define bus_space_write_multi_stream_4 bus_space_write_multi_4 710 1.15.4.2 tls #define bus_space_write_multi_stream_8 bus_space_write_multi_8 711 1.15.4.2 tls #define bus_space_write_region_stream_1 bus_space_write_region_1 712 1.15.4.2 tls #define bus_space_write_region_stream_2 bus_space_write_region_2 713 1.15.4.2 tls #define bus_space_write_region_stream_4 bus_space_write_region_4 714 1.15.4.2 tls #define bus_space_write_region_stream_8 bus_space_write_region_8 715 1.15.4.2 tls 716 1.15.4.2 tls #endif /* _KERNEL */ 717 1.15.4.2 tls 718 1.15.4.2 tls /* 719 1.15.4.2 tls * Flags used in various bus DMA methods. 720 1.15.4.2 tls */ 721 1.15.4.2 tls #define BUS_DMA_WAITOK 0x000 /* safe to sleep (pseudo-flag) */ 722 1.15.4.2 tls #define BUS_DMA_NOWAIT 0x001 /* not safe to sleep */ 723 1.15.4.2 tls #define BUS_DMA_ALLOCNOW 0x002 /* perform resource allocation now */ 724 1.15.4.2 tls #define BUS_DMA_COHERENT 0x004 /* hint: map memory DMA coherent */ 725 1.15.4.2 tls #define BUS_DMA_STREAMING 0x008 /* hint: sequential, unidirectional */ 726 1.15.4.2 tls #define BUS_DMA_BUS1 0x010 /* placeholders for bus functions... */ 727 1.15.4.2 tls #define BUS_DMA_BUS2 0x020 728 1.15.4.2 tls #define BUS_DMA_BUS3 0x040 729 1.15.4.2 tls #define BUS_DMA_BUS4 0x080 730 1.15.4.2 tls #define BUS_DMA_READ 0x100 /* mapping is device -> memory only */ 731 1.15.4.2 tls #define BUS_DMA_WRITE 0x200 /* mapping is memory -> device only */ 732 1.15.4.2 tls #define BUS_DMA_NOCACHE 0x400 /* hint: map non-cached memory */ 733 1.15.4.2 tls 734 1.15.4.2 tls #define PLAYSTATION2_DMAMAP_COHERENT 0x10000 /* no cache flush necessary on sync */ 735 1.15.4.2 tls 736 1.15.4.2 tls /* Forwards needed by prototypes below. */ 737 1.15.4.2 tls struct mbuf; 738 1.15.4.2 tls struct uio; 739 1.15.4.2 tls 740 1.15.4.2 tls /* 741 1.15.4.2 tls * Operations performed by bus_dmamap_sync(). 742 1.15.4.2 tls */ 743 1.15.4.2 tls #define BUS_DMASYNC_PREREAD 0x01 /* pre-read synchronization */ 744 1.15.4.2 tls #define BUS_DMASYNC_POSTREAD 0x02 /* post-read synchronization */ 745 1.15.4.2 tls #define BUS_DMASYNC_PREWRITE 0x04 /* pre-write synchronization */ 746 1.15.4.2 tls #define BUS_DMASYNC_POSTWRITE 0x08 /* post-write synchronization */ 747 1.15.4.2 tls 748 1.15.4.2 tls typedef struct playstation2_bus_dma_tag *bus_dma_tag_t; 749 1.15.4.2 tls typedef struct playstation2_bus_dmamap *bus_dmamap_t; 750 1.15.4.2 tls 751 1.15.4.2 tls #define BUS_DMA_TAG_VALID(t) ((t) != (bus_dma_tag_t)0) 752 1.15.4.2 tls 753 1.15.4.2 tls /* 754 1.15.4.2 tls * bus_dma_segment_t 755 1.15.4.2 tls * 756 1.15.4.2 tls * Describes a single contiguous DMA transaction. Values 757 1.15.4.2 tls * are suitable for programming into DMA registers. 758 1.15.4.2 tls */ 759 1.15.4.2 tls struct playstation2_bus_dma_segment { 760 1.15.4.2 tls bus_addr_t ds_addr; /* DMA address */ 761 1.15.4.2 tls bus_size_t ds_len; /* length of transfer */ 762 1.15.4.2 tls bus_addr_t _ds_vaddr; /* virtual address, 0 if invalid */ 763 1.15.4.2 tls }; 764 1.15.4.2 tls typedef struct playstation2_bus_dma_segment bus_dma_segment_t; 765 1.15.4.2 tls 766 1.15.4.2 tls /* 767 1.15.4.2 tls * bus_dma_tag_t 768 1.15.4.2 tls * 769 1.15.4.2 tls * A machine-dependent opaque type describing the implementation of 770 1.15.4.2 tls * DMA for a given bus. 771 1.15.4.2 tls */ 772 1.15.4.2 tls 773 1.15.4.2 tls struct playstation2_bus_dma_tag { 774 1.15.4.2 tls /* 775 1.15.4.2 tls * DMA mapping methods. 776 1.15.4.2 tls */ 777 1.15.4.2 tls int (*_dmamap_create)(bus_dma_tag_t, bus_size_t, int, 778 1.15.4.2 tls bus_size_t, bus_size_t, int, bus_dmamap_t *); 779 1.15.4.2 tls void (*_dmamap_destroy)(bus_dma_tag_t, bus_dmamap_t); 780 1.15.4.2 tls int (*_dmamap_load)(bus_dma_tag_t, bus_dmamap_t, void *, 781 1.15.4.2 tls bus_size_t, struct proc *, int); 782 1.15.4.2 tls int (*_dmamap_load_mbuf)(bus_dma_tag_t, bus_dmamap_t, 783 1.15.4.2 tls struct mbuf *, int); 784 1.15.4.2 tls int (*_dmamap_load_uio)(bus_dma_tag_t, bus_dmamap_t, 785 1.15.4.2 tls struct uio *, int); 786 1.15.4.2 tls int (*_dmamap_load_raw)(bus_dma_tag_t, bus_dmamap_t, 787 1.15.4.2 tls bus_dma_segment_t *, int, bus_size_t, int); 788 1.15.4.2 tls void (*_dmamap_unload)(bus_dma_tag_t, bus_dmamap_t); 789 1.15.4.2 tls void (*_dmamap_sync)(bus_dma_tag_t, bus_dmamap_t, 790 1.15.4.2 tls bus_addr_t, bus_size_t, int); 791 1.15.4.2 tls 792 1.15.4.2 tls /* 793 1.15.4.2 tls * DMA memory utility functions. 794 1.15.4.2 tls */ 795 1.15.4.2 tls int (*_dmamem_alloc)(bus_dma_tag_t, bus_size_t, bus_size_t, 796 1.15.4.2 tls bus_size_t, bus_dma_segment_t *, int, int *, int); 797 1.15.4.2 tls void (*_dmamem_free)(bus_dma_tag_t, 798 1.15.4.2 tls bus_dma_segment_t *, int); 799 1.15.4.2 tls int (*_dmamem_map)(bus_dma_tag_t, bus_dma_segment_t *, 800 1.15.4.2 tls int, size_t, void **, int); 801 1.15.4.2 tls void (*_dmamem_unmap)(bus_dma_tag_t, void *, size_t); 802 1.15.4.2 tls paddr_t (*_dmamem_mmap)(bus_dma_tag_t, bus_dma_segment_t *, 803 1.15.4.2 tls int, off_t, int, int); 804 1.15.4.2 tls 805 1.15.4.2 tls /* 806 1.15.4.2 tls * DMA controller private. 807 1.15.4.2 tls */ 808 1.15.4.2 tls void *_dmachip_cookie; 809 1.15.4.2 tls }; 810 1.15.4.2 tls 811 1.15.4.2 tls #define bus_dmamap_create(t, s, n, m, b, f, p) \ 812 1.15.4.2 tls (*(t)->_dmamap_create)((t), (s), (n), (m), (b), (f), (p)) 813 1.15.4.2 tls #define bus_dmamap_destroy(t, p) \ 814 1.15.4.2 tls (*(t)->_dmamap_destroy)((t), (p)) 815 1.15.4.2 tls #define bus_dmamap_load(t, m, b, s, p, f) \ 816 1.15.4.2 tls (*(t)->_dmamap_load)((t), (m), (b), (s), (p), (f)) 817 1.15.4.2 tls #define bus_dmamap_load_mbuf(t, m, b, f) \ 818 1.15.4.2 tls (*(t)->_dmamap_load_mbuf)((t), (m), (b), (f)) 819 1.15.4.2 tls #define bus_dmamap_load_uio(t, m, u, f) \ 820 1.15.4.2 tls (*(t)->_dmamap_load_uio)((t), (m), (u), (f)) 821 1.15.4.2 tls #define bus_dmamap_load_raw(t, m, sg, n, s, f) \ 822 1.15.4.2 tls (*(t)->_dmamap_load_raw)((t), (m), (sg), (n), (s), (f)) 823 1.15.4.2 tls #define bus_dmamap_unload(t, p) \ 824 1.15.4.2 tls (*(t)->_dmamap_unload)((t), (p)) 825 1.15.4.2 tls #define bus_dmamap_sync(t, p, o, l, ops) \ 826 1.15.4.2 tls (*(t)->_dmamap_sync)((t), (p), (o), (l), (ops)) 827 1.15.4.2 tls 828 1.15.4.2 tls #define bus_dmamem_alloc(t, s, a, b, sg, n, r, f) \ 829 1.15.4.2 tls (*(t)->_dmamem_alloc)((t), (s), (a), (b), (sg), (n), (r), (f)) 830 1.15.4.2 tls #define bus_dmamem_free(t, sg, n) \ 831 1.15.4.2 tls (*(t)->_dmamem_free)((t), (sg), (n)) 832 1.15.4.2 tls #define bus_dmamem_map(t, sg, n, s, k, f) \ 833 1.15.4.2 tls (*(t)->_dmamem_map)((t), (sg), (n), (s), (k), (f)) 834 1.15.4.2 tls #define bus_dmamem_unmap(t, k, s) \ 835 1.15.4.2 tls (*(t)->_dmamem_unmap)((t), (k), (s)) 836 1.15.4.2 tls #define bus_dmamem_mmap(t, sg, n, o, p, f) \ 837 1.15.4.2 tls (*(t)->_dmamem_mmap)((t), (sg), (n), (o), (p), (f)) 838 1.15.4.2 tls 839 1.15.4.2 tls #define bus_dmatag_subregion(t, mna, mxa, nt, f) EOPNOTSUPP 840 1.15.4.2 tls #define bus_dmatag_destroy(t) 841 1.15.4.2 tls 842 1.15.4.2 tls /* 843 1.15.4.2 tls * bus_dmamap_t 844 1.15.4.2 tls * 845 1.15.4.2 tls * Describes a DMA mapping. 846 1.15.4.2 tls */ 847 1.15.4.2 tls struct playstation2_bus_dmamap { 848 1.15.4.2 tls /* 849 1.15.4.2 tls * PRIVATE MEMBERS: not for use my machine-independent code. 850 1.15.4.2 tls */ 851 1.15.4.2 tls bus_size_t _dm_size; /* largest DMA transfer mappable */ 852 1.15.4.2 tls int _dm_segcnt; /* number of segs this map can map */ 853 1.15.4.2 tls bus_size_t _dm_maxmaxsegsz; /* fixed largest possible segment */ 854 1.15.4.2 tls bus_size_t _dm_boundary; /* don't cross this */ 855 1.15.4.2 tls int _dm_flags; /* misc. flags */ 856 1.15.4.2 tls 857 1.15.4.2 tls /* 858 1.15.4.2 tls * PUBLIC MEMBERS: these are used by machine-independent code. 859 1.15.4.2 tls */ 860 1.15.4.2 tls bus_size_t dm_maxsegsz; /* largest possible segment */ 861 1.15.4.2 tls bus_size_t dm_mapsize; /* size of the mapping */ 862 1.15.4.2 tls int dm_nsegs; /* # valid segments in mapping */ 863 1.15.4.2 tls bus_dma_segment_t dm_segs[1]; /* segments; variable length */ 864 1.15.4.2 tls }; 865 1.15.4.2 tls 866 1.15.4.2 tls #ifdef _PLAYSTATION2_BUS_DMA_PRIVATE 867 1.15.4.2 tls int _bus_dmamap_create(bus_dma_tag_t, bus_size_t, int, bus_size_t, 868 1.15.4.2 tls bus_size_t, int, bus_dmamap_t *); 869 1.15.4.2 tls void _bus_dmamap_destroy(bus_dma_tag_t, bus_dmamap_t); 870 1.15.4.2 tls int _bus_dmamap_load(bus_dma_tag_t, bus_dmamap_t, void *, 871 1.15.4.2 tls bus_size_t, struct proc *, int); 872 1.15.4.2 tls int _bus_dmamap_load_mbuf(bus_dma_tag_t, bus_dmamap_t, 873 1.15.4.2 tls struct mbuf *, int); 874 1.15.4.2 tls int _bus_dmamap_load_uio(bus_dma_tag_t, bus_dmamap_t, 875 1.15.4.2 tls struct uio *, int); 876 1.15.4.2 tls int _bus_dmamap_load_raw(bus_dma_tag_t, bus_dmamap_t, 877 1.15.4.2 tls bus_dma_segment_t *, int, bus_size_t, int); 878 1.15.4.2 tls void _bus_dmamap_unload(bus_dma_tag_t, bus_dmamap_t); 879 1.15.4.2 tls void _bus_dmamap_sync(bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 880 1.15.4.2 tls bus_size_t, int); 881 1.15.4.2 tls 882 1.15.4.2 tls int _bus_dmamem_alloc(bus_dma_tag_t tag, bus_size_t size, 883 1.15.4.2 tls bus_size_t alignment, bus_size_t boundary, 884 1.15.4.2 tls bus_dma_segment_t *segs, int nsegs, int *rsegs, int flags); 885 1.15.4.2 tls void _bus_dmamem_free(bus_dma_tag_t tag, bus_dma_segment_t *segs, 886 1.15.4.2 tls int nsegs); 887 1.15.4.2 tls int _bus_dmamem_map(bus_dma_tag_t tag, bus_dma_segment_t *segs, 888 1.15.4.2 tls int nsegs, size_t size, void **kvap, int flags); 889 1.15.4.2 tls void _bus_dmamem_unmap(bus_dma_tag_t tag, void *kva, 890 1.15.4.2 tls size_t size); 891 1.15.4.2 tls paddr_t _bus_dmamem_mmap(bus_dma_tag_t tag, bus_dma_segment_t *segs, 892 1.15.4.2 tls int nsegs, off_t off, int prot, int flags); 893 1.15.4.2 tls 894 1.15.4.2 tls int _bus_dmamem_alloc_range(bus_dma_tag_t tag, bus_size_t size, 895 1.15.4.2 tls bus_size_t alignment, bus_size_t boundary, 896 1.15.4.2 tls bus_dma_segment_t *segs, int nsegs, int *rsegs, int flags, 897 1.15.4.2 tls vaddr_t low, vaddr_t high); 898 1.15.4.2 tls 899 1.15.4.2 tls extern struct playstation2_bus_dma_tag playstation2_default_bus_dma_tag; 900 1.15.4.2 tls #endif /* _PLAYSTATION2_BUS_DMA_PRIVATE */ 901 1.15.4.2 tls 902 1.15.4.2 tls #endif /* _PLAYSTATION2_BUS_H_ */ 903
Indexes created Fri Oct 31 11:10:07 GMT 2025