sii.c revision 1.2 1 1.2 ad /* $NetBSD: sii.c,v 1.2 2006/07/29 19:10:57 ad Exp $ */
2 1.2 ad
3 1.2 ad /*-
4 1.2 ad * Copyright (c) 1992, 1993
5 1.2 ad * The Regents of the University of California. All rights reserved.
6 1.2 ad *
7 1.2 ad * This code is derived from software contributed to Berkeley by
8 1.2 ad * Ralph Campbell and Rick Macklem.
9 1.2 ad *
10 1.2 ad * Redistribution and use in source and binary forms, with or without
11 1.2 ad * modification, are permitted provided that the following conditions
12 1.2 ad * are met:
13 1.2 ad * 1. Redistributions of source code must retain the above copyright
14 1.2 ad * notice, this list of conditions and the following disclaimer.
15 1.2 ad * 2. Redistributions in binary form must reproduce the above copyright
16 1.2 ad * notice, this list of conditions and the following disclaimer in the
17 1.2 ad * documentation and/or other materials provided with the distribution.
18 1.2 ad * 3. Neither the name of the University nor the names of its contributors
19 1.2 ad * may be used to endorse or promote products derived from this software
20 1.2 ad * without specific prior written permission.
21 1.2 ad *
22 1.2 ad * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23 1.2 ad * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 1.2 ad * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 1.2 ad * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26 1.2 ad * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 1.2 ad * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 1.2 ad * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 1.2 ad * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 1.2 ad * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 1.2 ad * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 1.2 ad * SUCH DAMAGE.
33 1.2 ad *
34 1.2 ad * @(#)sii.c 8.2 (Berkeley) 11/30/93
35 1.2 ad *
36 1.2 ad * from: Header: /sprite/src/kernel/dev/ds3100.md/RCS/devSII.c,
37 1.2 ad * v 9.2 89/09/14 13:37:41 jhh Exp $ SPRITE (DECWRL)";
38 1.2 ad */
39 1.2 ad
40 1.2 ad #include <sys/cdefs.h>
41 1.2 ad __KERNEL_RCSID(0, "$NetBSD: sii.c,v 1.2 2006/07/29 19:10:57 ad Exp $");
42 1.2 ad
43 1.2 ad #include "sii.h"
44 1.2 ad /*
45 1.2 ad * SCSI interface driver
46 1.2 ad */
47 1.2 ad #include <sys/param.h>
48 1.2 ad #include <sys/buf.h>
49 1.2 ad #include <sys/conf.h>
50 1.2 ad #include <sys/device.h>
51 1.2 ad #include <sys/systm.h>
52 1.2 ad
53 1.2 ad #include <machine/locore.h>
54 1.2 ad
55 1.2 ad #include <dev/scsipi/scsi_all.h>
56 1.2 ad #include <dev/scsipi/scsi_message.h>
57 1.2 ad #include <dev/scsipi/scsipi_all.h>
58 1.2 ad #include <dev/scsipi/scsipi_disk.h>
59 1.2 ad #include <dev/scsipi/scsiconf.h>
60 1.2 ad
61 1.2 ad /* old 4.4BSD/pmax scsi drivers */
62 1.2 ad #include <pmax/ibus/siireg.h> /* device registers */
63 1.2 ad #include <pmax/ibus/siivar.h> /* softc and prototypes */
64 1.2 ad
65 1.2 ad #include <pmax/pmax/machdep.h> /* prom_scsiid prototype */
66 1.2 ad
67 1.2 ad /* XXX not in dev/scsipi/scsi_message.h */
68 1.2 ad #define MSG_EXT_MODIFY_DATA_PTR 0x00
69 1.2 ad
70 1.2 ad extern struct cfdriver sii_cd;
71 1.2 ad
72 1.2 ad /*
73 1.2 ad * MACROS for timing out spin loops.
74 1.2 ad *
75 1.2 ad * Wait until expression is true.
76 1.2 ad *
77 1.2 ad * Control register bits can change at any time so when the CPU
78 1.2 ad * reads a register, the bits might change and
79 1.2 ad * invalidate the setup and hold times for the CPU.
80 1.2 ad * This macro reads the register twice to be sure the value is stable.
81 1.2 ad *
82 1.2 ad * args: var - variable to save control register contents
83 1.2 ad * reg - control register to read
84 1.2 ad * expr - expression to spin on
85 1.2 ad * spincount - maximum number of times through the loop
86 1.2 ad * cntr - variable for number of tries
87 1.2 ad */
88 1.2 ad #define SII_WAIT_UNTIL(var, reg, expr, spincount, cntr) { \
89 1.2 ad u_int tmp = reg; \
90 1.2 ad for (cntr = 0; cntr < spincount; cntr++) { \
91 1.2 ad while (tmp != (var = reg)) \
92 1.2 ad tmp = var; \
93 1.2 ad if (expr) \
94 1.2 ad break; \
95 1.2 ad if (cntr >= 100) \
96 1.2 ad DELAY(100); \
97 1.2 ad } \
98 1.2 ad }
99 1.2 ad
100 1.2 ad #ifdef DEBUG
101 1.2 ad int sii_debug = 1;
102 1.2 ad int sii_debug_cmd;
103 1.2 ad int sii_debug_bn;
104 1.2 ad int sii_debug_sz;
105 1.2 ad #define NLOG 16
106 1.2 ad struct sii_log {
107 1.2 ad u_short cstat;
108 1.2 ad u_short dstat;
109 1.2 ad u_short comm;
110 1.2 ad u_short msg;
111 1.2 ad int rlen;
112 1.2 ad int dlen;
113 1.2 ad int target;
114 1.2 ad } sii_log[NLOG], *sii_logp = sii_log;
115 1.2 ad #endif
116 1.2 ad
117 1.2 ad static u_char sii_buf[256]; /* used for extended messages */
118 1.2 ad
119 1.2 ad #define NORESET 0
120 1.2 ad #define RESET 1
121 1.2 ad #define NOWAIT 0
122 1.2 ad #define WAIT 1
123 1.2 ad
124 1.2 ad
125 1.2 ad /*
126 1.2 ad * Define a safe address in the SCSI buffer for doing status & message DMA
127 1.2 ad * XXX why not add another field to softc?
128 1.2 ad */
129 1.2 ad #define SII_BUF_ADDR(sc) ((sc)->sc_buf + SII_MAX_DMA_XFER_LENGTH * 14)
130 1.2 ad
131 1.2 ad /*
132 1.2 ad * Forward references
133 1.2 ad */
134 1.2 ad
135 1.2 ad static void sii_Reset __P((struct siisoftc *sc, int resetbus));
136 1.2 ad static void sii_StartCmd __P((struct siisoftc *sc, int target));
137 1.2 ad static void sii_CmdDone __P((struct siisoftc *sc, int target, int error));
138 1.2 ad static void sii_DoIntr __P((struct siisoftc *sc, u_int dstat));
139 1.2 ad static void sii_StateChg __P((struct siisoftc *sc, u_int cstat));
140 1.2 ad static int sii_GetByte __P((SIIRegs *regs, int phase, int ack));
141 1.2 ad static void sii_DoSync __P((SIIRegs *regs, State *state));
142 1.2 ad static void sii_StartDMA __P((SIIRegs *regs, int phase, u_short *dmaAddr,
143 1.2 ad int size));
144 1.2 ad
145 1.2 ad #ifdef DEBUG
146 1.2 ad static void sii_DumpLog __P((void));
147 1.2 ad #endif
148 1.2 ad
149 1.2 ad
150 1.2 ad /*
151 1.2 ad * Match driver based on name
152 1.2 ad */
153 1.2 ad void
154 1.2 ad siiattach(sc)
155 1.2 ad struct siisoftc *sc;
156 1.2 ad {
157 1.2 ad int i;
158 1.2 ad
159 1.2 ad sc->sc_target = -1; /* no command active */
160 1.2 ad
161 1.2 ad /*
162 1.2 ad * Give each target its own DMA buffer region.
163 1.2 ad * Make it big enough for 2 max transfers so we can ping pong buffers
164 1.2 ad * while we copy the data.
165 1.2 ad */
166 1.2 ad for (i = 0; i < SII_NCMD; i++) {
167 1.2 ad sc->sc_st[i].dmaAddr[0] = (u_short *)
168 1.2 ad sc->sc_buf + 2 * SII_MAX_DMA_XFER_LENGTH * i;
169 1.2 ad sc->sc_st[i].dmaAddr[1] = sc->sc_st[i].dmaAddr[0] +
170 1.2 ad SII_MAX_DMA_XFER_LENGTH;
171 1.2 ad }
172 1.2 ad
173 1.2 ad sii_Reset(sc, RESET);
174 1.2 ad printf(": target %d\n", sc->sc_regs->id & SII_IDMSK);
175 1.2 ad
176 1.2 ad sc->sc_adapter.adapt_dev = &sc->sc_dev;
177 1.2 ad sc->sc_adapter.adapt_nchannels = 1;
178 1.2 ad sc->sc_adapter.adapt_openings = 7;
179 1.2 ad sc->sc_adapter.adapt_max_periph = 1;
180 1.2 ad sc->sc_adapter.adapt_ioctl = NULL;
181 1.2 ad sc->sc_adapter.adapt_minphys = minphys;
182 1.2 ad sc->sc_adapter.adapt_request = sii_scsi_request;
183 1.2 ad
184 1.2 ad sc->sc_channel.chan_adapter = &sc->sc_adapter;
185 1.2 ad sc->sc_channel.chan_bustype = &scsi_bustype;
186 1.2 ad sc->sc_channel.chan_channel = 0;
187 1.2 ad sc->sc_channel.chan_ntargets = 8;
188 1.2 ad sc->sc_channel.chan_nluns = 8;
189 1.2 ad sc->sc_channel.chan_id = sc->sc_regs->id & SII_IDMSK;
190 1.2 ad
191 1.2 ad
192 1.2 ad /*
193 1.2 ad * Now try to attach all the sub-devices
194 1.2 ad */
195 1.2 ad config_found(&sc->sc_dev, &sc->sc_channel, scsiprint);
196 1.2 ad }
197 1.2 ad
198 1.2 ad /*
199 1.2 ad * Start activity on a SCSI device.
200 1.2 ad * We maintain information on each device separately since devices can
201 1.2 ad * connect/disconnect during an operation.
202 1.2 ad */
203 1.2 ad
204 1.2 ad void
205 1.2 ad sii_scsi_request(chan, req, arg)
206 1.2 ad struct scsipi_channel *chan;
207 1.2 ad scsipi_adapter_req_t req;
208 1.2 ad void *arg;
209 1.2 ad {
210 1.2 ad struct scsipi_xfer *xs;
211 1.2 ad struct scsipi_periph *periph;
212 1.2 ad struct siisoftc *sc = (void *)chan->chan_adapter->adapt_dev;
213 1.2 ad int target;
214 1.2 ad int s;
215 1.2 ad int count;
216 1.2 ad
217 1.2 ad switch (req) {
218 1.2 ad case ADAPTER_REQ_RUN_XFER:
219 1.2 ad xs = arg;
220 1.2 ad periph = xs->xs_periph;
221 1.2 ad target = periph->periph_target;
222 1.2 ad s = splbio();
223 1.2 ad if (sc->sc_cmd[target]) {
224 1.2 ad splx(s);
225 1.2 ad xs->error = XS_RESOURCE_SHORTAGE;
226 1.2 ad scsipi_done(xs);
227 1.2 ad printf("[busy at start]\n");
228 1.2 ad return;
229 1.2 ad }
230 1.2 ad /*
231 1.2 ad * Build a ScsiCmd for this command and start it.
232 1.2 ad */
233 1.2 ad sc->sc_xs[target] = xs;
234 1.2 ad sc->sc_cmd[target] = &sc->sc_cmd_fake[target]; /* XXX */
235 1.2 ad sc->sc_cmd[target]->unit = 0;
236 1.2 ad sc->sc_cmd[target]->flags = 0;
237 1.2 ad sc->sc_cmd[target]->buflen = xs->datalen;
238 1.2 ad sc->sc_cmd[target]->buf = xs->data;
239 1.2 ad sc->sc_cmd[target]->cmdlen = xs->cmdlen;
240 1.2 ad sc->sc_cmd[target]->cmd = (u_char *)xs->cmd;
241 1.2 ad sc->sc_cmd[target]->lun = xs->xs_periph->periph_lun;
242 1.2 ad sii_StartCmd(sc, target);
243 1.2 ad splx(s);
244 1.2 ad if ((xs->xs_control & XS_CTL_POLL) == 0)
245 1.2 ad return;
246 1.2 ad count = xs->timeout;
247 1.2 ad while (count) {
248 1.2 ad if ((xs->xs_status & XS_STS_DONE) != 0)
249 1.2 ad return;
250 1.2 ad siiintr(sc);
251 1.2 ad /* XXX schedule another command? */
252 1.2 ad DELAY(1000);
253 1.2 ad --count;
254 1.2 ad }
255 1.2 ad xs->error = XS_TIMEOUT;
256 1.2 ad scsipi_done(xs);
257 1.2 ad return;
258 1.2 ad case ADAPTER_REQ_GROW_RESOURCES:
259 1.2 ad /* XXX Not supported. */
260 1.2 ad return;
261 1.2 ad
262 1.2 ad case ADAPTER_REQ_SET_XFER_MODE:
263 1.2 ad /* XXX Not supported. */
264 1.2 ad return;
265 1.2 ad }
266 1.2 ad }
267 1.2 ad
268 1.2 ad /*
269 1.2 ad * Check to see if any SII chips have pending interrupts
270 1.2 ad * and process as appropriate.
271 1.2 ad */
272 1.2 ad int
273 1.2 ad siiintr(xxxsc)
274 1.2 ad void *xxxsc;
275 1.2 ad {
276 1.2 ad struct siisoftc *sc = xxxsc;
277 1.2 ad u_int dstat;
278 1.2 ad
279 1.2 ad /*
280 1.2 ad * Find which controller caused the interrupt.
281 1.2 ad */
282 1.2 ad dstat = sc->sc_regs->dstat;
283 1.2 ad if (dstat & (SII_CI | SII_DI)) {
284 1.2 ad sii_DoIntr(sc, dstat);
285 1.2 ad return (0); /* XXX */
286 1.2 ad }
287 1.2 ad
288 1.2 ad return (1); /* XXX spurious interrupt? */
289 1.2 ad }
290 1.2 ad
291 1.2 ad /*
292 1.2 ad * Reset the SII chip and do a SCSI reset if 'reset' is true.
293 1.2 ad * NOTE: if !cold && reset, should probably probe for devices
294 1.2 ad * since a SCSI bus reset will set UNIT_ATTENTION.
295 1.2 ad */
296 1.2 ad static void
297 1.2 ad sii_Reset(sc, reset)
298 1.2 ad struct siisoftc* sc;
299 1.2 ad int reset; /* TRUE => reset SCSI bus */
300 1.2 ad {
301 1.2 ad SIIRegs *regs = sc->sc_regs;
302 1.2 ad
303 1.2 ad #ifdef DEBUG
304 1.2 ad if (sii_debug > 1)
305 1.2 ad printf("sii: RESET\n");
306 1.2 ad #endif
307 1.2 ad /*
308 1.2 ad * Reset the SII chip.
309 1.2 ad */
310 1.2 ad regs->comm = SII_CHRESET;
311 1.2 ad /*
312 1.2 ad * Set arbitrated bus mode.
313 1.2 ad */
314 1.2 ad regs->csr = SII_HPM;
315 1.2 ad /*
316 1.2 ad * Set host adapter ID (from PROM sciiidN variable).
317 1.2 ad */
318 1.2 ad /* XXX device_unit() abuse */
319 1.2 ad regs->id = SII_ID_IO | prom_scsiid(device_unit(&sc->sc_dev));
320 1.2 ad /*
321 1.2 ad * Enable SII to drive the SCSI bus.
322 1.2 ad */
323 1.2 ad regs->dictrl = SII_PRE;
324 1.2 ad regs->dmctrl = 0;
325 1.2 ad
326 1.2 ad if (reset) {
327 1.2 ad int i;
328 1.2 ad
329 1.2 ad /*
330 1.2 ad * Assert SCSI bus reset for at least 25 Usec to clear the
331 1.2 ad * world. SII_DO_RST is self clearing.
332 1.2 ad * Delay 250 ms before doing any commands.
333 1.2 ad */
334 1.2 ad regs->comm = SII_DO_RST;
335 1.2 ad wbflush();
336 1.2 ad DELAY(250000);
337 1.2 ad
338 1.2 ad /* rearbitrate synchronous offset */
339 1.2 ad for (i = 0; i < SII_NCMD; i++)
340 1.2 ad sc->sc_st[i].dmaReqAck = 0;
341 1.2 ad }
342 1.2 ad
343 1.2 ad /*
344 1.2 ad * Clear any pending interrupts from the reset.
345 1.2 ad */
346 1.2 ad regs->cstat = regs->cstat;
347 1.2 ad regs->dstat = regs->dstat;
348 1.2 ad /*
349 1.2 ad * Set up SII for arbitrated bus mode, SCSI parity checking,
350 1.2 ad * Reselect Enable, and Interrupt Enable.
351 1.2 ad */
352 1.2 ad regs->csr = SII_HPM | SII_RSE | SII_PCE | SII_IE;
353 1.2 ad wbflush();
354 1.2 ad }
355 1.2 ad
356 1.2 ad /*
357 1.2 ad * Start a SCSI command by sending the cmd data
358 1.2 ad * to a SCSI controller via the SII.
359 1.2 ad * Call the device done proceedure if it can't be started.
360 1.2 ad * NOTE: we should be called with interrupts disabled.
361 1.2 ad */
362 1.2 ad static void
363 1.2 ad sii_StartCmd(sc, target)
364 1.2 ad struct siisoftc *sc; /* which SII to use */
365 1.2 ad int target; /* which command to start */
366 1.2 ad {
367 1.2 ad SIIRegs *regs;
368 1.2 ad ScsiCmd *scsicmd;
369 1.2 ad State *state;
370 1.2 ad u_int status;
371 1.2 ad int error, retval;
372 1.2 ad
373 1.2 ad /* if another command is currently in progress, just wait */
374 1.2 ad if (sc->sc_target >= 0)
375 1.2 ad return;
376 1.2 ad
377 1.2 ad /* initialize state information for this command */
378 1.2 ad scsicmd = sc->sc_cmd[target];
379 1.2 ad state = &sc->sc_st[target];
380 1.2 ad state->flags = FIRST_DMA;
381 1.2 ad state->prevComm = 0;
382 1.2 ad state->dmalen = 0;
383 1.2 ad state->dmaCurPhase = -1;
384 1.2 ad state->dmaPrevPhase = -1;
385 1.2 ad state->dmaBufIndex = 0;
386 1.2 ad state->cmd = scsicmd->cmd;
387 1.2 ad state->cmdlen = scsicmd->cmdlen;
388 1.2 ad if ((state->buflen = scsicmd->buflen) == 0) {
389 1.2 ad state->dmaDataPhase = -1; /* illegal phase. shouldn't happen */
390 1.2 ad state->buf = (char *)0;
391 1.2 ad } else {
392 1.2 ad state->buf = scsicmd->buf;
393 1.2 ad }
394 1.2 ad
395 1.2 ad #ifdef DEBUG
396 1.2 ad if (sii_debug > 1) {
397 1.2 ad printf("sii_StartCmd: %s target %d cmd 0x%x addr %p size %d DMA %d\n",
398 1.2 ad sc->sc_dev.dv_xname,
399 1.2 ad target, scsicmd->cmd[0], scsicmd->buf, scsicmd->buflen,
400 1.2 ad state->dmaDataPhase);
401 1.2 ad }
402 1.2 ad sii_debug_cmd = scsicmd->cmd[0];
403 1.2 ad if (scsicmd->cmd[0] == READ_10 ||
404 1.2 ad scsicmd->cmd[0] == WRITE_10) {
405 1.2 ad sii_debug_bn = (scsicmd->cmd[2] << 24) |
406 1.2 ad (scsicmd->cmd[3] << 16) |
407 1.2 ad (scsicmd->cmd[4] << 8) |
408 1.2 ad scsicmd->cmd[5];
409 1.2 ad sii_debug_sz = (scsicmd->cmd[7] << 8) | scsicmd->cmd[8];
410 1.2 ad } else {
411 1.2 ad sii_debug_bn = 0;
412 1.2 ad sii_debug_sz = 0;
413 1.2 ad }
414 1.2 ad #endif
415 1.2 ad
416 1.2 ad /* try to select the target */
417 1.2 ad regs = sc->sc_regs;
418 1.2 ad
419 1.2 ad /*
420 1.2 ad * Another device may have selected us; in which case,
421 1.2 ad * this command will be restarted later.
422 1.2 ad */
423 1.2 ad if ((status = regs->dstat) & (SII_CI | SII_DI)) {
424 1.2 ad sii_DoIntr(sc, status);
425 1.2 ad return;
426 1.2 ad }
427 1.2 ad
428 1.2 ad sc->sc_target = target;
429 1.2 ad #if 0
430 1.2 ad /* seem to have problems with synchronous transfers */
431 1.2 ad if (scsicmd->flags & SCSICMD_USE_SYNC) {
432 1.2 ad printf("sii_StartCmd: doing extended msg\n"); /* XXX */
433 1.2 ad /*
434 1.2 ad * Setup to send both the identify message and the synchronous
435 1.2 ad * data transfer request.
436 1.2 ad */
437 1.2 ad sii_buf[0] = MSG_IDENTIFYFLAG | MSG_IDENTIFY_DISCFLAG;
438 1.2 ad sii_buf[1] = MSG_EXTENDED;
439 1.2 ad sii_buf[2] = MSG_EXT_SDTR_LEN;
440 1.2 ad sii_buf[3] = MSG_EXT_SDTR;
441 1.2 ad sii_buf[4] = 0;
442 1.2 ad sii_buf[5] = 3; /* maximum SII chip supports */
443 1.2 ad
444 1.2 ad state->dmaCurPhase = SII_MSG_OUT_PHASE,
445 1.2 ad state->dmalen = 6;
446 1.2 ad sc->sii_copytobuf((u_short *)sii_buf,
447 1.2 ad (volatile u_short *)SII_BUF_ADDR(sc), 6);
448 1.2 ad regs->slcsr = target;
449 1.2 ad regs->dmctrl = state->dmaReqAck;
450 1.2 ad regs->dmaddrl = (u_short)(SII_BUF_ADDR(sc) >> 1);
451 1.2 ad regs->dmaddrh = (u_short)(SII_BUF_ADDR(sc) >> 17) & 03;
452 1.2 ad regs->dmlotc = 6;
453 1.2 ad regs->comm = SII_DMA | SII_INXFER | SII_SELECT | SII_ATN |
454 1.2 ad SII_CON | SII_MSG_OUT_PHASE;
455 1.2 ad } else
456 1.2 ad #endif
457 1.2 ad {
458 1.2 ad /* do a chained, select with ATN and programmed I/O command */
459 1.2 ad regs->data = MSG_IDENTIFYFLAG | MSG_IDENTIFY_DISCFLAG |
460 1.2 ad scsicmd->lun;
461 1.2 ad regs->slcsr = target;
462 1.2 ad regs->dmctrl = state->dmaReqAck;
463 1.2 ad regs->comm = SII_INXFER | SII_SELECT | SII_ATN | SII_CON |
464 1.2 ad SII_MSG_OUT_PHASE;
465 1.2 ad }
466 1.2 ad wbflush();
467 1.2 ad
468 1.2 ad /*
469 1.2 ad * Wait for something to happen
470 1.2 ad * (should happen soon or we would use interrupts).
471 1.2 ad */
472 1.2 ad SII_WAIT_UNTIL(status, regs->cstat, status & (SII_CI | SII_DI),
473 1.2 ad SII_WAIT_COUNT/4, retval);
474 1.2 ad
475 1.2 ad /* check to see if we are connected OK */
476 1.2 ad if ((status & (SII_RST | SII_SCH | SII_STATE_MSK)) ==
477 1.2 ad (SII_SCH | SII_CON)) {
478 1.2 ad regs->cstat = status;
479 1.2 ad wbflush();
480 1.2 ad
481 1.2 ad #ifdef DEBUG
482 1.2 ad sii_logp->target = target;
483 1.2 ad sii_logp->cstat = status;
484 1.2 ad sii_logp->dstat = 0;
485 1.2 ad sii_logp->comm = regs->comm;
486 1.2 ad sii_logp->msg = -1;
487 1.2 ad sii_logp->rlen = state->buflen;
488 1.2 ad sii_logp->dlen = state->dmalen;
489 1.2 ad if (++sii_logp >= &sii_log[NLOG])
490 1.2 ad sii_logp = sii_log;
491 1.2 ad #endif
492 1.2 ad
493 1.2 ad /* wait a short time for command phase */
494 1.2 ad SII_WAIT_UNTIL(status, regs->dstat, status & SII_MIS,
495 1.2 ad SII_WAIT_COUNT, retval);
496 1.2 ad #ifdef DEBUG
497 1.2 ad if (sii_debug > 2)
498 1.2 ad printf("sii_StartCmd: ds %x cnt %d\n", status, retval);
499 1.2 ad #endif
500 1.2 ad if ((status & (SII_CI | SII_MIS | SII_PHASE_MSK)) !=
501 1.2 ad (SII_MIS | SII_CMD_PHASE)) {
502 1.2 ad printf("sii_StartCmd: timeout cs %x ds %x cnt %d\n",
503 1.2 ad regs->cstat, status, retval); /* XXX */
504 1.2 ad /* process interrupt or continue until it happens */
505 1.2 ad if (status & (SII_CI | SII_DI))
506 1.2 ad sii_DoIntr(sc, status);
507 1.2 ad return;
508 1.2 ad }
509 1.2 ad regs->dstat = SII_DNE; /* clear Msg Out DMA done */
510 1.2 ad
511 1.2 ad /* send command data */
512 1.2 ad sc->sii_copytobuf((u_short *)state->cmd,
513 1.2 ad (volatile u_short *)state->dmaAddr[0], state->cmdlen);
514 1.2 ad sii_StartDMA(regs, state->dmaCurPhase = SII_CMD_PHASE,
515 1.2 ad state->dmaAddr[0], state->dmalen = scsicmd->cmdlen);
516 1.2 ad
517 1.2 ad /* wait a little while for DMA to finish */
518 1.2 ad SII_WAIT_UNTIL(status, regs->dstat, status & (SII_CI | SII_DI),
519 1.2 ad SII_WAIT_COUNT, retval);
520 1.2 ad #ifdef DEBUG
521 1.2 ad if (sii_debug > 2)
522 1.2 ad printf("sii_StartCmd: ds %x, cnt %d\n", status, retval);
523 1.2 ad #endif
524 1.2 ad if (status & (SII_CI | SII_DI))
525 1.2 ad sii_DoIntr(sc, status);
526 1.2 ad #ifdef DEBUG
527 1.2 ad if (sii_debug > 2)
528 1.2 ad printf("sii_StartCmd: DONE ds %x\n", regs->dstat);
529 1.2 ad #endif
530 1.2 ad return;
531 1.2 ad }
532 1.2 ad
533 1.2 ad /*
534 1.2 ad * Another device may have selected us; in which case,
535 1.2 ad * this command will be restarted later.
536 1.2 ad */
537 1.2 ad if (status & (SII_CI | SII_DI)) {
538 1.2 ad sii_DoIntr(sc, regs->dstat);
539 1.2 ad return;
540 1.2 ad }
541 1.2 ad
542 1.2 ad /*
543 1.2 ad * Disconnect if selection command still in progress.
544 1.2 ad */
545 1.2 ad if (status & SII_SIP) {
546 1.2 ad error = ENXIO; /* device didn't respond */
547 1.2 ad regs->comm = SII_DISCON;
548 1.2 ad wbflush();
549 1.2 ad SII_WAIT_UNTIL(status, regs->cstat,
550 1.2 ad !(status & (SII_CON | SII_SIP)),
551 1.2 ad SII_WAIT_COUNT, retval);
552 1.2 ad } else
553 1.2 ad error = EBUSY; /* couldn't get the bus */
554 1.2 ad #ifdef DEBUG
555 1.2 ad if (sii_debug > 1)
556 1.2 ad printf("sii_StartCmd: Couldn't select target %d error %d\n",
557 1.2 ad target, error);
558 1.2 ad #endif
559 1.2 ad sc->sc_target = -1;
560 1.2 ad regs->cstat = 0xffff;
561 1.2 ad regs->dstat = 0xffff;
562 1.2 ad regs->comm = 0;
563 1.2 ad wbflush();
564 1.2 ad sii_CmdDone(sc, target, error);
565 1.2 ad }
566 1.2 ad
567 1.2 ad /*
568 1.2 ad * Process interrupt conditions.
569 1.2 ad */
570 1.2 ad static void
571 1.2 ad sii_DoIntr(sc, dstat)
572 1.2 ad struct siisoftc *sc;
573 1.2 ad u_int dstat;
574 1.2 ad {
575 1.2 ad SIIRegs *regs = sc->sc_regs;
576 1.2 ad State *state;
577 1.2 ad u_int cstat;
578 1.2 ad int i, msg;
579 1.2 ad u_int comm;
580 1.2 ad
581 1.2 ad again:
582 1.2 ad comm = regs->comm;
583 1.2 ad
584 1.2 ad #ifdef DEBUG
585 1.2 ad if (sii_debug > 3)
586 1.2 ad printf("sii_DoIntr: cs %x, ds %x cm %x ",
587 1.2 ad regs->cstat, dstat, comm);
588 1.2 ad sii_logp->target = sc->sc_target;
589 1.2 ad sii_logp->cstat = regs->cstat;
590 1.2 ad sii_logp->dstat = dstat;
591 1.2 ad sii_logp->comm = comm;
592 1.2 ad sii_logp->msg = -1;
593 1.2 ad if (sc->sc_target >= 0) {
594 1.2 ad sii_logp->rlen = sc->sc_st[sc->sc_target].buflen;
595 1.2 ad sii_logp->dlen = sc->sc_st[sc->sc_target].dmalen;
596 1.2 ad } else {
597 1.2 ad sii_logp->rlen = 0;
598 1.2 ad sii_logp->dlen = 0;
599 1.2 ad }
600 1.2 ad if (++sii_logp >= &sii_log[NLOG])
601 1.2 ad sii_logp = sii_log;
602 1.2 ad #endif
603 1.2 ad
604 1.2 ad regs->dstat = dstat; /* acknowledge everything */
605 1.2 ad wbflush();
606 1.2 ad
607 1.2 ad if (dstat & SII_CI) {
608 1.2 ad /* deglitch cstat register */
609 1.2 ad msg = regs->cstat;
610 1.2 ad while (msg != (cstat = regs->cstat))
611 1.2 ad msg = cstat;
612 1.2 ad regs->cstat = cstat; /* acknowledge everything */
613 1.2 ad wbflush();
614 1.2 ad #ifdef DEBUG
615 1.2 ad if (sii_logp > sii_log)
616 1.2 ad sii_logp[-1].cstat = cstat;
617 1.2 ad else
618 1.2 ad sii_log[NLOG - 1].cstat = cstat;
619 1.2 ad #endif
620 1.2 ad
621 1.2 ad /* check for a BUS RESET */
622 1.2 ad if (cstat & SII_RST) {
623 1.2 ad printf("%s: SCSI bus reset!!\n", sc->sc_dev.dv_xname);
624 1.2 ad /* need to flush disconnected commands */
625 1.2 ad for (i = 0; i < SII_NCMD; i++) {
626 1.2 ad if (!sc->sc_cmd[i])
627 1.2 ad continue;
628 1.2 ad sii_CmdDone(sc, i, EIO);
629 1.2 ad }
630 1.2 ad /* rearbitrate synchronous offset */
631 1.2 ad for (i = 0; i < SII_NCMD; i++)
632 1.2 ad sc->sc_st[i].dmaReqAck = 0;
633 1.2 ad sc->sc_target = -1;
634 1.2 ad return;
635 1.2 ad }
636 1.2 ad
637 1.2 ad #ifdef notdef
638 1.2 ad /*
639 1.2 ad * Check for a BUS ERROR.
640 1.2 ad * According to DEC, this feature doesn't really work
641 1.2 ad * and to just clear the bit if it's set.
642 1.2 ad */
643 1.2 ad if (cstat & SII_BER) {
644 1.2 ad regs->cstat = SII_BER;
645 1.2 ad wbflush();
646 1.2 ad }
647 1.2 ad #endif
648 1.2 ad
649 1.2 ad /* check for state change */
650 1.2 ad if (cstat & SII_SCH) {
651 1.2 ad sii_StateChg(sc, cstat);
652 1.2 ad comm = regs->comm;
653 1.2 ad }
654 1.2 ad }
655 1.2 ad
656 1.2 ad /* check for DMA completion */
657 1.2 ad if (dstat & SII_DNE) {
658 1.2 ad u_short *dma;
659 1.2 ad char *buf;
660 1.2 ad
661 1.2 ad /*
662 1.2 ad * There is a race condition with SII_SCH. There is a short
663 1.2 ad * window between the time a SII_SCH is seen after a disconnect
664 1.2 ad * and when the SII_SCH is cleared. A reselect can happen
665 1.2 ad * in this window and we will clear the SII_SCH without
666 1.2 ad * processing the reconnect.
667 1.2 ad */
668 1.2 ad if (sc->sc_target < 0) {
669 1.2 ad cstat = regs->cstat;
670 1.2 ad printf("%s: target %d DNE?? dev %d,%d cs %x\n",
671 1.2 ad sc->sc_dev.dv_xname, sc->sc_target,
672 1.2 ad regs->slcsr, regs->destat,
673 1.2 ad cstat); /* XXX */
674 1.2 ad if (cstat & SII_DST) {
675 1.2 ad sc->sc_target = regs->destat;
676 1.2 ad state = &sc->sc_st[sc->sc_target];
677 1.2 ad state->prevComm = 0;
678 1.2 ad } else
679 1.2 ad panic("sc_target 1");
680 1.2 ad }
681 1.2 ad state = &sc->sc_st[sc->sc_target];
682 1.2 ad /* check for a PARITY ERROR */
683 1.2 ad if (dstat & SII_IPE) {
684 1.2 ad state->flags |= PARITY_ERR;
685 1.2 ad printf("%s: Parity error!!\n", sc->sc_dev.dv_xname);
686 1.2 ad goto abort;
687 1.2 ad }
688 1.2 ad /* dmalen = amount left to transfer, i = amount transfered */
689 1.2 ad i = state->dmalen;
690 1.2 ad state->dmalen = 0;
691 1.2 ad state->dmaCurPhase = -1;
692 1.2 ad #ifdef DEBUG
693 1.2 ad if (sii_debug > 4) {
694 1.2 ad printf("DNE: amt %d ", i);
695 1.2 ad if (!(dstat & SII_TCZ))
696 1.2 ad printf("no TCZ?? (%d) ", regs->dmlotc);
697 1.2 ad } else if (!(dstat & SII_TCZ)) {
698 1.2 ad printf("%s: device %d: no TCZ?? (%d)\n",
699 1.2 ad sc->sc_dev.dv_xname, sc->sc_target, regs->dmlotc);
700 1.2 ad sii_DumpLog(); /* XXX */
701 1.2 ad }
702 1.2 ad #endif
703 1.2 ad switch (comm & SII_PHASE_MSK) {
704 1.2 ad case SII_CMD_PHASE:
705 1.2 ad state->cmdlen -= i;
706 1.2 ad break;
707 1.2 ad
708 1.2 ad case SII_DATA_IN_PHASE:
709 1.2 ad /* check for more data for the same phase */
710 1.2 ad dma = state->dmaAddr[state->dmaBufIndex];
711 1.2 ad buf = state->buf;
712 1.2 ad state->buf += i;
713 1.2 ad state->buflen -= i;
714 1.2 ad if (state->buflen > 0 && !(dstat & SII_MIS)) {
715 1.2 ad int len;
716 1.2 ad
717 1.2 ad /* start reading next chunk */
718 1.2 ad len = state->buflen;
719 1.2 ad if (len > SII_MAX_DMA_XFER_LENGTH)
720 1.2 ad len = SII_MAX_DMA_XFER_LENGTH;
721 1.2 ad state->dmaBufIndex = !state->dmaBufIndex;
722 1.2 ad sii_StartDMA(regs,
723 1.2 ad state->dmaCurPhase = SII_DATA_IN_PHASE,
724 1.2 ad state->dmaAddr[state->dmaBufIndex],
725 1.2 ad state->dmaCnt = state->dmalen = len);
726 1.2 ad dstat &= ~(SII_IBF | SII_TBE);
727 1.2 ad }
728 1.2 ad /* copy in the data */
729 1.2 ad sc->sii_copyfrombuf((volatile u_short *)dma, buf, i);
730 1.2 ad break;
731 1.2 ad
732 1.2 ad case SII_DATA_OUT_PHASE:
733 1.2 ad state->dmaBufIndex = !state->dmaBufIndex;
734 1.2 ad state->buf += i;
735 1.2 ad state->buflen -= i;
736 1.2 ad
737 1.2 ad /* check for more data for the same phase */
738 1.2 ad if (state->buflen <= 0 || (dstat & SII_MIS))
739 1.2 ad break;
740 1.2 ad
741 1.2 ad /* start next chunk */
742 1.2 ad i = state->buflen;
743 1.2 ad if (i > SII_MAX_DMA_XFER_LENGTH) {
744 1.2 ad sii_StartDMA(regs, state->dmaCurPhase =
745 1.2 ad SII_DATA_OUT_PHASE,
746 1.2 ad state->dmaAddr[state->dmaBufIndex],
747 1.2 ad state->dmaCnt = state->dmalen =
748 1.2 ad SII_MAX_DMA_XFER_LENGTH);
749 1.2 ad /* prepare for next chunk */
750 1.2 ad i -= SII_MAX_DMA_XFER_LENGTH;
751 1.2 ad if (i > SII_MAX_DMA_XFER_LENGTH)
752 1.2 ad i = SII_MAX_DMA_XFER_LENGTH;
753 1.2 ad sc->sii_copytobuf((u_short *)(state->buf +
754 1.2 ad SII_MAX_DMA_XFER_LENGTH),
755 1.2 ad (volatile u_short *)
756 1.2 ad state->dmaAddr[!state->dmaBufIndex], i);
757 1.2 ad } else {
758 1.2 ad sii_StartDMA(regs, state->dmaCurPhase =
759 1.2 ad SII_DATA_OUT_PHASE,
760 1.2 ad state->dmaAddr[state->dmaBufIndex],
761 1.2 ad state->dmaCnt = state->dmalen = i);
762 1.2 ad }
763 1.2 ad dstat &= ~(SII_IBF | SII_TBE);
764 1.2 ad }
765 1.2 ad }
766 1.2 ad
767 1.2 ad /* check for phase change or another MsgIn/Out */
768 1.2 ad if (dstat & (SII_MIS | SII_IBF | SII_TBE)) {
769 1.2 ad /*
770 1.2 ad * There is a race condition with SII_SCH. There is a short
771 1.2 ad * window between the time a SII_SCH is seen after a disconnect
772 1.2 ad * and when the SII_SCH is cleared. A reselect can happen
773 1.2 ad * in this window and we will clear the SII_SCH without
774 1.2 ad * processing the reconnect.
775 1.2 ad */
776 1.2 ad if (sc->sc_target < 0) {
777 1.2 ad cstat = regs->cstat;
778 1.2 ad printf("%s: target %d MIS?? dev %d,%d cs %x ds %x\n",
779 1.2 ad sc->sc_dev.dv_xname, sc->sc_target,
780 1.2 ad regs->slcsr, regs->destat,
781 1.2 ad cstat, dstat); /* XXX */
782 1.2 ad if (cstat & SII_DST) {
783 1.2 ad sc->sc_target = regs->destat;
784 1.2 ad state = &sc->sc_st[sc->sc_target];
785 1.2 ad state->prevComm = 0;
786 1.2 ad } else {
787 1.2 ad #ifdef DEBUG
788 1.2 ad sii_DumpLog();
789 1.2 ad #endif
790 1.2 ad panic("sc_target 2");
791 1.2 ad }
792 1.2 ad }
793 1.2 ad state = &sc->sc_st[sc->sc_target];
794 1.2 ad switch (dstat & SII_PHASE_MSK) {
795 1.2 ad case SII_CMD_PHASE:
796 1.2 ad if (state->dmaPrevPhase >= 0) {
797 1.2 ad /* restart DMA after disconnect/reconnect */
798 1.2 ad if (state->dmaPrevPhase != SII_CMD_PHASE) {
799 1.2 ad printf("%s: device %d: DMA reselect phase doesn't match\n",
800 1.2 ad sc->sc_dev.dv_xname, sc->sc_target);
801 1.2 ad goto abort;
802 1.2 ad }
803 1.2 ad state->dmaCurPhase = SII_CMD_PHASE;
804 1.2 ad state->dmaPrevPhase = -1;
805 1.2 ad regs->dmaddrl = state->dmaAddrL;
806 1.2 ad regs->dmaddrh = state->dmaAddrH;
807 1.2 ad regs->dmlotc = state->dmaCnt;
808 1.2 ad if (state->dmaCnt & 1)
809 1.2 ad regs->dmabyte = state->dmaByte;
810 1.2 ad regs->comm = SII_DMA | SII_INXFER |
811 1.2 ad (comm & SII_STATE_MSK) | SII_CMD_PHASE;
812 1.2 ad wbflush();
813 1.2 ad #ifdef DEBUG
814 1.2 ad if (sii_debug > 4)
815 1.2 ad printf("Cmd dcnt %d dadr %x ",
816 1.2 ad state->dmaCnt,
817 1.2 ad (state->dmaAddrH << 16) |
818 1.2 ad state->dmaAddrL);
819 1.2 ad #endif
820 1.2 ad } else {
821 1.2 ad /* send command data */
822 1.2 ad i = state->cmdlen;
823 1.2 ad if (i == 0) {
824 1.2 ad printf("%s: device %d: cmd count exceeded\n",
825 1.2 ad sc->sc_dev.dv_xname, sc->sc_target);
826 1.2 ad goto abort;
827 1.2 ad }
828 1.2 ad sc->sii_copytobuf((u_short *)state->cmd,
829 1.2 ad (volatile u_short *)state->dmaAddr[0],
830 1.2 ad i);
831 1.2 ad sii_StartDMA(regs, state->dmaCurPhase =
832 1.2 ad SII_CMD_PHASE, state->dmaAddr[0],
833 1.2 ad state->dmaCnt = state->dmalen = i);
834 1.2 ad }
835 1.2 ad /* wait a short time for XFER complete */
836 1.2 ad SII_WAIT_UNTIL(dstat, regs->dstat,
837 1.2 ad dstat & (SII_CI | SII_DI), SII_WAIT_COUNT, i);
838 1.2 ad if (dstat & (SII_CI | SII_DI)) {
839 1.2 ad #ifdef DEBUG
840 1.2 ad if (sii_debug > 4)
841 1.2 ad printf("cnt %d\n", i);
842 1.2 ad else if (sii_debug > 0)
843 1.2 ad printf("sii_DoIntr: cmd wait ds %x cnt %d\n",
844 1.2 ad dstat, i);
845 1.2 ad #endif
846 1.2 ad goto again;
847 1.2 ad }
848 1.2 ad break;
849 1.2 ad
850 1.2 ad case SII_DATA_IN_PHASE:
851 1.2 ad case SII_DATA_OUT_PHASE:
852 1.2 ad if (state->cmdlen > 0) {
853 1.2 ad printf("%s: device %d: cmd %x: command data not all sent (%d) 1\n",
854 1.2 ad sc->sc_dev.dv_xname, sc->sc_target,
855 1.2 ad sc->sc_cmd[sc->sc_target]->cmd[0],
856 1.2 ad state->cmdlen);
857 1.2 ad state->cmdlen = 0;
858 1.2 ad #ifdef DEBUG
859 1.2 ad sii_DumpLog();
860 1.2 ad #endif
861 1.2 ad }
862 1.2 ad if (state->dmaPrevPhase >= 0) {
863 1.2 ad /* restart DMA after disconnect/reconnect */
864 1.2 ad if (state->dmaPrevPhase !=
865 1.2 ad (dstat & SII_PHASE_MSK)) {
866 1.2 ad printf("%s: device %d: DMA reselect phase doesn't match\n",
867 1.2 ad sc->sc_dev.dv_xname, sc->sc_target);
868 1.2 ad goto abort;
869 1.2 ad }
870 1.2 ad state->dmaCurPhase = state->dmaPrevPhase;
871 1.2 ad state->dmaPrevPhase = -1;
872 1.2 ad regs->dmaddrl = state->dmaAddrL;
873 1.2 ad regs->dmaddrh = state->dmaAddrH;
874 1.2 ad regs->dmlotc = state->dmaCnt;
875 1.2 ad if (state->dmaCnt & 1)
876 1.2 ad regs->dmabyte = state->dmaByte;
877 1.2 ad regs->comm = SII_DMA | SII_INXFER |
878 1.2 ad (comm & SII_STATE_MSK) |
879 1.2 ad state->dmaCurPhase;
880 1.2 ad wbflush();
881 1.2 ad #ifdef DEBUG
882 1.2 ad if (sii_debug > 4)
883 1.2 ad printf("Data %d dcnt %d dadr %x ",
884 1.2 ad state->dmaDataPhase,
885 1.2 ad state->dmaCnt,
886 1.2 ad (state->dmaAddrH << 16) |
887 1.2 ad state->dmaAddrL);
888 1.2 ad #endif
889 1.2 ad break;
890 1.2 ad }
891 1.2 ad #ifdef DEBUG
892 1.2 ad if (sii_debug > 4) {
893 1.2 ad printf("Data %d ", state->dmaDataPhase);
894 1.2 ad if (sii_debug > 5)
895 1.2 ad printf("\n");
896 1.2 ad }
897 1.2 ad #endif
898 1.2 ad i = state->buflen;
899 1.2 ad if (i == 0) {
900 1.2 ad printf("%s: device %d: data count exceeded\n",
901 1.2 ad sc->sc_dev.dv_xname, sc->sc_target);
902 1.2 ad goto abort;
903 1.2 ad }
904 1.2 ad if (i > SII_MAX_DMA_XFER_LENGTH)
905 1.2 ad i = SII_MAX_DMA_XFER_LENGTH;
906 1.2 ad if ((dstat & SII_PHASE_MSK) == SII_DATA_IN_PHASE) {
907 1.2 ad sii_StartDMA(regs,
908 1.2 ad state->dmaCurPhase = SII_DATA_IN_PHASE,
909 1.2 ad state->dmaAddr[state->dmaBufIndex],
910 1.2 ad state->dmaCnt = state->dmalen = i);
911 1.2 ad break;
912 1.2 ad }
913 1.2 ad /* start first chunk */
914 1.2 ad if (state->flags & FIRST_DMA) {
915 1.2 ad state->flags &= ~FIRST_DMA;
916 1.2 ad sc->sii_copytobuf((u_short *)state->buf,
917 1.2 ad (volatile u_short *)
918 1.2 ad state->dmaAddr[state->dmaBufIndex], i);
919 1.2 ad }
920 1.2 ad sii_StartDMA(regs,
921 1.2 ad state->dmaCurPhase = SII_DATA_OUT_PHASE,
922 1.2 ad state->dmaAddr[state->dmaBufIndex],
923 1.2 ad state->dmaCnt = state->dmalen = i);
924 1.2 ad i = state->buflen - SII_MAX_DMA_XFER_LENGTH;
925 1.2 ad if (i > 0) {
926 1.2 ad /* prepare for next chunk */
927 1.2 ad if (i > SII_MAX_DMA_XFER_LENGTH)
928 1.2 ad i = SII_MAX_DMA_XFER_LENGTH;
929 1.2 ad sc->sii_copytobuf((u_short *)(state->buf +
930 1.2 ad SII_MAX_DMA_XFER_LENGTH),
931 1.2 ad (volatile u_short *)
932 1.2 ad state->dmaAddr[!state->dmaBufIndex], i);
933 1.2 ad }
934 1.2 ad break;
935 1.2 ad
936 1.2 ad case SII_STATUS_PHASE:
937 1.2 ad if (state->cmdlen > 0) {
938 1.2 ad printf("%s: device %d: cmd %x: command data not all sent (%d) 2\n",
939 1.2 ad sc->sc_dev.dv_xname, sc->sc_target,
940 1.2 ad sc->sc_cmd[sc->sc_target]->cmd[0],
941 1.2 ad state->cmdlen);
942 1.2 ad state->cmdlen = 0;
943 1.2 ad #ifdef DEBUG
944 1.2 ad sii_DumpLog();
945 1.2 ad #endif
946 1.2 ad }
947 1.2 ad
948 1.2 ad /* read amount transfered if DMA didn't finish */
949 1.2 ad if (state->dmalen > 0) {
950 1.2 ad i = state->dmalen - regs->dmlotc;
951 1.2 ad state->dmalen = 0;
952 1.2 ad state->dmaCurPhase = -1;
953 1.2 ad regs->dmlotc = 0;
954 1.2 ad regs->comm = comm &
955 1.2 ad (SII_STATE_MSK | SII_PHASE_MSK);
956 1.2 ad wbflush();
957 1.2 ad regs->dstat = SII_DNE;
958 1.2 ad wbflush();
959 1.2 ad #ifdef DEBUG
960 1.2 ad if (sii_debug > 4)
961 1.2 ad printf("DMA amt %d ", i);
962 1.2 ad #endif
963 1.2 ad switch (comm & SII_PHASE_MSK) {
964 1.2 ad case SII_DATA_IN_PHASE:
965 1.2 ad /* copy in the data */
966 1.2 ad sc->sii_copyfrombuf((volatile u_short*)
967 1.2 ad state->dmaAddr[state->dmaBufIndex],
968 1.2 ad state->buf, i);
969 1.2 ad
970 1.2 ad case SII_CMD_PHASE:
971 1.2 ad case SII_DATA_OUT_PHASE:
972 1.2 ad state->buflen -= i;
973 1.2 ad }
974 1.2 ad }
975 1.2 ad
976 1.2 ad /* read a one byte status message */
977 1.2 ad state->statusByte = msg =
978 1.2 ad sii_GetByte(regs, SII_STATUS_PHASE, 1);
979 1.2 ad if (msg < 0) {
980 1.2 ad dstat = regs->dstat;
981 1.2 ad goto again;
982 1.2 ad }
983 1.2 ad #ifdef DEBUG
984 1.2 ad if (sii_debug > 4)
985 1.2 ad printf("Status %x ", msg);
986 1.2 ad if (sii_logp > sii_log)
987 1.2 ad sii_logp[-1].msg = msg;
988 1.2 ad else
989 1.2 ad sii_log[NLOG - 1].msg = msg;
990 1.2 ad #endif
991 1.2 ad
992 1.2 ad /* do a quick wait for COMMAND_COMPLETE */
993 1.2 ad SII_WAIT_UNTIL(dstat, regs->dstat,
994 1.2 ad dstat & (SII_CI | SII_DI), SII_WAIT_COUNT, i);
995 1.2 ad if (dstat & (SII_CI | SII_DI)) {
996 1.2 ad #ifdef DEBUG
997 1.2 ad if (sii_debug > 4)
998 1.2 ad printf("cnt2 %d\n", i);
999 1.2 ad #endif
1000 1.2 ad goto again;
1001 1.2 ad }
1002 1.2 ad break;
1003 1.2 ad
1004 1.2 ad case SII_MSG_IN_PHASE:
1005 1.2 ad /*
1006 1.2 ad * Save DMA state if DMA didn't finish.
1007 1.2 ad * Be careful not to save state again after reconnect
1008 1.2 ad * and see RESTORE_POINTER message.
1009 1.2 ad * Note that the SII DMA address is not incremented
1010 1.2 ad * as DMA proceeds.
1011 1.2 ad */
1012 1.2 ad if (state->dmaCurPhase >= 0) {
1013 1.2 ad /* save DMA registers */
1014 1.2 ad state->dmaPrevPhase = state->dmaCurPhase;
1015 1.2 ad state->dmaCurPhase = -1;
1016 1.2 ad if (dstat & SII_OBB)
1017 1.2 ad state->dmaByte = regs->dmabyte;
1018 1.2 ad i = regs->dmlotc;
1019 1.2 ad if (i != 0)
1020 1.2 ad i = state->dmaCnt - i;
1021 1.2 ad /* note: no carry from dmaddrl to dmaddrh */
1022 1.2 ad state->dmaAddrL = regs->dmaddrl + i;
1023 1.2 ad state->dmaAddrH = regs->dmaddrh;
1024 1.2 ad state->dmaCnt = regs->dmlotc;
1025 1.2 ad if (state->dmaCnt == 0)
1026 1.2 ad state->dmaCnt = SII_MAX_DMA_XFER_LENGTH;
1027 1.2 ad regs->comm = comm &
1028 1.2 ad (SII_STATE_MSK | SII_PHASE_MSK);
1029 1.2 ad wbflush();
1030 1.2 ad regs->dstat = SII_DNE;
1031 1.2 ad wbflush();
1032 1.2 ad #ifdef DEBUG
1033 1.2 ad if (sii_debug > 4) {
1034 1.2 ad printf("SavP dcnt %d dadr %x ",
1035 1.2 ad state->dmaCnt,
1036 1.2 ad (state->dmaAddrH << 16) |
1037 1.2 ad state->dmaAddrL);
1038 1.2 ad if (((dstat & SII_OBB) != 0) ^
1039 1.2 ad (state->dmaCnt & 1))
1040 1.2 ad printf("OBB??? ");
1041 1.2 ad } else if (sii_debug > 0) {
1042 1.2 ad if (((dstat & SII_OBB) != 0) ^
1043 1.2 ad (state->dmaCnt & 1)) {
1044 1.2 ad printf("sii_DoIntr: OBB??? ds %x cnt %d\n",
1045 1.2 ad dstat, state->dmaCnt);
1046 1.2 ad sii_DumpLog();
1047 1.2 ad }
1048 1.2 ad }
1049 1.2 ad #endif
1050 1.2 ad }
1051 1.2 ad
1052 1.2 ad /* read a one byte message */
1053 1.2 ad msg = sii_GetByte(regs, SII_MSG_IN_PHASE, 0);
1054 1.2 ad if (msg < 0) {
1055 1.2 ad dstat = regs->dstat;
1056 1.2 ad goto again;
1057 1.2 ad }
1058 1.2 ad #ifdef DEBUG
1059 1.2 ad if (sii_debug > 4)
1060 1.2 ad printf("MsgIn %x ", msg);
1061 1.2 ad if (sii_logp > sii_log)
1062 1.2 ad sii_logp[-1].msg = msg;
1063 1.2 ad else
1064 1.2 ad sii_log[NLOG - 1].msg = msg;
1065 1.2 ad #endif
1066 1.2 ad
1067 1.2 ad /* process message */
1068 1.2 ad switch (msg) {
1069 1.2 ad case MSG_CMDCOMPLETE:
1070 1.2 ad /* acknowledge last byte */
1071 1.2 ad regs->comm = SII_INXFER | SII_MSG_IN_PHASE |
1072 1.2 ad (comm & SII_STATE_MSK);
1073 1.2 ad SII_WAIT_UNTIL(dstat, regs->dstat,
1074 1.2 ad dstat & SII_DNE, SII_WAIT_COUNT, i);
1075 1.2 ad regs->dstat = SII_DNE;
1076 1.2 ad wbflush();
1077 1.2 ad msg = sc->sc_target;
1078 1.2 ad sc->sc_target = -1;
1079 1.2 ad /*
1080 1.2 ad * Wait a short time for disconnect.
1081 1.2 ad * Don't be fooled if SII_BER happens first.
1082 1.2 ad * Note: a reselect may happen here.
1083 1.2 ad */
1084 1.2 ad SII_WAIT_UNTIL(cstat, regs->cstat,
1085 1.2 ad cstat & (SII_RST | SII_SCH),
1086 1.2 ad SII_WAIT_COUNT, i);
1087 1.2 ad if ((cstat & (SII_RST | SII_SCH |
1088 1.2 ad SII_STATE_MSK)) == SII_SCH) {
1089 1.2 ad regs->cstat = SII_SCH | SII_BER;
1090 1.2 ad regs->comm = 0;
1091 1.2 ad wbflush();
1092 1.2 ad /*
1093 1.2 ad * Double check that we didn't miss a
1094 1.2 ad * state change between seeing it and
1095 1.2 ad * clearing the SII_SCH bit.
1096 1.2 ad */
1097 1.2 ad i = regs->cstat;
1098 1.2 ad if (!(i & SII_SCH) &&
1099 1.2 ad (i & SII_STATE_MSK) !=
1100 1.2 ad (cstat & SII_STATE_MSK))
1101 1.2 ad sii_StateChg(sc, i);
1102 1.2 ad }
1103 1.2 ad #ifdef DEBUG
1104 1.2 ad if (sii_debug > 4)
1105 1.2 ad printf("cs %x\n", cstat);
1106 1.2 ad #endif
1107 1.2 ad sii_CmdDone(sc, msg, 0);
1108 1.2 ad break;
1109 1.2 ad
1110 1.2 ad case MSG_EXTENDED:
1111 1.2 ad /* acknowledge last byte */
1112 1.2 ad regs->comm = SII_INXFER | SII_MSG_IN_PHASE |
1113 1.2 ad (comm & SII_STATE_MSK);
1114 1.2 ad SII_WAIT_UNTIL(dstat, regs->dstat,
1115 1.2 ad dstat & SII_DNE, SII_WAIT_COUNT, i);
1116 1.2 ad regs->dstat = SII_DNE;
1117 1.2 ad wbflush();
1118 1.2 ad /* read the message length */
1119 1.2 ad msg = sii_GetByte(regs, SII_MSG_IN_PHASE, 1);
1120 1.2 ad if (msg < 0) {
1121 1.2 ad dstat = regs->dstat;
1122 1.2 ad goto again;
1123 1.2 ad }
1124 1.2 ad sii_buf[1] = msg; /* message length */
1125 1.2 ad if (msg == 0)
1126 1.2 ad msg = 256;
1127 1.2 ad /*
1128 1.2 ad * We read and acknowlege all the bytes
1129 1.2 ad * except the last so we can assert ATN
1130 1.2 ad * if needed before acknowledging the last.
1131 1.2 ad */
1132 1.2 ad for (i = 0; i < msg; i++) {
1133 1.2 ad dstat = sii_GetByte(regs,
1134 1.2 ad SII_MSG_IN_PHASE, i < msg - 1);
1135 1.2 ad if ((int)dstat < 0) {
1136 1.2 ad dstat = regs->dstat;
1137 1.2 ad goto again;
1138 1.2 ad }
1139 1.2 ad sii_buf[i + 2] = dstat;
1140 1.2 ad }
1141 1.2 ad
1142 1.2 ad switch (sii_buf[2]) {
1143 1.2 ad case MSG_EXT_MODIFY_DATA_PTR:
1144 1.2 ad /* acknowledge last byte */
1145 1.2 ad regs->comm = SII_INXFER |
1146 1.2 ad SII_MSG_IN_PHASE |
1147 1.2 ad (comm & SII_STATE_MSK);
1148 1.2 ad SII_WAIT_UNTIL(dstat, regs->dstat,
1149 1.2 ad dstat & SII_DNE,
1150 1.2 ad SII_WAIT_COUNT, i);
1151 1.2 ad regs->dstat = SII_DNE;
1152 1.2 ad wbflush();
1153 1.2 ad i = (sii_buf[3] << 24) |
1154 1.2 ad (sii_buf[4] << 16) |
1155 1.2 ad (sii_buf[5] << 8) |
1156 1.2 ad sii_buf[6];
1157 1.2 ad if (state->dmaPrevPhase >= 0) {
1158 1.2 ad state->dmaAddrL += i;
1159 1.2 ad state->dmaCnt -= i;
1160 1.2 ad }
1161 1.2 ad break;
1162 1.2 ad
1163 1.2 ad case MSG_EXT_SDTR_LEN:
1164 1.2 ad /*
1165 1.2 ad * Acknowledge last byte and
1166 1.2 ad * signal a request for MSG_OUT.
1167 1.2 ad */
1168 1.2 ad regs->comm = SII_INXFER | SII_ATN |
1169 1.2 ad SII_MSG_IN_PHASE |
1170 1.2 ad (comm & SII_STATE_MSK);
1171 1.2 ad SII_WAIT_UNTIL(dstat, regs->dstat,
1172 1.2 ad dstat & SII_DNE,
1173 1.2 ad SII_WAIT_COUNT, i);
1174 1.2 ad regs->dstat = SII_DNE;
1175 1.2 ad wbflush();
1176 1.2 ad sii_DoSync(regs, state);
1177 1.2 ad break;
1178 1.2 ad
1179 1.2 ad default:
1180 1.2 ad reject:
1181 1.2 ad /*
1182 1.2 ad * Acknowledge last byte and
1183 1.2 ad * signal a request for MSG_OUT.
1184 1.2 ad */
1185 1.2 ad regs->comm = SII_INXFER | SII_ATN |
1186 1.2 ad SII_MSG_IN_PHASE |
1187 1.2 ad (comm & SII_STATE_MSK);
1188 1.2 ad SII_WAIT_UNTIL(dstat, regs->dstat,
1189 1.2 ad dstat & SII_DNE,
1190 1.2 ad SII_WAIT_COUNT, i);
1191 1.2 ad regs->dstat = SII_DNE;
1192 1.2 ad wbflush();
1193 1.2 ad
1194 1.2 ad /* wait for MSG_OUT phase */
1195 1.2 ad SII_WAIT_UNTIL(dstat, regs->dstat,
1196 1.2 ad dstat & SII_TBE,
1197 1.2 ad SII_WAIT_COUNT, i);
1198 1.2 ad
1199 1.2 ad /* send a reject message */
1200 1.2 ad regs->data = MSG_MESSAGE_REJECT;
1201 1.2 ad regs->comm = SII_INXFER |
1202 1.2 ad (regs->cstat & SII_STATE_MSK) |
1203 1.2 ad SII_MSG_OUT_PHASE;
1204 1.2 ad SII_WAIT_UNTIL(dstat, regs->dstat,
1205 1.2 ad dstat & SII_DNE,
1206 1.2 ad SII_WAIT_COUNT, i);
1207 1.2 ad regs->dstat = SII_DNE;
1208 1.2 ad wbflush();
1209 1.2 ad }
1210 1.2 ad break;
1211 1.2 ad
1212 1.2 ad case MSG_SAVEDATAPOINTER:
1213 1.2 ad case MSG_RESTOREPOINTERS:
1214 1.2 ad /* acknowledge last byte */
1215 1.2 ad regs->comm = SII_INXFER | SII_MSG_IN_PHASE |
1216 1.2 ad (comm & SII_STATE_MSK);
1217 1.2 ad SII_WAIT_UNTIL(dstat, regs->dstat,
1218 1.2 ad dstat & SII_DNE, SII_WAIT_COUNT, i);
1219 1.2 ad regs->dstat = SII_DNE;
1220 1.2 ad wbflush();
1221 1.2 ad /* wait a short time for another msg */
1222 1.2 ad SII_WAIT_UNTIL(dstat, regs->dstat,
1223 1.2 ad dstat & (SII_CI | SII_DI),
1224 1.2 ad SII_WAIT_COUNT, i);
1225 1.2 ad if (dstat & (SII_CI | SII_DI)) {
1226 1.2 ad #ifdef DEBUG
1227 1.2 ad if (sii_debug > 4)
1228 1.2 ad printf("cnt %d\n", i);
1229 1.2 ad #endif
1230 1.2 ad goto again;
1231 1.2 ad }
1232 1.2 ad break;
1233 1.2 ad
1234 1.2 ad case MSG_DISCONNECT:
1235 1.2 ad /* acknowledge last byte */
1236 1.2 ad regs->comm = SII_INXFER | SII_MSG_IN_PHASE |
1237 1.2 ad (comm & SII_STATE_MSK);
1238 1.2 ad SII_WAIT_UNTIL(dstat, regs->dstat,
1239 1.2 ad dstat & SII_DNE, SII_WAIT_COUNT, i);
1240 1.2 ad regs->dstat = SII_DNE;
1241 1.2 ad wbflush();
1242 1.2 ad state->prevComm = comm;
1243 1.2 ad #ifdef DEBUG
1244 1.2 ad if (sii_debug > 4)
1245 1.2 ad printf("disconn %d ", sc->sc_target);
1246 1.2 ad #endif
1247 1.2 ad /*
1248 1.2 ad * Wait a short time for disconnect.
1249 1.2 ad * Don't be fooled if SII_BER happens first.
1250 1.2 ad * Note: a reselect may happen here.
1251 1.2 ad */
1252 1.2 ad SII_WAIT_UNTIL(cstat, regs->cstat,
1253 1.2 ad cstat & (SII_RST | SII_SCH),
1254 1.2 ad SII_WAIT_COUNT, i);
1255 1.2 ad if ((cstat & (SII_RST | SII_SCH |
1256 1.2 ad SII_STATE_MSK)) != SII_SCH) {
1257 1.2 ad #ifdef DEBUG
1258 1.2 ad if (sii_debug > 4)
1259 1.2 ad printf("cnt %d\n", i);
1260 1.2 ad #endif
1261 1.2 ad dstat = regs->dstat;
1262 1.2 ad goto again;
1263 1.2 ad }
1264 1.2 ad regs->cstat = SII_SCH | SII_BER;
1265 1.2 ad regs->comm = 0;
1266 1.2 ad wbflush();
1267 1.2 ad sc->sc_target = -1;
1268 1.2 ad /*
1269 1.2 ad * Double check that we didn't miss a state
1270 1.2 ad * change between seeing it and clearing
1271 1.2 ad * the SII_SCH bit.
1272 1.2 ad */
1273 1.2 ad i = regs->cstat;
1274 1.2 ad if (!(i & SII_SCH) && (i & SII_STATE_MSK) !=
1275 1.2 ad (cstat & SII_STATE_MSK))
1276 1.2 ad sii_StateChg(sc, i);
1277 1.2 ad break;
1278 1.2 ad
1279 1.2 ad case MSG_MESSAGE_REJECT:
1280 1.2 ad /* acknowledge last byte */
1281 1.2 ad regs->comm = SII_INXFER | SII_MSG_IN_PHASE |
1282 1.2 ad (comm & SII_STATE_MSK);
1283 1.2 ad SII_WAIT_UNTIL(dstat, regs->dstat,
1284 1.2 ad dstat & SII_DNE, SII_WAIT_COUNT, i);
1285 1.2 ad regs->dstat = SII_DNE;
1286 1.2 ad wbflush();
1287 1.2 ad printf("%s: device %d: message reject.\n",
1288 1.2 ad sc->sc_dev.dv_xname, sc->sc_target);
1289 1.2 ad break;
1290 1.2 ad
1291 1.2 ad default:
1292 1.2 ad if (!(msg & MSG_IDENTIFYFLAG)) {
1293 1.2 ad printf("%s: device %d: couldn't handle "
1294 1.2 ad "message 0x%x... rejecting.\n",
1295 1.2 ad sc->sc_dev.dv_xname, sc->sc_target,
1296 1.2 ad msg);
1297 1.2 ad #ifdef DEBUG
1298 1.2 ad sii_DumpLog();
1299 1.2 ad #endif
1300 1.2 ad goto reject;
1301 1.2 ad }
1302 1.2 ad /* acknowledge last byte */
1303 1.2 ad regs->comm = SII_INXFER | SII_MSG_IN_PHASE |
1304 1.2 ad (comm & SII_STATE_MSK);
1305 1.2 ad SII_WAIT_UNTIL(dstat, regs->dstat,
1306 1.2 ad dstat & SII_DNE, SII_WAIT_COUNT, i);
1307 1.2 ad regs->dstat = SII_DNE;
1308 1.2 ad wbflush();
1309 1.2 ad /* may want to check LUN some day */
1310 1.2 ad /* wait a short time for another msg */
1311 1.2 ad SII_WAIT_UNTIL(dstat, regs->dstat,
1312 1.2 ad dstat & (SII_CI | SII_DI),
1313 1.2 ad SII_WAIT_COUNT, i);
1314 1.2 ad if (dstat & (SII_CI | SII_DI)) {
1315 1.2 ad #ifdef DEBUG
1316 1.2 ad if (sii_debug > 4)
1317 1.2 ad printf("cnt %d\n", i);
1318 1.2 ad #endif
1319 1.2 ad goto again;
1320 1.2 ad }
1321 1.2 ad }
1322 1.2 ad break;
1323 1.2 ad
1324 1.2 ad case SII_MSG_OUT_PHASE:
1325 1.2 ad #ifdef DEBUG
1326 1.2 ad if (sii_debug > 4)
1327 1.2 ad printf("MsgOut\n");
1328 1.2 ad #endif
1329 1.2 ad printf("MsgOut %x\n", state->flags); /* XXX */
1330 1.2 ad
1331 1.2 ad /*
1332 1.2 ad * Check for parity error.
1333 1.2 ad * Hardware will automatically set ATN
1334 1.2 ad * to request the device for a MSG_OUT phase.
1335 1.2 ad */
1336 1.2 ad if (state->flags & PARITY_ERR) {
1337 1.2 ad state->flags &= ~PARITY_ERR;
1338 1.2 ad regs->data = MSG_PARITY_ERROR;
1339 1.2 ad } else
1340 1.2 ad regs->data = MSG_NOOP;
1341 1.2 ad regs->comm = SII_INXFER | (comm & SII_STATE_MSK) |
1342 1.2 ad SII_MSG_OUT_PHASE;
1343 1.2 ad wbflush();
1344 1.2 ad
1345 1.2 ad /* wait a short time for XFER complete */
1346 1.2 ad SII_WAIT_UNTIL(dstat, regs->dstat, dstat & SII_DNE,
1347 1.2 ad SII_WAIT_COUNT, i);
1348 1.2 ad #ifdef DEBUG
1349 1.2 ad if (sii_debug > 4)
1350 1.2 ad printf("ds %x i %d\n", dstat, i);
1351 1.2 ad #endif
1352 1.2 ad /* just clear the DNE bit and check errors later */
1353 1.2 ad if (dstat & SII_DNE) {
1354 1.2 ad regs->dstat = SII_DNE;
1355 1.2 ad wbflush();
1356 1.2 ad }
1357 1.2 ad break;
1358 1.2 ad
1359 1.2 ad default:
1360 1.2 ad printf("%s: Couldn't handle phase %d... ignoring.\n",
1361 1.2 ad sc->sc_dev.dv_xname, dstat & SII_PHASE_MSK);
1362 1.2 ad }
1363 1.2 ad }
1364 1.2 ad
1365 1.2 ad #ifdef DEBUG
1366 1.2 ad if (sii_debug > 3)
1367 1.2 ad printf("\n");
1368 1.2 ad #endif
1369 1.2 ad /*
1370 1.2 ad * Check to make sure we won't be interrupted again.
1371 1.2 ad * Deglitch dstat register.
1372 1.2 ad */
1373 1.2 ad msg = regs->dstat;
1374 1.2 ad while (msg != (dstat = regs->dstat))
1375 1.2 ad msg = dstat;
1376 1.2 ad if (dstat & (SII_CI | SII_DI))
1377 1.2 ad goto again;
1378 1.2 ad
1379 1.2 ad if (sc->sc_target < 0) {
1380 1.2 ad /* look for another device that is ready */
1381 1.2 ad for (i = 0; i < SII_NCMD; i++) {
1382 1.2 ad /* don't restart a disconnected command */
1383 1.2 ad if (!sc->sc_cmd[i] || sc->sc_st[i].prevComm)
1384 1.2 ad continue;
1385 1.2 ad sii_StartCmd(sc, i);
1386 1.2 ad break;
1387 1.2 ad }
1388 1.2 ad }
1389 1.2 ad return;
1390 1.2 ad
1391 1.2 ad abort:
1392 1.2 ad /* jump here to abort the current command */
1393 1.2 ad printf("%s: device %d: current command terminated\n",
1394 1.2 ad sc->sc_dev.dv_xname, sc->sc_target);
1395 1.2 ad #ifdef DEBUG
1396 1.2 ad sii_DumpLog();
1397 1.2 ad #endif
1398 1.2 ad
1399 1.2 ad if ((cstat = regs->cstat) & SII_CON) {
1400 1.2 ad /* try to send an abort msg for awhile */
1401 1.2 ad regs->dstat = SII_DNE;
1402 1.2 ad regs->data = MSG_ABORT;
1403 1.2 ad regs->comm = SII_INXFER | SII_ATN | (cstat & SII_STATE_MSK) |
1404 1.2 ad SII_MSG_OUT_PHASE;
1405 1.2 ad wbflush();
1406 1.2 ad SII_WAIT_UNTIL(dstat, regs->dstat,
1407 1.2 ad (dstat & (SII_DNE | SII_PHASE_MSK)) ==
1408 1.2 ad (SII_DNE | SII_MSG_OUT_PHASE),
1409 1.2 ad 2 * SII_WAIT_COUNT, i);
1410 1.2 ad #ifdef DEBUG
1411 1.2 ad if (sii_debug > 0)
1412 1.2 ad printf("Abort: cs %x ds %x i %d\n", cstat, dstat, i);
1413 1.2 ad #endif
1414 1.2 ad if ((dstat & (SII_DNE | SII_PHASE_MSK)) ==
1415 1.2 ad (SII_DNE | SII_MSG_OUT_PHASE)) {
1416 1.2 ad /* disconnect if command in progress */
1417 1.2 ad regs->comm = SII_DISCON;
1418 1.2 ad wbflush();
1419 1.2 ad SII_WAIT_UNTIL(cstat, regs->cstat,
1420 1.2 ad !(cstat & SII_CON), SII_WAIT_COUNT, i);
1421 1.2 ad }
1422 1.2 ad } else {
1423 1.2 ad #ifdef DEBUG
1424 1.2 ad if (sii_debug > 0)
1425 1.2 ad printf("Abort: cs %x\n", cstat);
1426 1.2 ad #endif
1427 1.2 ad }
1428 1.2 ad regs->cstat = 0xffff;
1429 1.2 ad regs->dstat = 0xffff;
1430 1.2 ad regs->comm = 0;
1431 1.2 ad wbflush();
1432 1.2 ad
1433 1.2 ad i = sc->sc_target;
1434 1.2 ad sc->sc_target = -1;
1435 1.2 ad sii_CmdDone(sc, i, EIO);
1436 1.2 ad #ifdef DEBUG
1437 1.2 ad if (sii_debug > 4)
1438 1.2 ad printf("sii_DoIntr: after CmdDone target %d\n", sc->sc_target);
1439 1.2 ad #endif
1440 1.2 ad }
1441 1.2 ad
1442 1.2 ad static void
1443 1.2 ad sii_StateChg(sc, cstat)
1444 1.2 ad struct siisoftc *sc;
1445 1.2 ad u_int cstat;
1446 1.2 ad {
1447 1.2 ad SIIRegs *regs = sc->sc_regs;
1448 1.2 ad State *state;
1449 1.2 ad int i;
1450 1.2 ad
1451 1.2 ad #ifdef DEBUG
1452 1.2 ad if (sii_debug > 4)
1453 1.2 ad printf("SCH: ");
1454 1.2 ad #endif
1455 1.2 ad
1456 1.2 ad switch (cstat & SII_STATE_MSK) {
1457 1.2 ad case 0:
1458 1.2 ad /* disconnect */
1459 1.2 ad i = sc->sc_target;
1460 1.2 ad sc->sc_target = -1;
1461 1.2 ad #ifdef DEBUG
1462 1.2 ad if (sii_debug > 4)
1463 1.2 ad printf("disconn %d ", i);
1464 1.2 ad #endif
1465 1.2 ad if (i >= 0 && !sc->sc_st[i].prevComm) {
1466 1.2 ad printf("%s: device %d: spurrious disconnect (%d)\n",
1467 1.2 ad sc->sc_dev.dv_xname, i, regs->slcsr);
1468 1.2 ad sc->sc_st[i].prevComm = 0;
1469 1.2 ad }
1470 1.2 ad break;
1471 1.2 ad
1472 1.2 ad case SII_CON:
1473 1.2 ad /* connected as initiator */
1474 1.2 ad i = regs->slcsr;
1475 1.2 ad if (sc->sc_target == i)
1476 1.2 ad break;
1477 1.2 ad printf("%s: device %d: connect to device %d??\n",
1478 1.2 ad sc->sc_dev.dv_xname, sc->sc_target, i);
1479 1.2 ad sc->sc_target = i;
1480 1.2 ad break;
1481 1.2 ad
1482 1.2 ad case SII_DST:
1483 1.2 ad /*
1484 1.2 ad * Wait for CON to become valid,
1485 1.2 ad * chip is slow sometimes.
1486 1.2 ad */
1487 1.2 ad SII_WAIT_UNTIL(cstat, regs->cstat,
1488 1.2 ad cstat & SII_CON, SII_WAIT_COUNT, i);
1489 1.2 ad if (!(cstat & SII_CON))
1490 1.2 ad panic("sii resel");
1491 1.2 ad /* FALLTHROUGH */
1492 1.2 ad
1493 1.2 ad case SII_CON | SII_DST:
1494 1.2 ad /*
1495 1.2 ad * Its a reselection. Save the ID and wait for
1496 1.2 ad * interrupts to tell us what to do next
1497 1.2 ad * (should be MSG_IN of IDENTIFY).
1498 1.2 ad * NOTE: sc_target may be >= 0 if we were in
1499 1.2 ad * the process of trying to start a command
1500 1.2 ad * and were reselected before the select
1501 1.2 ad * command finished.
1502 1.2 ad */
1503 1.2 ad sc->sc_target = i = regs->destat;
1504 1.2 ad state = &sc->sc_st[i];
1505 1.2 ad regs->comm = SII_CON | SII_DST | SII_MSG_IN_PHASE;
1506 1.2 ad regs->dmctrl = state->dmaReqAck;
1507 1.2 ad wbflush();
1508 1.2 ad if (!state->prevComm) {
1509 1.2 ad printf("%s: device %d: spurious reselection\n",
1510 1.2 ad sc->sc_dev.dv_xname, i);
1511 1.2 ad break;
1512 1.2 ad }
1513 1.2 ad state->prevComm = 0;
1514 1.2 ad #ifdef DEBUG
1515 1.2 ad if (sii_debug > 4)
1516 1.2 ad printf("resel %d ", sc->sc_target);
1517 1.2 ad #endif
1518 1.2 ad break;
1519 1.2 ad
1520 1.2 ad #ifdef notyet
1521 1.2 ad case SII_DST | SII_TGT:
1522 1.2 ad case SII_CON | SII_DST | SII_TGT:
1523 1.2 ad /* connected as target */
1524 1.2 ad printf("%s: Selected by device %d as target!!\n",
1525 1.2 ad sc->sc_dev.dv_xname, regs->destat);
1526 1.2 ad regs->comm = SII_DISCON;
1527 1.2 ad wbflush();
1528 1.2 ad SII_WAIT_UNTIL(!(regs->cstat & SII_CON),
1529 1.2 ad SII_WAIT_COUNT, i);
1530 1.2 ad regs->cstat = 0xffff;
1531 1.2 ad regs->dstat = 0xffff;
1532 1.2 ad regs->comm = 0;
1533 1.2 ad break;
1534 1.2 ad #endif
1535 1.2 ad
1536 1.2 ad default:
1537 1.2 ad printf("%s: Unknown state change (cs %x)!!\n",
1538 1.2 ad sc->sc_dev.dv_xname, cstat);
1539 1.2 ad #ifdef DEBUG
1540 1.2 ad sii_DumpLog();
1541 1.2 ad #endif
1542 1.2 ad }
1543 1.2 ad }
1544 1.2 ad
1545 1.2 ad /*
1546 1.2 ad * Read one byte of data.
1547 1.2 ad * If 'ack' is true, acknowledge the byte.
1548 1.2 ad */
1549 1.2 ad static int
1550 1.2 ad sii_GetByte(regs, phase, ack)
1551 1.2 ad SIIRegs *regs;
1552 1.2 ad int phase, ack;
1553 1.2 ad {
1554 1.2 ad u_int dstat;
1555 1.2 ad u_int state;
1556 1.2 ad int i;
1557 1.2 ad int data;
1558 1.2 ad
1559 1.2 ad dstat = regs->dstat;
1560 1.2 ad state = regs->cstat & SII_STATE_MSK;
1561 1.2 ad i = -1;
1562 1.2 ad if (!(dstat & SII_IBF) || (dstat & SII_MIS)) {
1563 1.2 ad regs->comm = state | phase;
1564 1.2 ad wbflush();
1565 1.2 ad /* wait a short time for IBF */
1566 1.2 ad SII_WAIT_UNTIL(dstat, regs->dstat, dstat & SII_IBF,
1567 1.2 ad SII_WAIT_COUNT, i);
1568 1.2 ad #ifdef DEBUG
1569 1.2 ad if (!(dstat & SII_IBF))
1570 1.2 ad printf("status no IBF\n");
1571 1.2 ad #endif
1572 1.2 ad }
1573 1.2 ad if (dstat & SII_DNE) { /* XXX */
1574 1.2 ad printf("sii_GetByte: DNE set 5\n");
1575 1.2 ad #ifdef DEBUG
1576 1.2 ad sii_DumpLog();
1577 1.2 ad #endif
1578 1.2 ad regs->dstat = SII_DNE;
1579 1.2 ad }
1580 1.2 ad data = regs->data;
1581 1.2 ad /* check for parity error */
1582 1.2 ad if (dstat & SII_IPE) {
1583 1.2 ad #ifdef DEBUG
1584 1.2 ad if (sii_debug > 4)
1585 1.2 ad printf("cnt0 %d\n", i);
1586 1.2 ad #endif
1587 1.2 ad printf("sii_GetByte: data %x ?? ds %x cm %x i %d\n",
1588 1.2 ad data, dstat, regs->comm, i); /* XXX */
1589 1.2 ad data = -1;
1590 1.2 ad ack = 1;
1591 1.2 ad }
1592 1.2 ad
1593 1.2 ad if (ack) {
1594 1.2 ad regs->comm = SII_INXFER | state | phase;
1595 1.2 ad wbflush();
1596 1.2 ad
1597 1.2 ad /* wait a short time for XFER complete */
1598 1.2 ad SII_WAIT_UNTIL(dstat, regs->dstat, dstat & SII_DNE,
1599 1.2 ad SII_WAIT_COUNT, i);
1600 1.2 ad
1601 1.2 ad /* clear the DNE */
1602 1.2 ad if (dstat & SII_DNE) {
1603 1.2 ad regs->dstat = SII_DNE;
1604 1.2 ad wbflush();
1605 1.2 ad }
1606 1.2 ad }
1607 1.2 ad
1608 1.2 ad return (data);
1609 1.2 ad }
1610 1.2 ad
1611 1.2 ad /*
1612 1.2 ad * Exchange messages to initiate synchronous data transfers.
1613 1.2 ad */
1614 1.2 ad static void
1615 1.2 ad sii_DoSync(regs, state)
1616 1.2 ad SIIRegs *regs;
1617 1.2 ad State *state;
1618 1.2 ad {
1619 1.2 ad u_int dstat, comm;
1620 1.2 ad int i, j;
1621 1.2 ad u_int len;
1622 1.2 ad
1623 1.2 ad #ifdef DEBUG
1624 1.2 ad if (sii_debug)
1625 1.2 ad printf("sii_DoSync: len %d per %d req/ack %d\n",
1626 1.2 ad sii_buf[1], sii_buf[3], sii_buf[4]);
1627 1.2 ad #endif
1628 1.2 ad
1629 1.2 ad /* SII chip can only handle a minimum transfer period of ??? */
1630 1.2 ad if (sii_buf[3] < 64)
1631 1.2 ad sii_buf[3] = 64;
1632 1.2 ad /* SII chip can only handle a maximum REQ/ACK offset of 3 */
1633 1.2 ad len = sii_buf[4];
1634 1.2 ad if (len > 3)
1635 1.2 ad len = 3;
1636 1.2 ad
1637 1.2 ad sii_buf[0] = MSG_EXTENDED;
1638 1.2 ad sii_buf[1] = MSG_EXT_SDTR_LEN;
1639 1.2 ad sii_buf[2] = MSG_EXT_SDTR;
1640 1.2 ad sii_buf[4] = len;
1641 1.2 ad #if 1
1642 1.2 ad comm = SII_INXFER | SII_ATN | SII_MSG_OUT_PHASE |
1643 1.2 ad (regs->cstat & SII_STATE_MSK);
1644 1.2 ad regs->comm = comm & ~SII_INXFER;
1645 1.2 ad for (j = 0; j < 5; j++) {
1646 1.2 ad /* wait for target to request the next byte */
1647 1.2 ad SII_WAIT_UNTIL(dstat, regs->dstat, dstat & SII_TBE,
1648 1.2 ad SII_WAIT_COUNT, i);
1649 1.2 ad if (!(dstat & SII_TBE) ||
1650 1.2 ad (dstat & SII_PHASE_MSK) != SII_MSG_OUT_PHASE) {
1651 1.2 ad printf("sii_DoSync: TBE? ds %x cm %x i %d\n",
1652 1.2 ad dstat, comm, i); /* XXX */
1653 1.2 ad return;
1654 1.2 ad }
1655 1.2 ad
1656 1.2 ad /* the last message byte should have ATN off */
1657 1.2 ad if (j == 4)
1658 1.2 ad comm &= ~SII_ATN;
1659 1.2 ad
1660 1.2 ad regs->data = sii_buf[j];
1661 1.2 ad regs->comm = comm;
1662 1.2 ad wbflush();
1663 1.2 ad
1664 1.2 ad /* wait a short time for XFER complete */
1665 1.2 ad SII_WAIT_UNTIL(dstat, regs->dstat, dstat & SII_DNE,
1666 1.2 ad SII_WAIT_COUNT, i);
1667 1.2 ad
1668 1.2 ad if (!(dstat & SII_DNE)) {
1669 1.2 ad printf("sii_DoSync: DNE? ds %x cm %x i %d\n",
1670 1.2 ad dstat, comm, i); /* XXX */
1671 1.2 ad return;
1672 1.2 ad }
1673 1.2 ad
1674 1.2 ad /* clear the DNE, other errors handled later */
1675 1.2 ad regs->dstat = SII_DNE;
1676 1.2 ad wbflush();
1677 1.2 ad }
1678 1.2 ad #else /* 0 */
1679 1.2 ad sc->sii_copytobuf((u_short *)sii_buf,
1680 1.2 ad (volatile u_short *)SII_BUF_ADDR(sc), 5);
1681 1.2 ad printf("sii_DoSync: %x %x %x ds %x\n",
1682 1.2 ad ((volatile u_short *)SII_BUF_ADDR(sc))[0],
1683 1.2 ad ((volatile u_short *)SII_BUF_ADDR(sc))[2],
1684 1.2 ad ((volatile u_short *)SII_BUF_ADDR(sc))[4],
1685 1.2 ad regs->dstat); /* XXX */
1686 1.2 ad regs->dmaddrl = (u_short)(SII_BUF_ADDR(sc) >> 1);
1687 1.2 ad regs->dmaddrh = (u_short)(SII_BUF_ADDR(sc) >> 17) & 03;
1688 1.2 ad regs->dmlotc = 5;
1689 1.2 ad regs->comm = SII_DMA | SII_INXFER | SII_ATN |
1690 1.2 ad (regs->cstat & SII_STATE_MSK) | SII_MSG_OUT_PHASE;
1691 1.2 ad wbflush();
1692 1.2 ad
1693 1.2 ad /* wait a short time for XFER complete */
1694 1.2 ad SII_WAIT_UNTIL(dstat, regs->dstat,
1695 1.2 ad (dstat & (SII_DNE | SII_TCZ)) == (SII_DNE | SII_TCZ),
1696 1.2 ad SII_WAIT_COUNT, i);
1697 1.2 ad
1698 1.2 ad if ((dstat & (SII_DNE | SII_TCZ)) != (SII_DNE | SII_TCZ)) {
1699 1.2 ad printf("sii_DoSync: ds %x cm %x i %d lotc %d\n",
1700 1.2 ad dstat, regs->comm, i, regs->dmlotc); /* XXX */
1701 1.2 ad sii_DumpLog(); /* XXX */
1702 1.2 ad return;
1703 1.2 ad }
1704 1.2 ad /* clear the DNE, other errors handled later */
1705 1.2 ad regs->dstat = SII_DNE;
1706 1.2 ad wbflush();
1707 1.2 ad #endif /* 0 */
1708 1.2 ad
1709 1.2 ad #if 0
1710 1.2 ad SII_WAIT_UNTIL(dstat, regs->dstat, dstat & (SII_CI | SII_DI),
1711 1.2 ad SII_WAIT_COUNT, i);
1712 1.2 ad printf("sii_DoSync: ds %x cm %x i %d lotc %d\n",
1713 1.2 ad dstat, regs->comm, i, regs->dmlotc); /* XXX */
1714 1.2 ad #endif
1715 1.2 ad
1716 1.2 ad state->dmaReqAck = len;
1717 1.2 ad }
1718 1.2 ad
1719 1.2 ad /*
1720 1.2 ad * Issue the sequence of commands to the controller to start DMA.
1721 1.2 ad * NOTE: the data buffer should be word-aligned for DMA out.
1722 1.2 ad */
1723 1.2 ad static void
1724 1.2 ad sii_StartDMA(regs, phase, dmaAddr, size)
1725 1.2 ad SIIRegs *regs; /* which SII to use */
1726 1.2 ad int phase; /* phase to send/receive data */
1727 1.2 ad u_short *dmaAddr; /* DMA buffer address */
1728 1.2 ad int size; /* # of bytes to transfer */
1729 1.2 ad {
1730 1.2 ad
1731 1.2 ad if (regs->dstat & SII_DNE) { /* XXX */
1732 1.2 ad regs->dstat = SII_DNE;
1733 1.2 ad printf("sii_StartDMA: DNE set\n");
1734 1.2 ad #ifdef DEBUG
1735 1.2 ad sii_DumpLog();
1736 1.2 ad #endif
1737 1.2 ad }
1738 1.2 ad regs->dmaddrl = ((u_long)dmaAddr >> 1);
1739 1.2 ad regs->dmaddrh = ((u_long)dmaAddr >> 17) & 03;
1740 1.2 ad regs->dmlotc = size;
1741 1.2 ad regs->comm = SII_DMA | SII_INXFER | (regs->cstat & SII_STATE_MSK) |
1742 1.2 ad phase;
1743 1.2 ad wbflush();
1744 1.2 ad
1745 1.2 ad #ifdef DEBUG
1746 1.2 ad if (sii_debug > 5) {
1747 1.2 ad printf("sii_StartDMA: cs 0x%x, ds 0x%x, cm 0x%x, size %d\n",
1748 1.2 ad regs->cstat, regs->dstat, regs->comm, size);
1749 1.2 ad }
1750 1.2 ad #endif
1751 1.2 ad }
1752 1.2 ad
1753 1.2 ad /*
1754 1.2 ad * Call the device driver's 'done' routine to let it know the command is done.
1755 1.2 ad * The 'done' routine may try to start another command.
1756 1.2 ad * To be fair, we should start pending commands for other devices
1757 1.2 ad * before allowing the same device to start another command.
1758 1.2 ad */
1759 1.2 ad static void
1760 1.2 ad sii_CmdDone(sc, target, error)
1761 1.2 ad struct siisoftc *sc; /* which SII to use */
1762 1.2 ad int target; /* which device is done */
1763 1.2 ad int error; /* error code if any errors */
1764 1.2 ad {
1765 1.2 ad ScsiCmd *scsicmd;
1766 1.2 ad int i;
1767 1.2 ad
1768 1.2 ad scsicmd = sc->sc_cmd[target];
1769 1.2 ad #ifdef DIAGNOSTIC
1770 1.2 ad if (target < 0 || !scsicmd)
1771 1.2 ad panic("sii_CmdDone");
1772 1.2 ad #endif
1773 1.2 ad sc->sc_cmd[target] = (ScsiCmd *)0;
1774 1.2 ad #ifdef DEBUG
1775 1.2 ad if (sii_debug > 1) {
1776 1.2 ad printf("sii_CmdDone: %s target %d cmd %x err %d resid %d\n",
1777 1.2 ad sc->sc_dev.dv_xname,
1778 1.2 ad target, scsicmd->cmd[0], error, sc->sc_st[target].buflen);
1779 1.2 ad }
1780 1.2 ad #endif
1781 1.2 ad
1782 1.2 ad /* look for another device that is ready */
1783 1.2 ad for (i = 0; i < SII_NCMD; i++) {
1784 1.2 ad /* don't restart a disconnected command */
1785 1.2 ad if (!sc->sc_cmd[i] || sc->sc_st[i].prevComm)
1786 1.2 ad continue;
1787 1.2 ad sii_StartCmd(sc, i);
1788 1.2 ad break;
1789 1.2 ad }
1790 1.2 ad
1791 1.2 ad sc->sc_xs[target]->status = sc->sc_st[target].statusByte;
1792 1.2 ad /*
1793 1.2 ad * Convert SII driver error code to MI SCSI XS_*.
1794 1.2 ad */
1795 1.2 ad switch (error) {
1796 1.2 ad case 0:
1797 1.2 ad sc->sc_xs[target]->error = XS_NOERROR;
1798 1.2 ad break;
1799 1.2 ad case ENXIO:
1800 1.2 ad sc->sc_xs[target]->error = XS_SELTIMEOUT;
1801 1.2 ad break;
1802 1.2 ad case EBUSY:
1803 1.2 ad sc->sc_xs[target]->error = XS_BUSY;
1804 1.2 ad break;
1805 1.2 ad case EIO:
1806 1.2 ad sc->sc_xs[target]->error = XS_DRIVER_STUFFUP;
1807 1.2 ad break;
1808 1.2 ad default:
1809 1.2 ad sc->sc_xs[target]->error = XS_DRIVER_STUFFUP;
1810 1.2 ad }
1811 1.2 ad sc->sc_xs[target]->resid = sc->sc_st[target].buflen;
1812 1.2 ad sc->sc_xs[target]->xs_status |= XS_STS_DONE;
1813 1.2 ad scsipi_done(sc->sc_xs[target]);
1814 1.2 ad }
1815 1.2 ad
1816 1.2 ad #ifdef DEBUG
1817 1.2 ad static void
1818 1.2 ad sii_DumpLog()
1819 1.2 ad {
1820 1.2 ad struct sii_log *lp;
1821 1.2 ad
1822 1.2 ad printf("sii: cmd %x bn %d cnt %d\n", sii_debug_cmd, sii_debug_bn,
1823 1.2 ad sii_debug_sz);
1824 1.2 ad lp = sii_logp;
1825 1.2 ad do {
1826 1.2 ad printf("target %d cs %x ds %x cm %x msg %x rlen %x dlen %x\n",
1827 1.2 ad lp->target, lp->cstat, lp->dstat, lp->comm, lp->msg,
1828 1.2 ad lp->rlen, lp->dlen);
1829 1.2 ad if (++lp >= &sii_log[NLOG])
1830 1.2 ad lp = sii_log;
1831 1.2 ad } while (lp != sii_logp);
1832 1.2 ad }
1833 1.2 ad #endif
1834