bus.h revision 1.4
1/* $NetBSD: bus.h,v 1.4 1997/11/28 00:33:53 jonathan Exp $ */ 2 3/* 4 * Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author) 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Jonathan Stone for 18 * the NetBSD Project. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 36/* 37 * NetBSD machine-indepedent bus accessor macros/functions for Decstations. 38 */ 39#ifndef _PMAX_BUS_H_ 40#define _PMAX_BUS_H_ 41 42#include <mips/locore.h> /* wbflush() */ 43 44 45/* 46 * Bus address and size types 47 */ 48typedef u_long bus_addr_t; 49typedef u_long bus_size_t; 50 51/* 52 * Access types for bus resources and addresses. 53 */ 54typedef int bus_space_tag_t; 55typedef u_long bus_space_handle_t; 56 57 58/* 59 * Read or write a 1, 2, or 4-byte quantity from/to a bus-space 60 * address, as defined by (space-tag, handle, offset 61 */ 62#define bus_space_read_1(t, h, o) \ 63 (*(volatile u_int8_t *)((h) + (o))) 64 65#define bus_space_read_2(t, h, o) \ 66 (*(volatile u_int16_t *)((h) + (o))) 67 68#define bus_space_read_4(t, h, o) \ 69 (*(volatile u_int32_t *)((h) + (o))) 70 71#define bus_space_write_1(t, h, o, v) \ 72 do { ((void)(*(volatile u_int8_t *)((h) + (o)) = (v))); } while (0) 73 74#define bus_space_write_2(t, h, o, v) \ 75 do { ((void)(*(volatile u_int16_t *)((h) + (o)) = (v))); } while (0) 76 77#define bus_space_write_4(t, h, o, v) \ 78 do { ((void)(*(volatile u_int32_t *)((h) + (o)) = (v))); } while (0) 79 80/* 81 * Read `count' 1, 2, or 4-byte quantities from bus-space 82 * address, defined by (space-tag, handle, offset). 83 * Copy to the specified buffer address. 84 */ 85#define bus_space_read_multi_1(t, h, o, a, c) \ 86 do { \ 87 register int __i ; \ 88 for (__i = 0; i < (c); i++) \ 89 ((u_char *)(a))[__i] = bus_space_read_1(t, h, o); \ 90 } while (0) 91 92 93#define bus_space_read_multi_2(t, h, o, a, c) \ 94 do { \ 95 register int __i ; \ 96 for (__i = 0; i < (c); i++) \ 97 ((u_int16t_t *)(a))[__i] = bus_space_read_2(t, h, o); \ 98 } while (0) 99 100#define bus_space_read_multi_4(t, h, o, a, c) \ 101 do { \ 102 register int __i ; \ 103 for (__i = 0; i < (c); i++) \ 104 ((u_int32_t *)(a))[__i] = bus_space_read_4(t, h, o); \ 105 } while (0) 106 107/* 108 * Write `count' 1, 2, or 4-byte quantities to a bus-space 109 * address, defined by (space-tag, handle, offset). 110 * Copy from the specified buffer address. 111 */ 112#define bus_space_write_multi_1(t, h, o, a, c) \ 113 do { \ 114 register int __i ; \ 115 for (__i = 0; i < (c); i++) \ 116 bus_space_write_1(t, h, o, ((u_char *)(a))[__i]); \ 117 } while (0) 118 119#define bus_space_write_multi_2(t, h, o, a, c) \ 120 do { \ 121 register int __i ; \ 122 for (__i = 0; i < (c); i++) \ 123 bus_space_write_2(t, h, o, ((u_int16_t *)(a))[__i]); \ 124 } while (0) 125 126#define bus_space_write_multi_4(t, h, o, a, c) \ 127 do { \ 128 register int __i ; \ 129 for (__i = 0; i < (c); i++) \ 130 bus_space_write_4(t, h, o, ((u_int32_t *)(a))[__i]); \ 131 } while (0) 132 133/* 134 * Copy `count' 1, 2, or 4-byte values from one bus-space address 135 * (t, h, o triple) to another. 136 */ 137#define bus_space_copy_multi_1(t, h1, h2, o1, o2, c) \ 138 do { \ 139 register int __i ; \ 140 for (__i = 0; i < (c); i++) \ 141 bus_space_write_1(t, h1, o1, bus_space_read_1(t, h2, o2)); \ 142 } while (0) 143 144#define bus_space_copy_multi_2(t, h1, h2, o1, o2, c) \ 145 do { \ 146 register int __i ; \ 147 for (__i = 0; i < (c); i++) \ 148 bus_space_write_2(t, h1, o1, bus_space_read_2(t, h2, o2)); \ 149 while (0) 150 151#define bus_space_copy_multi_4(t, h1, h2, o1, o2, c) \ 152 do { \ 153 register int __i ; \ 154 for (__i = 0; i < (c); i++) \ 155 bus_space_write_4(t, h1, o1, bus_space_read_4(t, h2, o2)); \ 156 } while (0) 157 158 159/* 160 * Bus-space barriers. 161 * Since DECstation DMA is non-cache-coherent, we have to handle 162 * consistency in software anyway (e.g., via bus -DMA, or by ensuring 163 * that DMA buffers are referenced via uncached address space. 164 * For now, simply do CPU writebuffer flushes and export the flags 165 * to MI code. 166 */ 167#define bus_space_barrier(t, h, o, l, f) wbflush() 168 169#define BUS_BARRIER_READ 0x01 170#define BUS_BARRIER_WRITE 0x02 171 172#endif /* _PMAX_BUS_H_ */ 173