intr.h revision 1.10 1 1.10 ad /* $NetBSD: intr.h,v 1.10 2000/01/09 15:34:43 ad Exp $ */
2 1.2 perry
3 1.3 jonathan /*
4 1.3 jonathan * Copyright (c) 1998 Jonathan Stone. All rights reserved.
5 1.3 jonathan *
6 1.3 jonathan * Redistribution and use in source and binary forms, with or without
7 1.3 jonathan * modification, are permitted provided that the following conditions
8 1.3 jonathan * are met:
9 1.3 jonathan * 1. Redistributions of source code must retain the above copyright
10 1.3 jonathan * notice, this list of conditions and the following disclaimer.
11 1.3 jonathan * 2. Redistributions in binary form must reproduce the above copyright
12 1.3 jonathan * notice, this list of conditions and the following disclaimer in the
13 1.3 jonathan * documentation and/or other materials provided with the distribution.
14 1.3 jonathan * 3. All advertising materials mentioning features or use of this software
15 1.3 jonathan * must display the following acknowledgement:
16 1.3 jonathan * This product includes software developed by Jonathan Stone for
17 1.3 jonathan * the NetBSD Project.
18 1.3 jonathan * 4. The name of the author may not be used to endorse or promote products
19 1.3 jonathan * derived from this software without specific prior written permission.
20 1.3 jonathan *
21 1.3 jonathan * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22 1.3 jonathan * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23 1.3 jonathan * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24 1.3 jonathan * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 1.3 jonathan * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 1.3 jonathan * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 1.3 jonathan * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 1.3 jonathan * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 1.3 jonathan * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 1.3 jonathan * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 1.3 jonathan */
32 1.1 jonathan
33 1.1 jonathan #ifndef _PMAX_INTR_H_
34 1.1 jonathan #define _PMAX_INTR_H_
35 1.4 jonathan
36 1.4 jonathan #define IPL_NONE 0 /* disable only this interrupt */
37 1.4 jonathan #define IPL_BIO 1 /* disable block I/O interrupts */
38 1.4 jonathan #define IPL_NET 2 /* disable network interrupts */
39 1.4 jonathan #define IPL_TTY 3 /* disable terminal interrupts */
40 1.4 jonathan #define IPL_CLOCK 4 /* disable clock interrupts */
41 1.4 jonathan #define IPL_STATCLOCK 5 /* disable profiling interrupts */
42 1.4 jonathan #define IPL_SERIAL 6 /* disable serial hardware interrupts */
43 1.4 jonathan #define IPL_DMA 7 /* disable DMA reload interrupts */
44 1.4 jonathan #define IPL_HIGH 8 /* disable all interrupts */
45 1.4 jonathan
46 1.5 nisimura #ifdef _KERNEL
47 1.5 nisimura #ifndef _LOCORE
48 1.5 nisimura
49 1.6 nisimura #include <mips/cpuregs.h>
50 1.6 nisimura
51 1.9 simonb int _splraise __P((int));
52 1.9 simonb int _spllower __P((int));
53 1.9 simonb int _splset __P((int));
54 1.9 simonb int _splget __P((void));
55 1.9 simonb void _splnone __P((void));
56 1.9 simonb void _setsoftintr __P((int));
57 1.9 simonb void _clrsoftintr __P((int));
58 1.6 nisimura
59 1.6 nisimura #define setsoftclock() _setsoftintr(MIPS_SOFT_INT_MASK_0)
60 1.6 nisimura #define setsoftnet() _setsoftintr(MIPS_SOFT_INT_MASK_1)
61 1.6 nisimura #define clearsoftclock() _clrsoftintr(MIPS_SOFT_INT_MASK_0)
62 1.6 nisimura #define clearsoftnet() _clrsoftintr(MIPS_SOFT_INT_MASK_1)
63 1.6 nisimura
64 1.6 nisimura #define splhigh() _splraise(MIPS_INT_MASK)
65 1.6 nisimura #define spl0() (void)_spllower(0)
66 1.6 nisimura #define splx(s) (void)_splset(s)
67 1.6 nisimura #define splbio() (_splraise(splvec.splbio))
68 1.6 nisimura #define splnet() (_splraise(splvec.splnet))
69 1.6 nisimura #define spltty() (_splraise(splvec.spltty))
70 1.6 nisimura #define splimp() (_splraise(splvec.splimp))
71 1.6 nisimura #define splpmap() (_splraise(splvec.splimp))
72 1.6 nisimura #define splclock() (_splraise(splvec.splclock))
73 1.6 nisimura #define splstatclock() (_splraise(splvec.splstatclock))
74 1.8 thorpej #define spllowersoftclock() _spllower(MIPS_SOFT_INT_MASK_0)
75 1.8 thorpej #define splsoftclock() _splraise(MIPS_SOFT_INT_MASK_0)
76 1.6 nisimura #define splsoftnet() _splraise(MIPS_SOFT_INT_MASK_1)
77 1.6 nisimura
78 1.6 nisimura struct splvec {
79 1.6 nisimura int splbio;
80 1.6 nisimura int splnet;
81 1.6 nisimura int spltty;
82 1.6 nisimura int splimp;
83 1.6 nisimura int splclock;
84 1.6 nisimura int splstatclock;
85 1.6 nisimura };
86 1.6 nisimura extern struct splvec splvec;
87 1.6 nisimura
88 1.6 nisimura /* Conventionals ... */
89 1.6 nisimura
90 1.6 nisimura #define MIPS_SPLHIGH (MIPS_INT_MASK)
91 1.6 nisimura #define MIPS_SPL0 (MIPS_INT_MASK_0|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1)
92 1.6 nisimura #define MIPS_SPL1 (MIPS_INT_MASK_1|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1)
93 1.6 nisimura #define MIPS_SPL3 (MIPS_INT_MASK_3|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1)
94 1.6 nisimura #define MIPS_SPL_0_1 (MIPS_INT_MASK_1|MIPS_SPL0)
95 1.6 nisimura #define MIPS_SPL_0_1_2 (MIPS_INT_MASK_2|MIPS_SPL_0_1)
96 1.6 nisimura #define MIPS_SPL_0_1_3 (MIPS_INT_MASK_3|MIPS_SPL_0_1)
97 1.6 nisimura #define MIPS_SPL_0_1_2_3 (MIPS_INT_MASK_3|MIPS_SPL_0_1_2)
98 1.3 jonathan
99 1.3 jonathan /*
100 1.3 jonathan * Index into intrcnt[], which is defined in locore
101 1.3 jonathan */
102 1.3 jonathan extern u_long intrcnt[];
103 1.3 jonathan
104 1.5 nisimura #define SOFTCLOCK_INTR 0
105 1.5 nisimura #define SOFTNET_INTR 1
106 1.5 nisimura #define SERIAL0_INTR 2
107 1.5 nisimura #define SERIAL1_INTR 3
108 1.5 nisimura #define SERIAL2_INTR 4
109 1.5 nisimura #define LANCE_INTR 5
110 1.5 nisimura #define SCSI_INTR 6
111 1.5 nisimura #define ERROR_INTR 7
112 1.5 nisimura #define HARDCLOCK 8
113 1.5 nisimura #define FPU_INTR 9
114 1.5 nisimura #define SLOT0_INTR 10
115 1.5 nisimura #define SLOT1_INTR 11
116 1.5 nisimura #define SLOT2_INTR 12
117 1.5 nisimura #define DTOP_INTR 13
118 1.5 nisimura #define ISDN_INTR 14
119 1.5 nisimura #define FLOPPY_INTR 15
120 1.5 nisimura #define STRAY_INTR 16
121 1.5 nisimura
122 1.5 nisimura /* handle i/o device interrupts */
123 1.5 nisimura extern int (*mips_hardware_intr) __P((unsigned, unsigned, unsigned, unsigned));
124 1.5 nisimura
125 1.5 nisimura #endif /* !_LOCORE */
126 1.5 nisimura #endif /* _KERNEL */
127 1.3 jonathan
128 1.10 ad #endif /* !_PMAX_INTR_H_ */
129