intr.h revision 1.21
1 /* $NetBSD: intr.h,v 1.21 2001/08/22 06:59:44 nisimura Exp $ */ 2 3 /* 4 * Copyright (c) 1998 Jonathan Stone. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Jonathan Stone for 17 * the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #ifndef _PMAX_INTR_H_ 34 #define _PMAX_INTR_H_ 35 36 #include <sys/device.h> 37 #include <sys/lock.h> 38 #include <sys/queue.h> 39 40 #define IPL_NONE 0 /* disable only this interrupt */ 41 42 #define IPL_SOFT 1 /* generic software interrupts (SI 0) */ 43 #define IPL_SOFTCLOCK 2 /* clock software interrupts (SI 0) */ 44 #define IPL_SOFTNET 3 /* network software interrupts (SI 1) */ 45 #define IPL_SOFTSERIAL 4 /* serial software interrupts (SI 1) */ 46 47 #define IPL_BIO 5 /* disable block I/O interrupts */ 48 #define IPL_NET 6 /* disable network interrupts */ 49 #define IPL_TTY 7 /* disable terminal interrupts */ 50 #define IPL_SERIAL 7 /* disable serial interrupts */ 51 #define IPL_CLOCK 8 /* disable clock interrupts */ 52 #define IPL_HIGH 8 /* disable all interrupts */ 53 54 #define _IPL_NSOFT 4 55 #define _IPL_N 9 56 57 #define _IPL_SI0_FIRST IPL_SOFT 58 #define _IPL_SI0_LAST IPL_SOFTCLOCK 59 60 #define _IPL_SI1_FIRST IPL_SOFTNET 61 #define _IPL_SI1_LAST IPL_SOFTSERIAL 62 63 #define IPL_SOFTNAMES { \ 64 "misc", \ 65 "clock", \ 66 "net", \ 67 "serial", \ 68 } 69 70 #ifdef _KERNEL 71 #ifndef _LOCORE 72 73 extern const u_int32_t ipl_si_to_sr[_IPL_NSOFT]; 74 75 #include <mips/cpuregs.h> 76 77 int _splraise __P((int)); 78 int _spllower __P((int)); 79 int _splset __P((int)); 80 int _splget __P((void)); 81 void _splnone __P((void)); 82 void _setsoftintr __P((int)); 83 void _clrsoftintr __P((int)); 84 85 #define splhigh() _splraise(MIPS_INT_MASK) 86 #define spl0() (void)_spllower(0) 87 #define splx(s) (void)_splset(s) 88 #define splbio() (_splraise(splvec.splbio)) 89 #define splnet() (_splraise(splvec.splnet)) 90 #define spltty() (_splraise(splvec.spltty)) 91 #define splvm() (_splraise(splvec.splvm)) 92 #define splclock() (_splraise(splvec.splclock)) 93 #define splstatclock() (_splraise(splvec.splstatclock)) 94 #define spllowersoftclock() _spllower(MIPS_SOFT_INT_MASK_0) 95 #define splsoftclock() _splraise(MIPS_SOFT_INT_MASK_0) 96 #define splsoftnet() _splraise(MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1) 97 98 #define splsched() splhigh() 99 #define spllock() splhigh() 100 101 struct splvec { 102 int splbio; 103 int splnet; 104 int spltty; 105 int splvm; 106 int splclock; 107 int splstatclock; 108 }; 109 extern struct splvec splvec; 110 111 /* Conventionals ... */ 112 113 #define MIPS_SPLHIGH (MIPS_INT_MASK) 114 #define MIPS_SPL0 (MIPS_INT_MASK_0|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1) 115 #define MIPS_SPL1 (MIPS_INT_MASK_1|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1) 116 #define MIPS_SPL3 (MIPS_INT_MASK_3|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1) 117 #define MIPS_SPL_0_1 (MIPS_INT_MASK_1|MIPS_SPL0) 118 #define MIPS_SPL_0_1_2 (MIPS_INT_MASK_2|MIPS_SPL_0_1) 119 #define MIPS_SPL_0_1_3 (MIPS_INT_MASK_3|MIPS_SPL_0_1) 120 #define MIPS_SPL_0_1_2_3 (MIPS_INT_MASK_3|MIPS_SPL_0_1_2) 121 122 /* 123 * Index into intrcnt[], which is defined in locore 124 */ 125 extern u_long intrcnt[]; 126 127 #if 0 128 #define SOFTCLOCK_INTR 0 129 #define SOFTNET_INTR 1 130 #define SERIAL0_INTR 2 131 #define SERIAL1_INTR 3 132 #define LANCE_INTR 4 133 #define SCSI_INTR 5 134 #define ERROR_INTR 6 135 #define HARDCLOCK 7 136 #define FPU_INTR 8 137 #define SLOT0_INTR 9 138 #define SLOT1_INTR 10 139 #define SLOT2_INTR 11 140 #define DTOP_INTR 12 141 #define ISDN_INTR 13 142 #define FLOPPY_INTR 14 143 #define STRAY_INTR 15 144 #else 145 #define SERIAL0_INTR 0 146 #define SERIAL1_INTR 1 147 #define LANCE_INTR 2 148 #define SCSI_INTR 3 149 #define ERROR_INTR 4 150 #define SLOT0_INTR 5 151 #define SLOT1_INTR 6 152 #define SLOT2_INTR 7 153 #define DTOP_INTR 8 154 #define ISDN_INTR 9 155 #define FLOPPY_INTR 10 156 #define STRAY_INTR 11 157 #endif 158 159 struct intrhand { 160 int (*ih_func) __P((void *)); 161 void *ih_arg; 162 }; 163 extern struct intrhand intrtab[]; 164 165 #define SYS_DEV_SCSI SCSI_INTR 166 #define SYS_DEV_LANCE LANCE_INTR 167 #define SYS_DEV_SCC0 SERIAL0_INTR 168 #define SYS_DEV_SCC1 SERIAL1_INTR 169 #define SYS_DEV_DTOP DTOP_INTR 170 #define SYS_DEV_FDC FLOPPY_INTR 171 #define SYS_DEV_ISDN ISDN_INTR 172 #define SYS_DEV_OPT0 SLOT0_INTR 173 #define SYS_DEV_OPT1 SLOT1_INTR 174 #define SYS_DEV_OPT2 SLOT2_INTR 175 #define SYS_DEV_BOGUS -1 176 #define MAX_DEV_NCOOKIES 12 177 178 struct pmax_intrhand { 179 LIST_ENTRY(pmax_intrhand) ih_q; 180 int (*ih_func)(void *); 181 void *ih_arg; 182 }; 183 184 #define setsoft(x) \ 185 do { \ 186 _setsoftintr(ipl_si_to_sr[(x) - IPL_SOFT]); \ 187 } while (0) 188 189 struct pmax_soft_intrhand { 190 TAILQ_ENTRY(pmax_soft_intrhand) 191 sih_q; 192 struct pmax_soft_intr *sih_intrhead; 193 void (*sih_fn)(void *); 194 void *sih_arg; 195 int sih_pending; 196 }; 197 198 struct pmax_soft_intr { 199 TAILQ_HEAD(, pmax_soft_intrhand) 200 softintr_q; 201 struct evcnt softintr_evcnt; 202 struct simplelock softintr_slock; 203 unsigned long softintr_ipl; 204 }; 205 206 void *softintr_establish(int, void (*)(void *), void *); 207 void softintr_disestablish(void *); 208 void softintr_init(void); 209 void softintr_dispatch(void); 210 211 #define softintr_schedule(arg) \ 212 do { \ 213 struct pmax_soft_intrhand *__sih = (arg); \ 214 struct pmax_soft_intr *__si = __sih->sih_intrhead; \ 215 int __s; \ 216 \ 217 __s = splhigh(); \ 218 simple_lock(&__si->softintr_slock); \ 219 if (__sih->sih_pending == 0) { \ 220 TAILQ_INSERT_TAIL(&__si->softintr_q, __sih, sih_q); \ 221 __sih->sih_pending = 1; \ 222 setsoft(__si->softintr_ipl); \ 223 } \ 224 simple_unlock(&__si->softintr_slock); \ 225 splx(__s); \ 226 } while (0) 227 228 extern struct pmax_soft_intrhand *softnet_intrhand; 229 230 #define setsoftnet() softintr_schedule(softnet_intrhand) 231 232 extern struct evcnt pmax_clock_evcnt; 233 extern struct evcnt pmax_fpu_evcnt; 234 235 #endif /* !_LOCORE */ 236 #endif /* _KERNEL */ 237 238 #endif /* !_PMAX_INTR_H_ */ 239
Indexes created Wed Sep 24 02:09:48 GMT 2025