Home | History | Annotate | Line # | Download | only in include
intr.h revision 1.5
      1 /*	$NetBSD: intr.h,v 1.5 1998/08/25 01:55:40 nisimura Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1998 Jonathan Stone.  All rights reserved.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  * 3. All advertising materials mentioning features or use of this software
     15  *    must display the following acknowledgement:
     16  *	This product includes software developed by Jonathan Stone for
     17  *      the NetBSD Project.
     18  * 4. The name of the author may not be used to endorse or promote products
     19  *    derived from this software without specific prior written permission.
     20  *
     21  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     22  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     23  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     24  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     26  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     30  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     31  */
     32 
     33 #ifndef _PMAX_INTR_H_
     34 #define _PMAX_INTR_H_
     35 
     36 #define	IPL_NONE	0	/* disable only this interrupt */
     37 #define	IPL_BIO		1	/* disable block I/O interrupts */
     38 #define	IPL_NET		2	/* disable network interrupts */
     39 #define	IPL_TTY		3	/* disable terminal interrupts */
     40 #define	IPL_CLOCK	4	/* disable clock interrupts */
     41 #define	IPL_STATCLOCK	5	/* disable profiling interrupts */
     42 #define	IPL_SERIAL	6	/* disable serial hardware interrupts */
     43 #define	IPL_DMA		7	/* disable DMA reload interrupts */
     44 #define	IPL_HIGH	8	/* disable all interrupts */
     45 
     46 #ifdef _KERNEL
     47 #ifndef _LOCORE
     48 
     49 typedef int spl_t;
     50 extern spl_t splx __P((spl_t));
     51 extern spl_t splsoftnet __P((void)), splsoftclock __P((void));
     52 extern spl_t splhigh __P((void));
     53 extern spl_t spl0 __P((void));	/* XXX should not enable TC on 3min */
     54 
     55 extern void setsoftnet __P((void)), clearsoftnet __P((void));
     56 extern void setsoftclock __P((void)), clearsoftclock __P((void));
     57 
     58 
     59 extern int (*Mach_splnet) __P((void)), (*Mach_splbio) __P((void)),
     60 	   (*Mach_splimp) __P((void)), (*Mach_spltty) __P((void)),
     61 	   (*Mach_splclock) __P((void)), (*Mach_splstatclock) __P((void)),
     62 	   (*Mach_splnone) __P((void));
     63 
     64 #define	splnet()	(*Mach_splnet)()
     65 #define	splbio()	(*Mach_splbio)()
     66 #define	splimp()	(*Mach_splimp)()
     67 #define	spltty()	(*Mach_spltty)()
     68 #define	splclock()	(*Mach_splclock)()
     69 #define	splstatclock()	(*Mach_splstatclock)()
     70 
     71 /*
     72  * Index into intrcnt[], which is defined in locore
     73  */
     74 extern u_long intrcnt[];
     75 
     76 #define	SOFTCLOCK_INTR	0
     77 #define	SOFTNET_INTR	1
     78 #define	SERIAL0_INTR	2
     79 #define	SERIAL1_INTR	3
     80 #define	SERIAL2_INTR	4
     81 #define	LANCE_INTR	5
     82 #define	SCSI_INTR	6
     83 #define	ERROR_INTR	7
     84 #define	HARDCLOCK	8
     85 #define	FPU_INTR	9
     86 #define	SLOT0_INTR	10
     87 #define	SLOT1_INTR	11
     88 #define	SLOT2_INTR	12
     89 #define	DTOP_INTR	13
     90 #define	ISDN_INTR	14
     91 #define	FLOPPY_INTR	15
     92 #define	STRAY_INTR	16
     93 
     94 /* handle i/o device interrupts */
     95 extern int (*mips_hardware_intr) __P((unsigned, unsigned, unsigned, unsigned));
     96 
     97 #endif /* !_LOCORE */
     98 #endif /* _KERNEL */
     99 
    100 #endif /* !_PMAX_INTR_H_ */
    101