intr.h revision 1.7 1 /* $NetBSD: intr.h,v 1.7 1999/05/31 07:42:57 nisimura Exp $ */
2
3 /*
4 * Copyright (c) 1998 Jonathan Stone. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Jonathan Stone for
17 * the NetBSD Project.
18 * 4. The name of the author may not be used to endorse or promote products
19 * derived from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #ifndef _PMAX_INTR_H_
34 #define _PMAX_INTR_H_
35
36 #define IPL_NONE 0 /* disable only this interrupt */
37 #define IPL_BIO 1 /* disable block I/O interrupts */
38 #define IPL_NET 2 /* disable network interrupts */
39 #define IPL_TTY 3 /* disable terminal interrupts */
40 #define IPL_CLOCK 4 /* disable clock interrupts */
41 #define IPL_STATCLOCK 5 /* disable profiling interrupts */
42 #define IPL_SERIAL 6 /* disable serial hardware interrupts */
43 #define IPL_DMA 7 /* disable DMA reload interrupts */
44 #define IPL_HIGH 8 /* disable all interrupts */
45
46 #ifdef _KERNEL
47 #ifndef _LOCORE
48
49 #include <mips/cpuregs.h>
50
51 extern int _splraise __P((int));
52 extern int _spllower __P((int));
53 extern int _splset __P((int));
54 extern int _splget __P((void));
55 extern void _splnone __P((void));
56 extern void _setsoftintr __P((int));
57 extern void _clrsoftintr __P((int));
58
59 #define setsoftclock() _setsoftintr(MIPS_SOFT_INT_MASK_0)
60 #define setsoftnet() _setsoftintr(MIPS_SOFT_INT_MASK_1)
61 #define clearsoftclock() _clrsoftintr(MIPS_SOFT_INT_MASK_0)
62 #define clearsoftnet() _clrsoftintr(MIPS_SOFT_INT_MASK_1)
63
64 #define splhigh() _splraise(MIPS_INT_MASK)
65 #define spl0() (void)_spllower(0)
66 #define splx(s) (void)_splset(s)
67 #define splbio() (_splraise(splvec.splbio))
68 #define splnet() (_splraise(splvec.splnet))
69 #define spltty() (_splraise(splvec.spltty))
70 #define splimp() (_splraise(splvec.splimp))
71 #define splpmap() (_splraise(splvec.splimp))
72 #define splclock() (_splraise(splvec.splclock))
73 #define splstatclock() (_splraise(splvec.splstatclock))
74 #define splsoftclock() _spllower(MIPS_SOFT_INT_MASK_0)
75 #define splsoftnet() _splraise(MIPS_SOFT_INT_MASK_1)
76
77 struct splvec {
78 int splbio;
79 int splnet;
80 int spltty;
81 int splimp;
82 int splclock;
83 int splstatclock;
84 };
85 extern struct splvec splvec;
86
87 /* Conventionals ... */
88
89 #define MIPS_SPLHIGH (MIPS_INT_MASK)
90 #define MIPS_SPL0 (MIPS_INT_MASK_0|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1)
91 #define MIPS_SPL1 (MIPS_INT_MASK_1|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1)
92 #define MIPS_SPL3 (MIPS_INT_MASK_3|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1)
93 #define MIPS_SPL_0_1 (MIPS_INT_MASK_1|MIPS_SPL0)
94 #define MIPS_SPL_0_1_2 (MIPS_INT_MASK_2|MIPS_SPL_0_1)
95 #define MIPS_SPL_0_1_3 (MIPS_INT_MASK_3|MIPS_SPL_0_1)
96 #define MIPS_SPL_0_1_2_3 (MIPS_INT_MASK_3|MIPS_SPL_0_1_2)
97
98 /*
99 * Index into intrcnt[], which is defined in locore
100 */
101 extern u_long intrcnt[];
102
103 #define SOFTCLOCK_INTR 0
104 #define SOFTNET_INTR 1
105 #define SERIAL0_INTR 2
106 #define SERIAL1_INTR 3
107 #define SERIAL2_INTR 4
108 #define LANCE_INTR 5
109 #define SCSI_INTR 6
110 #define ERROR_INTR 7
111 #define HARDCLOCK 8
112 #define FPU_INTR 9
113 #define SLOT0_INTR 10
114 #define SLOT1_INTR 11
115 #define SLOT2_INTR 12
116 #define DTOP_INTR 13
117 #define ISDN_INTR 14
118 #define FLOPPY_INTR 15
119 #define STRAY_INTR 16
120
121 /* handle i/o device interrupts */
122 extern int (*mips_hardware_intr) __P((unsigned, unsigned, unsigned, unsigned));
123
124 #endif /* !_LOCORE */
125 #endif /* _KERNEL */
126
127 #endif /* !_PMAX_INTR_H_ */
128