dec_3min.c revision 1.17
1/* $NetBSD: dec_3min.c,v 1.17 1999/05/25 07:37:08 nisimura Exp $ */ 2 3/* 4 * Copyright (c) 1998 Jonathan Stone. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Jonathan Stone for 17 * the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Copyright (c) 1988 University of Utah. 35 * Copyright (c) 1992, 1993 36 * The Regents of the University of California. All rights reserved. 37 * 38 * This code is derived from software contributed to Berkeley by 39 * the Systems Programming Group of the University of Utah Computer 40 * Science Department, The Mach Operating System project at 41 * Carnegie-Mellon University and Ralph Campbell. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by the University of 54 * California, Berkeley and its contributors. 55 * 4. Neither the name of the University nor the names of its contributors 56 * may be used to endorse or promote products derived from this software 57 * without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 61 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 62 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 63 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 64 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 65 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69 * SUCH DAMAGE. 70 * 71 * @(#)machdep.c 8.3 (Berkeley) 1/12/94 72 */ 73 74#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 75 76__KERNEL_RCSID(0, "$NetBSD: dec_3min.c,v 1.17 1999/05/25 07:37:08 nisimura Exp $"); 77 78 79#include <sys/types.h> 80#include <sys/systm.h> 81 82#include <machine/cpu.h> 83#include <machine/intr.h> 84#include <machine/reg.h> 85#include <machine/psl.h> 86#include <machine/autoconf.h> /* intr_arg_t */ 87#include <machine/sysconf.h> 88 89#include <mips/mips_param.h> /* hokey spl()s */ 90#include <mips/mips/mips_mcclock.h> /* mcclock CPUspeed estimation */ 91 92/* all these to get ioasic_base */ 93#include <sys/device.h> /* struct cfdata for.. */ 94#include <dev/tc/tcvar.h> /* tc type definitions for.. */ 95#include <dev/tc/ioasicreg.h> /* ioasic interrrupt masks */ 96#include <dev/tc/ioasicvar.h> /* ioasic_base */ 97 98#include <pmax/pmax/clockreg.h> 99#include <pmax/pmax/turbochannel.h> 100#include <pmax/pmax/pmaxtype.h> 101 102#include <pmax/pmax/machdep.h> /* XXXjrs replace with vectors */ 103 104#include <pmax/pmax/kmin.h> /* 3min baseboard addresses */ 105#include <pmax/pmax/memc.h> /* 3min/maxine memory errors */ 106 107 108/* 109 * forward declarations 110 */ 111void dec_3min_init __P((void)); 112void dec_3min_os_init __P((void)); 113void dec_3min_bus_reset __P((void)); 114void dec_3maxplus_device_register __P((struct device *, void *)); 115 116void dec_3min_enable_intr 117 __P ((u_int slotno, int (*handler) __P((intr_arg_t sc)), 118 intr_arg_t sc, int onoff)); 119int dec_3min_intr __P((unsigned, unsigned, unsigned, unsigned)); 120void dec_3min_device_register __P((struct device *, void *)); 121void dec_3min_cons_init __P((void)); 122 123 124/* 125 * Local declarations. 126 */ 127void dec_3min_mcclock_cpuspeed __P((volatile struct chiptime *mcclock_addr, 128 int clockmask)); 129u_long kmin_tc3_imask; 130 131void kn02ba_wbflush __P((void)); 132unsigned kn02ba_clkread __P((void)); 133extern unsigned (*clkread) __P((void)); 134 135/* 136 * Fill in platform struct. 137 */ 138void 139dec_3min_init() 140{ 141 platform.iobus = "tc3min"; 142 143 platform.os_init = dec_3min_os_init; 144 platform.bus_reset = dec_3min_bus_reset; 145 platform.cons_init = dec_3min_cons_init; 146 platform.device_register = dec_3min_device_register; 147 148 dec_3min_os_init(); 149 150 sprintf(cpu_model, "DECstation 5000/1%d (3MIN)", cpu_mhz); 151} 152 153 154/* 155 * Initalize the memory system and I/O buses. 156 */ 157void 158dec_3min_bus_reset() 159{ 160 161 /* 162 * Reset interrupts, clear any errors from newconf probes 163 */ 164 165 *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0; 166 kn02ba_wbflush(); 167 168 *(u_int32_t *)(ioasic_base + IOASIC_INTR) = 0; 169 kn02ba_wbflush(); 170} 171 172 173void 174dec_3min_os_init() 175{ 176 ioasic_base = MIPS_PHYS_TO_KSEG1(KMIN_SYS_ASIC); 177 mips_hardware_intr = dec_3min_intr; 178 tc_enable_interrupt = dec_3min_enable_intr; /* XXX */ 179 mcclock_addr = (void *)(ioasic_base + IOASIC_SLOT_8_START); 180 181 /* R4000 3MIN can ultilize on-chip counter */ 182 clkread = kn02ba_clkread; 183 184 /* 185 * All the baseboard interrupts come through the I/O ASIC 186 * (at INT_MASK_3), so it has to be turned off for all the spls. 187 * Since we don't know what kinds of devices are in the 188 * turbochannel option slots, just block them all. 189 */ 190 splvec.splbio = MIPS_SPL_0_1_2_3; 191 splvec.splnet = MIPS_SPL_0_1_2_3; 192 splvec.spltty = MIPS_SPL_0_1_2_3; 193 splvec.splimp = MIPS_SPL_0_1_2_3; 194 splvec.splclock = MIPS_SPL_0_1_2_3; 195 splvec.splstatclock = MIPS_SPL_0_1_2_3; 196 197 dec_3min_mcclock_cpuspeed(mcclock_addr, MIPS_INT_MASK_3); 198 199 *(u_int32_t *)(ioasic_base + IOASIC_LANCE_DECODE) = 0x3; 200 *(u_int32_t *)(ioasic_base + IOASIC_SCSI_DECODE) = 0xe; 201#if 0 202 *(u_int32_t *)(ioasic_base + IOASIC_SCC0_DECODE) = (0x10|4); 203 *(u_int32_t *)(ioasic_base + IOASIC_SCC1_DECODE) = (0x10|6); 204 *(u_int32_t *)(ioasic_base + IOASIC_CSR) = 0x00000f00; 205#endif 206 /* 207 * Initialize interrupts. 208 */ 209 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = KMIN_IM0; 210 *(u_int32_t *)(ioasic_base + IOASIC_INTR) = 0; 211 212 /* 213 * The kmin memory hardware seems to wrap memory addresses 214 * with 4Mbyte SIMMs, which causes the physmem computation 215 * to lose. Find out how big the SIMMS are and set 216 * max_ physmem accordingly. 217 */ 218 physmem_boardmax = KMIN_PHYS_MEMORY_END + 1; 219 if ((*(int *)(MIPS_PHYS_TO_KSEG1(KMIN_REG_MSR)) & 220 KMIN_MSR_SIZE_16Mb) == 0) 221 physmem_boardmax = physmem_boardmax >> 2; 222 physmem_boardmax = MIPS_PHYS_TO_KSEG1(physmem_boardmax); 223 224 /* clear any memory errors from probes */ 225 *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0; 226 kn02ba_wbflush(); 227 228 kmin_tc3_imask = 229 (KMIN_INTR_CLOCK | KMIN_INTR_PSWARN | KMIN_INTR_TIMEOUT); 230 231 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = 232 kmin_tc3_imask | 233 (KMIN_IM0 & ~(KN03_INTR_TC_0|KN03_INTR_TC_1|KN03_INTR_TC_2)); 234} 235 236 237void 238dec_3min_cons_init() 239{ 240 /* notyet */ 241} 242 243 244void 245dec_3min_device_register(dev, aux) 246 struct device *dev; 247 void *aux; 248{ 249 panic("dec_3min_device_register unimplemented"); 250} 251 252 253void 254dec_3min_enable_intr(slotno, handler, sc, on) 255 unsigned int slotno; 256 int (*handler) __P((void* softc)); 257 void *sc; 258 int on; 259{ 260 unsigned mask; 261 262 switch (slotno) { 263 /* slots 0-2 don't interrupt through the IOASIC. */ 264 case 0: 265 mask = MIPS_INT_MASK_0; break; 266 case 1: 267 mask = MIPS_INT_MASK_1; break; 268 case 2: 269 mask = MIPS_INT_MASK_2; break; 270 271 case KMIN_SCSI_SLOT: 272 mask = (IOASIC_INTR_SCSI | IOASIC_INTR_SCSI_PTR_LOAD | 273 IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E); 274 break; 275 276 case KMIN_LANCE_SLOT: 277 mask = KMIN_INTR_LANCE; 278 break; 279 case KMIN_SCC0_SLOT: 280 mask = KMIN_INTR_SCC_0; 281 break; 282 case KMIN_SCC1_SLOT: 283 mask = KMIN_INTR_SCC_1; 284 break; 285 case KMIN_ASIC_SLOT: 286 mask = KMIN_INTR_ASIC; 287 break; 288 default: 289 return; 290 } 291 292#if defined(DEBUG) || defined(DIAGNOSTIC) 293 printf("3MIN: imask %lx, %sabling slot %d, sc %p handler %p\n", 294 kmin_tc3_imask, (on? "en" : "dis"), slotno, sc, handler); 295#endif 296 297 /* 298 * Enable the interrupt handler, and if it's an IOASIC 299 * slot, set the IOASIC interrupt mask. 300 * Otherwise, set the appropriate spl level in the R3000 301 * register. 302 * Be careful to set handlers before enabling, and disable 303 * interrupts before clearing handlers. 304 */ 305 306 if (on) { 307 /* Set the interrupt handler and argument ... */ 308 tc_slot_info[slotno].intr = handler; 309 tc_slot_info[slotno].sc = sc; 310 311 /* ... and set the relevant mask */ 312 if (slotno <= 2) { 313 /* it's an option slot */ 314 int s = splhigh(); 315 s |= mask; 316 splx(s); 317 } else { 318 /* it's a baseboard device going via the ASIC */ 319 kmin_tc3_imask |= mask; 320 } 321 } else { 322 /* Clear the relevant mask... */ 323 if (slotno <= 2) { 324 /* it's an option slot */ 325 int s = splhigh(); 326 printf("kmin_intr: cannot disable option slot %d\n", 327 slotno); 328 s &= ~mask; 329 splx(s); 330 } else { 331 /* it's a baseboard device going via the ASIC */ 332 kmin_tc3_imask &= ~mask; 333 } 334 /* ... and clear the handler */ 335 tc_slot_info[slotno].intr = 0; 336 tc_slot_info[slotno].sc = 0; 337 } 338} 339 340 341 342/* 343 * 3min hardware interrupts. (DECstation 5000/1xx) 344 */ 345int 346dec_3min_intr(cpumask, pc, status, cause) 347 unsigned cpumask; 348 unsigned pc; 349 unsigned status; 350 unsigned cause; 351{ 352 static int user_warned = 0; 353 static int intr_depth = 0; 354 u_int32_t old_mask; 355 356 intr_depth++; 357 old_mask = *(u_int32_t *)(ioasic_base + IOASIC_IMSK); 358 359 if (cpumask & MIPS_INT_MASK_4) 360 prom_haltbutton(); 361 362 if (cpumask & MIPS_INT_MASK_3) { 363 /* NB: status & MIPS_INT_MASK3 must also be set */ 364 /* masked interrupts are still observable */ 365 u_int32_t intr, imsk, turnoff; 366 367 turnoff = 0; 368 intr = *(u_int32_t *)(ioasic_base + IOASIC_INTR); 369 imsk = *(u_int32_t *)(ioasic_base + IOASIC_IMSK); 370 intr &= imsk; 371 372 if (intr & IOASIC_INTR_SCSI_PTR_LOAD) { 373 turnoff |= IOASIC_INTR_SCSI_PTR_LOAD; 374#ifdef notdef 375 asc_dma_intr(); 376#endif 377 } 378 379 if (intr & (IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E)) 380 turnoff |= IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E; 381 382 if (intr & IOASIC_INTR_LANCE_READ_E) 383 turnoff |= IOASIC_INTR_LANCE_READ_E; 384 385 if (turnoff) 386 *(u_int32_t *)(ioasic_base + IOASIC_INTR) = ~turnoff; 387 388 if (intr & KMIN_INTR_TIMEOUT) 389 kn02ba_errintr(); 390 391 if (intr & KMIN_INTR_CLOCK) { 392 struct clockframe cf; 393 struct chiptime *clk; 394 volatile int temp; 395 extern u_int32_t mips3_cycle_count __P((void)); 396 397 clk = (void *)(ioasic_base + IOASIC_SLOT_8_START); 398 temp = clk->regc; /* XXX clear interrupt bits */ 399 400#ifdef MIPS3 401 if (CPUISMIPS3) { 402 latched_cycle_cnt = mips3_cycle_count(); 403 } 404#endif 405 cf.pc = pc; 406 cf.sr = status; 407 hardclock(&cf); 408 intrcnt[HARDCLOCK]++; 409 } 410 411 /* If clock interrups were enabled, re-enable them ASAP. */ 412 if (old_mask & KMIN_INTR_CLOCK) { 413 /* ioctl interrupt mask to splclock and higher */ 414 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) 415 = old_mask & 416 ~(KMIN_INTR_SCC_0|KMIN_INTR_SCC_1 | 417 IOASIC_INTR_LANCE|IOASIC_INTR_SCSI); 418 kn02ba_wbflush(); 419 _splset(MIPS_SR_INT_IE | (status & MIPS_INT_MASK_3)); 420 } 421 422 if (intr_depth > 1) 423 goto done; 424 425 if ((intr & KMIN_INTR_SCC_0) && 426 tc_slot_info[KMIN_SCC0_SLOT].intr) { 427 (*(tc_slot_info[KMIN_SCC0_SLOT].intr)) 428 (tc_slot_info[KMIN_SCC0_SLOT].sc); 429 intrcnt[SERIAL0_INTR]++; 430 } 431 432 if ((intr & KMIN_INTR_SCC_1) && 433 tc_slot_info[KMIN_SCC1_SLOT].intr) { 434 (*(tc_slot_info[KMIN_SCC1_SLOT].intr)) 435 (tc_slot_info[KMIN_SCC1_SLOT].sc); 436 intrcnt[SERIAL1_INTR]++; 437 } 438 439#ifdef notyet /* untested */ 440 /* If tty interrupts were enabled, re-enable them ASAP. */ 441 if ((old_mask & (KMIN_INTR_SCC_1|KMIN_INTR_SCC_0)) == 442 (KMIN_INTR_SCC_1|KMIN_INTR_SCC_0)) { 443 *imaskp = old_mask & 444 ~(KMIN_INTR_SCC_0|KMIN_INTR_SCC_1 | 445 IOASIC_INTR_LANCE|IOASIC_INTR_SCSI); 446 kn02ba_wbflush(); 447 } 448 449 /* XXX until we know about SPLs of TC options. */ 450 if (intr_depth > 1) 451 goto done; 452#endif 453 if ((intr & IOASIC_INTR_LANCE) && 454 tc_slot_info[KMIN_LANCE_SLOT].intr) { 455 (*(tc_slot_info[KMIN_LANCE_SLOT].intr)) 456 (tc_slot_info[KMIN_LANCE_SLOT].sc); 457 intrcnt[LANCE_INTR]++; 458 } 459 460 if ((intr & IOASIC_INTR_SCSI) && 461 tc_slot_info[KMIN_SCSI_SLOT].intr) { 462 (*(tc_slot_info[KMIN_SCSI_SLOT].intr)) 463 (tc_slot_info[KMIN_SCSI_SLOT].sc); 464 intrcnt[SCSI_INTR]++; 465 } 466 467 if (user_warned && ((intr & KMIN_INTR_PSWARN) == 0)) { 468 printf("%s\n", "Power supply ok now."); 469 user_warned = 0; 470 } 471 if ((intr & KMIN_INTR_PSWARN) && (user_warned < 3)) { 472 user_warned++; 473 printf("%s\n", "Power supply overheating"); 474 } 475 } 476 if ((cpumask & MIPS_INT_MASK_0) && tc_slot_info[0].intr) { 477 (*tc_slot_info[0].intr)(tc_slot_info[0].sc); 478 intrcnt[SLOT0_INTR]++; 479 } 480 481 if ((cpumask & MIPS_INT_MASK_1) && tc_slot_info[1].intr) { 482 (*tc_slot_info[1].intr)(tc_slot_info[1].sc); 483 intrcnt[SLOT1_INTR]++; 484 } 485 if ((cpumask & MIPS_INT_MASK_2) && tc_slot_info[2].intr) { 486 (*tc_slot_info[2].intr)(tc_slot_info[2].sc); 487 intrcnt[SLOT2_INTR]++; 488 } 489 490done: 491 /* restore entry state */ 492 splhigh(); 493 intr_depth--; 494 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = old_mask; 495 496 497 return (MIPS_SR_INT_IE | (status & ~cause & MIPS_HARD_INT_MASK)); 498} 499 500 501 502/* 503 ************************************************************************ 504 * Extra functions 505 ************************************************************************ 506 */ 507 508 509 510 511/* 512 * Count instructions between 4ms mcclock interrupt requests, 513 * using the ioasic clock-interrupt-pending bit to determine 514 * when clock ticks occur. 515 * Set up iosiac to allow only clock interrupts, then 516 * call 517 */ 518void 519dec_3min_mcclock_cpuspeed(mcclock_addr, clockmask) 520 volatile struct chiptime *mcclock_addr; 521 int clockmask; 522{ 523 u_int32_t saved_imask; 524 525 saved_imask = *(u_int32_t *)(ioasic_base + IOASIC_IMSK); 526 527 /* Allow only clock interrupts through ioasic. */ 528 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = KMIN_INTR_CLOCK; 529 kn02ba_wbflush(); 530 531 mc_cpuspeed(mcclock_addr, clockmask); 532 533 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = saved_imask; 534 kn02ba_wbflush(); 535} 536 537void 538kn02ba_wbflush() 539{ 540 /* read twice IOASIC_INTR register */ 541 __asm __volatile("lw $0,0xbc040120; lw $0,0xbc040120"); 542} 543 544unsigned 545kn02ba_clkread() 546{ 547#ifdef MIPS3 548 extern u_int32_t mips3_cycle_count __P((void)); 549 extern u_long latched_cycle_cnt; 550 551 if (CPUISMIPS3) { 552 u_int32_t mips3_cycles; 553 554 mips3_cycles = mips3_cycle_count() - latched_cycle_cnt; 555#if 0 556 /* XXX divides take 78 cycles: approximate with * 41/2048 */ 557 return (mips3_cycles / cpu_mhz); 558#else 559 return((mips3_cycles >> 6) + (mips3_cycles >> 8) + 560 (mips3_cycles >> 11)); 561#endif 562 } 563#endif 564 return 0; 565} 566