dec_3min.c revision 1.18
1/* $NetBSD: dec_3min.c,v 1.18 1999/05/26 04:23:59 nisimura Exp $ */ 2 3/* 4 * Copyright (c) 1998 Jonathan Stone. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Jonathan Stone for 17 * the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Copyright (c) 1988 University of Utah. 35 * Copyright (c) 1992, 1993 36 * The Regents of the University of California. All rights reserved. 37 * 38 * This code is derived from software contributed to Berkeley by 39 * the Systems Programming Group of the University of Utah Computer 40 * Science Department, The Mach Operating System project at 41 * Carnegie-Mellon University and Ralph Campbell. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by the University of 54 * California, Berkeley and its contributors. 55 * 4. Neither the name of the University nor the names of its contributors 56 * may be used to endorse or promote products derived from this software 57 * without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 61 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 62 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 63 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 64 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 65 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69 * SUCH DAMAGE. 70 * 71 * @(#)machdep.c 8.3 (Berkeley) 1/12/94 72 */ 73 74#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 75 76__KERNEL_RCSID(0, "$NetBSD: dec_3min.c,v 1.18 1999/05/26 04:23:59 nisimura Exp $"); 77 78 79#include <sys/types.h> 80#include <sys/systm.h> 81 82#include <machine/cpu.h> 83#include <machine/intr.h> 84#include <machine/reg.h> 85#include <machine/psl.h> 86#include <machine/autoconf.h> /* intr_arg_t */ 87#include <machine/sysconf.h> 88 89#include <mips/mips_param.h> /* hokey spl()s */ 90#include <mips/mips/mips_mcclock.h> /* mcclock CPUspeed estimation */ 91 92/* all these to get ioasic_base */ 93#include <sys/device.h> /* struct cfdata for.. */ 94#include <dev/tc/tcvar.h> /* tc type definitions for.. */ 95#include <dev/tc/ioasicreg.h> /* ioasic interrrupt masks */ 96#include <dev/tc/ioasicvar.h> /* ioasic_base */ 97 98#include <pmax/pmax/clockreg.h> 99#include <pmax/pmax/turbochannel.h> 100#include <pmax/pmax/pmaxtype.h> 101 102#include <pmax/pmax/kmin.h> /* 3min baseboard addresses */ 103#include <pmax/pmax/memc.h> /* 3min/maxine memory errors */ 104 105 106/* 107 * forward declarations 108 */ 109void dec_3min_init __P((void)); 110void dec_3min_os_init __P((void)); 111void dec_3min_bus_reset __P((void)); 112void dec_3maxplus_device_register __P((struct device *, void *)); 113 114void dec_3min_enable_intr 115 __P ((u_int slotno, int (*handler) __P((intr_arg_t sc)), 116 intr_arg_t sc, int onoff)); 117int dec_3min_intr __P((unsigned, unsigned, unsigned, unsigned)); 118void dec_3min_device_register __P((struct device *, void *)); 119void dec_3min_cons_init __P((void)); 120 121 122/* 123 * Local declarations. 124 */ 125void dec_3min_mcclock_cpuspeed __P((volatile struct chiptime *mcclock_addr, 126 int clockmask)); 127u_long kmin_tc3_imask; 128 129static unsigned latched_cycle_cnt; 130 131void kn02ba_wbflush __P((void)); 132unsigned kn02ba_clkread __P((void)); 133extern unsigned (*clkread) __P((void)); 134extern void prom_haltbutton __P((void)); 135 136extern volatile struct chiptime *mcclock_addr; /* XXX */ 137extern char cpu_model[]; 138extern int physmem_boardmax; 139 140#ifdef MIPS3 141extern u_int32_t mips3_cycle_count __P((void)); 142#endif 143 144 145/* 146 * Fill in platform struct. 147 */ 148void 149dec_3min_init() 150{ 151 platform.iobus = "tc3min"; 152 153 platform.os_init = dec_3min_os_init; 154 platform.bus_reset = dec_3min_bus_reset; 155 platform.cons_init = dec_3min_cons_init; 156 platform.device_register = dec_3min_device_register; 157 158 dec_3min_os_init(); 159 160 sprintf(cpu_model, "DECstation 5000/1%d (3MIN)", cpu_mhz); 161} 162 163 164/* 165 * Initalize the memory system and I/O buses. 166 */ 167void 168dec_3min_bus_reset() 169{ 170 171 /* 172 * Reset interrupts, clear any errors from newconf probes 173 */ 174 175 *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0; 176 kn02ba_wbflush(); 177 178 *(u_int32_t *)(ioasic_base + IOASIC_INTR) = 0; 179 kn02ba_wbflush(); 180} 181 182 183void 184dec_3min_os_init() 185{ 186 ioasic_base = MIPS_PHYS_TO_KSEG1(KMIN_SYS_ASIC); 187 mips_hardware_intr = dec_3min_intr; 188 tc_enable_interrupt = dec_3min_enable_intr; /* XXX */ 189 mcclock_addr = (void *)(ioasic_base + IOASIC_SLOT_8_START); 190 191 /* R4000 3MIN can ultilize on-chip counter */ 192 clkread = kn02ba_clkread; 193 194 /* 195 * All the baseboard interrupts come through the I/O ASIC 196 * (at INT_MASK_3), so it has to be turned off for all the spls. 197 * Since we don't know what kinds of devices are in the 198 * turbochannel option slots, just block them all. 199 */ 200 splvec.splbio = MIPS_SPL_0_1_2_3; 201 splvec.splnet = MIPS_SPL_0_1_2_3; 202 splvec.spltty = MIPS_SPL_0_1_2_3; 203 splvec.splimp = MIPS_SPL_0_1_2_3; 204 splvec.splclock = MIPS_SPL_0_1_2_3; 205 splvec.splstatclock = MIPS_SPL_0_1_2_3; 206 207 dec_3min_mcclock_cpuspeed(mcclock_addr, MIPS_INT_MASK_3); 208 209 *(u_int32_t *)(ioasic_base + IOASIC_LANCE_DECODE) = 0x3; 210 *(u_int32_t *)(ioasic_base + IOASIC_SCSI_DECODE) = 0xe; 211#if 0 212 *(u_int32_t *)(ioasic_base + IOASIC_SCC0_DECODE) = (0x10|4); 213 *(u_int32_t *)(ioasic_base + IOASIC_SCC1_DECODE) = (0x10|6); 214 *(u_int32_t *)(ioasic_base + IOASIC_CSR) = 0x00000f00; 215#endif 216 /* 217 * Initialize interrupts. 218 */ 219 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = KMIN_IM0; 220 *(u_int32_t *)(ioasic_base + IOASIC_INTR) = 0; 221 222 /* 223 * The kmin memory hardware seems to wrap memory addresses 224 * with 4Mbyte SIMMs, which causes the physmem computation 225 * to lose. Find out how big the SIMMS are and set 226 * max_ physmem accordingly. 227 */ 228 physmem_boardmax = KMIN_PHYS_MEMORY_END + 1; 229 if ((*(int *)(MIPS_PHYS_TO_KSEG1(KMIN_REG_MSR)) & 230 KMIN_MSR_SIZE_16Mb) == 0) 231 physmem_boardmax = physmem_boardmax >> 2; 232 physmem_boardmax = MIPS_PHYS_TO_KSEG1(physmem_boardmax); 233 234 /* clear any memory errors from probes */ 235 *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0; 236 kn02ba_wbflush(); 237 238 kmin_tc3_imask = 239 (KMIN_INTR_CLOCK | KMIN_INTR_PSWARN | KMIN_INTR_TIMEOUT); 240 241 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = 242 kmin_tc3_imask | 243 (KMIN_IM0 & ~(KN03_INTR_TC_0|KN03_INTR_TC_1|KN03_INTR_TC_2)); 244} 245 246 247void 248dec_3min_cons_init() 249{ 250 /* notyet */ 251} 252 253 254void 255dec_3min_device_register(dev, aux) 256 struct device *dev; 257 void *aux; 258{ 259 panic("dec_3min_device_register unimplemented"); 260} 261 262 263void 264dec_3min_enable_intr(slotno, handler, sc, on) 265 unsigned int slotno; 266 int (*handler) __P((void* softc)); 267 void *sc; 268 int on; 269{ 270 unsigned mask; 271 272 switch (slotno) { 273 /* slots 0-2 don't interrupt through the IOASIC. */ 274 case 0: 275 mask = MIPS_INT_MASK_0; break; 276 case 1: 277 mask = MIPS_INT_MASK_1; break; 278 case 2: 279 mask = MIPS_INT_MASK_2; break; 280 281 case KMIN_SCSI_SLOT: 282 mask = (IOASIC_INTR_SCSI | IOASIC_INTR_SCSI_PTR_LOAD | 283 IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E); 284 break; 285 286 case KMIN_LANCE_SLOT: 287 mask = KMIN_INTR_LANCE; 288 break; 289 case KMIN_SCC0_SLOT: 290 mask = KMIN_INTR_SCC_0; 291 break; 292 case KMIN_SCC1_SLOT: 293 mask = KMIN_INTR_SCC_1; 294 break; 295 case KMIN_ASIC_SLOT: 296 mask = KMIN_INTR_ASIC; 297 break; 298 default: 299 return; 300 } 301 302#if defined(DEBUG) || defined(DIAGNOSTIC) 303 printf("3MIN: imask %lx, %sabling slot %d, sc %p handler %p\n", 304 kmin_tc3_imask, (on? "en" : "dis"), slotno, sc, handler); 305#endif 306 307 /* 308 * Enable the interrupt handler, and if it's an IOASIC 309 * slot, set the IOASIC interrupt mask. 310 * Otherwise, set the appropriate spl level in the R3000 311 * register. 312 * Be careful to set handlers before enabling, and disable 313 * interrupts before clearing handlers. 314 */ 315 316 if (on) { 317 /* Set the interrupt handler and argument ... */ 318 tc_slot_info[slotno].intr = handler; 319 tc_slot_info[slotno].sc = sc; 320 321 /* ... and set the relevant mask */ 322 if (slotno <= 2) { 323 /* it's an option slot */ 324 int s = splhigh(); 325 s |= mask; 326 splx(s); 327 } else { 328 /* it's a baseboard device going via the ASIC */ 329 kmin_tc3_imask |= mask; 330 } 331 } else { 332 /* Clear the relevant mask... */ 333 if (slotno <= 2) { 334 /* it's an option slot */ 335 int s = splhigh(); 336 printf("kmin_intr: cannot disable option slot %d\n", 337 slotno); 338 s &= ~mask; 339 splx(s); 340 } else { 341 /* it's a baseboard device going via the ASIC */ 342 kmin_tc3_imask &= ~mask; 343 } 344 /* ... and clear the handler */ 345 tc_slot_info[slotno].intr = 0; 346 tc_slot_info[slotno].sc = 0; 347 } 348} 349 350 351 352/* 353 * 3min hardware interrupts. (DECstation 5000/1xx) 354 */ 355int 356dec_3min_intr(cpumask, pc, status, cause) 357 unsigned cpumask; 358 unsigned pc; 359 unsigned status; 360 unsigned cause; 361{ 362 static int user_warned = 0; 363 static int intr_depth = 0; 364 u_int32_t old_mask; 365 366 intr_depth++; 367 old_mask = *(u_int32_t *)(ioasic_base + IOASIC_IMSK); 368 369 if (cpumask & MIPS_INT_MASK_4) 370 prom_haltbutton(); 371 372 if (cpumask & MIPS_INT_MASK_3) { 373 /* NB: status & MIPS_INT_MASK3 must also be set */ 374 /* masked interrupts are still observable */ 375 u_int32_t intr, imsk, turnoff; 376 377 turnoff = 0; 378 intr = *(u_int32_t *)(ioasic_base + IOASIC_INTR); 379 imsk = *(u_int32_t *)(ioasic_base + IOASIC_IMSK); 380 intr &= imsk; 381 382 if (intr & IOASIC_INTR_SCSI_PTR_LOAD) { 383 turnoff |= IOASIC_INTR_SCSI_PTR_LOAD; 384#ifdef notdef 385 asc_dma_intr(); 386#endif 387 } 388 389 if (intr & (IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E)) 390 turnoff |= IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E; 391 392 if (intr & IOASIC_INTR_LANCE_READ_E) 393 turnoff |= IOASIC_INTR_LANCE_READ_E; 394 395 if (turnoff) 396 *(u_int32_t *)(ioasic_base + IOASIC_INTR) = ~turnoff; 397 398 if (intr & KMIN_INTR_TIMEOUT) 399 kn02ba_errintr(); 400 401 if (intr & KMIN_INTR_CLOCK) { 402 struct clockframe cf; 403 struct chiptime *clk; 404 volatile int temp; 405 406 clk = (void *)(ioasic_base + IOASIC_SLOT_8_START); 407 temp = clk->regc; /* XXX clear interrupt bits */ 408 409#ifdef MIPS3 410 if (CPUISMIPS3) { 411 latched_cycle_cnt = mips3_cycle_count(); 412 } 413#endif 414 cf.pc = pc; 415 cf.sr = status; 416 hardclock(&cf); 417 intrcnt[HARDCLOCK]++; 418 } 419 420 /* If clock interrups were enabled, re-enable them ASAP. */ 421 if (old_mask & KMIN_INTR_CLOCK) { 422 /* ioctl interrupt mask to splclock and higher */ 423 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) 424 = old_mask & 425 ~(KMIN_INTR_SCC_0|KMIN_INTR_SCC_1 | 426 IOASIC_INTR_LANCE|IOASIC_INTR_SCSI); 427 kn02ba_wbflush(); 428 _splset(MIPS_SR_INT_IE | (status & MIPS_INT_MASK_3)); 429 } 430 431 if (intr_depth > 1) 432 goto done; 433 434 if ((intr & KMIN_INTR_SCC_0) && 435 tc_slot_info[KMIN_SCC0_SLOT].intr) { 436 (*(tc_slot_info[KMIN_SCC0_SLOT].intr)) 437 (tc_slot_info[KMIN_SCC0_SLOT].sc); 438 intrcnt[SERIAL0_INTR]++; 439 } 440 441 if ((intr & KMIN_INTR_SCC_1) && 442 tc_slot_info[KMIN_SCC1_SLOT].intr) { 443 (*(tc_slot_info[KMIN_SCC1_SLOT].intr)) 444 (tc_slot_info[KMIN_SCC1_SLOT].sc); 445 intrcnt[SERIAL1_INTR]++; 446 } 447 448#ifdef notyet /* untested */ 449 /* If tty interrupts were enabled, re-enable them ASAP. */ 450 if ((old_mask & (KMIN_INTR_SCC_1|KMIN_INTR_SCC_0)) == 451 (KMIN_INTR_SCC_1|KMIN_INTR_SCC_0)) { 452 *imaskp = old_mask & 453 ~(KMIN_INTR_SCC_0|KMIN_INTR_SCC_1 | 454 IOASIC_INTR_LANCE|IOASIC_INTR_SCSI); 455 kn02ba_wbflush(); 456 } 457 458 /* XXX until we know about SPLs of TC options. */ 459 if (intr_depth > 1) 460 goto done; 461#endif 462 if ((intr & IOASIC_INTR_LANCE) && 463 tc_slot_info[KMIN_LANCE_SLOT].intr) { 464 (*(tc_slot_info[KMIN_LANCE_SLOT].intr)) 465 (tc_slot_info[KMIN_LANCE_SLOT].sc); 466 intrcnt[LANCE_INTR]++; 467 } 468 469 if ((intr & IOASIC_INTR_SCSI) && 470 tc_slot_info[KMIN_SCSI_SLOT].intr) { 471 (*(tc_slot_info[KMIN_SCSI_SLOT].intr)) 472 (tc_slot_info[KMIN_SCSI_SLOT].sc); 473 intrcnt[SCSI_INTR]++; 474 } 475 476 if (user_warned && ((intr & KMIN_INTR_PSWARN) == 0)) { 477 printf("%s\n", "Power supply ok now."); 478 user_warned = 0; 479 } 480 if ((intr & KMIN_INTR_PSWARN) && (user_warned < 3)) { 481 user_warned++; 482 printf("%s\n", "Power supply overheating"); 483 } 484 } 485 if ((cpumask & MIPS_INT_MASK_0) && tc_slot_info[0].intr) { 486 (*tc_slot_info[0].intr)(tc_slot_info[0].sc); 487 intrcnt[SLOT0_INTR]++; 488 } 489 490 if ((cpumask & MIPS_INT_MASK_1) && tc_slot_info[1].intr) { 491 (*tc_slot_info[1].intr)(tc_slot_info[1].sc); 492 intrcnt[SLOT1_INTR]++; 493 } 494 if ((cpumask & MIPS_INT_MASK_2) && tc_slot_info[2].intr) { 495 (*tc_slot_info[2].intr)(tc_slot_info[2].sc); 496 intrcnt[SLOT2_INTR]++; 497 } 498 499done: 500 /* restore entry state */ 501 splhigh(); 502 intr_depth--; 503 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = old_mask; 504 505 506 return (MIPS_SR_INT_IE | (status & ~cause & MIPS_HARD_INT_MASK)); 507} 508 509 510 511/* 512 ************************************************************************ 513 * Extra functions 514 ************************************************************************ 515 */ 516 517 518 519 520/* 521 * Count instructions between 4ms mcclock interrupt requests, 522 * using the ioasic clock-interrupt-pending bit to determine 523 * when clock ticks occur. 524 * Set up iosiac to allow only clock interrupts, then 525 * call 526 */ 527void 528dec_3min_mcclock_cpuspeed(mcclock_addr, clockmask) 529 volatile struct chiptime *mcclock_addr; 530 int clockmask; 531{ 532 u_int32_t saved_imask; 533 534 saved_imask = *(u_int32_t *)(ioasic_base + IOASIC_IMSK); 535 536 /* Allow only clock interrupts through ioasic. */ 537 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = KMIN_INTR_CLOCK; 538 kn02ba_wbflush(); 539 540 mc_cpuspeed(mcclock_addr, clockmask); 541 542 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = saved_imask; 543 kn02ba_wbflush(); 544} 545 546void 547kn02ba_wbflush() 548{ 549 /* read twice IOASIC_INTR register */ 550 __asm __volatile("lw $0,0xbc040120; lw $0,0xbc040120"); 551} 552 553unsigned 554kn02ba_clkread() 555{ 556#ifdef MIPS3 557 if (CPUISMIPS3) { 558 u_int32_t mips3_cycles; 559 560 mips3_cycles = mips3_cycle_count() - latched_cycle_cnt; 561 /* XXX divides take 78 cycles: approximate with * 41/2048 */ 562 return((mips3_cycles >> 6) + (mips3_cycles >> 8) + 563 (mips3_cycles >> 11)); 564 } 565#endif 566 return 0; 567} 568