dec_3min.c revision 1.21
1/* $NetBSD: dec_3min.c,v 1.21 1999/06/10 01:37:10 nisimura Exp $ */ 2 3/* 4 * Copyright (c) 1998 Jonathan Stone. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Jonathan Stone for 17 * the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Copyright (c) 1988 University of Utah. 35 * Copyright (c) 1992, 1993 36 * The Regents of the University of California. All rights reserved. 37 * 38 * This code is derived from software contributed to Berkeley by 39 * the Systems Programming Group of the University of Utah Computer 40 * Science Department, The Mach Operating System project at 41 * Carnegie-Mellon University and Ralph Campbell. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by the University of 54 * California, Berkeley and its contributors. 55 * 4. Neither the name of the University nor the names of its contributors 56 * may be used to endorse or promote products derived from this software 57 * without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 61 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 62 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 63 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 64 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 65 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69 * SUCH DAMAGE. 70 * 71 * @(#)machdep.c 8.3 (Berkeley) 1/12/94 72 */ 73 74#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 75 76__KERNEL_RCSID(0, "$NetBSD: dec_3min.c,v 1.21 1999/06/10 01:37:10 nisimura Exp $"); 77 78 79#include <sys/types.h> 80#include <sys/systm.h> 81 82#include <machine/cpu.h> 83#include <machine/intr.h> 84#include <machine/reg.h> 85#include <machine/psl.h> 86#include <machine/autoconf.h> /* intr_arg_t */ 87#include <machine/sysconf.h> 88 89#include <mips/mips_param.h> /* hokey spl()s */ 90#include <mips/mips/mips_mcclock.h> /* mcclock CPUspeed estimation */ 91 92/* all these to get ioasic_base */ 93#include <sys/device.h> /* struct cfdata for.. */ 94#include <dev/tc/tcvar.h> /* tc type definitions for.. */ 95#include <dev/tc/ioasicreg.h> /* ioasic interrrupt masks */ 96#include <dev/tc/ioasicvar.h> /* ioasic_base */ 97 98#include <pmax/pmax/clockreg.h> 99#include <pmax/pmax/turbochannel.h> 100#include <pmax/pmax/pmaxtype.h> 101#include <pmax/pmax/machdep.h> 102 103#include <pmax/pmax/kmin.h> /* 3min baseboard addresses */ 104#include <pmax/pmax/memc.h> /* 3min/maxine memory errors */ 105 106 107/* 108 * forward declarations 109 */ 110void dec_3min_init __P((void)); 111void dec_3min_os_init __P((void)); 112void dec_3min_bus_reset __P((void)); 113void dec_3maxplus_device_register __P((struct device *, void *)); 114 115void dec_3min_enable_intr 116 __P ((u_int slotno, int (*handler) __P((intr_arg_t sc)), 117 intr_arg_t sc, int onoff)); 118int dec_3min_intr __P((unsigned, unsigned, unsigned, unsigned)); 119void dec_3min_device_register __P((struct device *, void *)); 120void dec_3min_cons_init __P((void)); 121 122 123/* 124 * Local declarations. 125 */ 126void dec_3min_mcclock_cpuspeed __P((volatile struct chiptime *mcclock_addr, 127 int clockmask)); 128u_long kmin_tc3_imask; 129 130void kn02ba_wbflush __P((void)); 131unsigned kn02ba_clkread __P((void)); 132extern unsigned (*clkread) __P((void)); 133 134extern volatile struct chiptime *mcclock_addr; /* XXX */ 135extern char cpu_model[]; 136extern int physmem_boardmax; 137 138#ifdef MIPS3 139static unsigned latched_cycle_cnt; 140extern u_int32_t mips3_cycle_count __P((void)); 141#endif 142 143 144/* 145 * Fill in platform struct. 146 */ 147void 148dec_3min_init() 149{ 150 platform.iobus = "tc3min"; 151 152 platform.os_init = dec_3min_os_init; 153 platform.bus_reset = dec_3min_bus_reset; 154 platform.cons_init = dec_3min_cons_init; 155 platform.device_register = dec_3min_device_register; 156 157 dec_3min_os_init(); 158 159 sprintf(cpu_model, "DECstation 5000/1%d (3MIN)", cpu_mhz); 160} 161 162 163/* 164 * Initalize the memory system and I/O buses. 165 */ 166void 167dec_3min_bus_reset() 168{ 169 170 /* 171 * Reset interrupts, clear any errors from newconf probes 172 */ 173 174 *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0; 175 kn02ba_wbflush(); 176 177 *(u_int32_t *)(ioasic_base + IOASIC_INTR) = 0; 178 kn02ba_wbflush(); 179} 180 181 182void 183dec_3min_os_init() 184{ 185 ioasic_base = MIPS_PHYS_TO_KSEG1(KMIN_SYS_ASIC); 186 mips_hardware_intr = dec_3min_intr; 187 tc_enable_interrupt = dec_3min_enable_intr; /* XXX */ 188 mcclock_addr = (void *)(ioasic_base + IOASIC_SLOT_8_START); 189 190 /* R4000 3MIN can ultilize on-chip counter */ 191 clkread = kn02ba_clkread; 192 193 /* 194 * All the baseboard interrupts come through the I/O ASIC 195 * (at INT_MASK_3), so it has to be turned off for all the spls. 196 * Since we don't know what kinds of devices are in the 197 * turbochannel option slots, just block them all. 198 */ 199 splvec.splbio = MIPS_SPL_0_1_2_3; 200 splvec.splnet = MIPS_SPL_0_1_2_3; 201 splvec.spltty = MIPS_SPL_0_1_2_3; 202 splvec.splimp = MIPS_SPL_0_1_2_3; 203 splvec.splclock = MIPS_SPL_0_1_2_3; 204 splvec.splstatclock = MIPS_SPL_0_1_2_3; 205 206 dec_3min_mcclock_cpuspeed(mcclock_addr, MIPS_INT_MASK_3); 207 208 *(u_int32_t *)(ioasic_base + IOASIC_LANCE_DECODE) = 0x3; 209 *(u_int32_t *)(ioasic_base + IOASIC_SCSI_DECODE) = 0xe; 210#if 0 211 *(u_int32_t *)(ioasic_base + IOASIC_SCC0_DECODE) = (0x10|4); 212 *(u_int32_t *)(ioasic_base + IOASIC_SCC1_DECODE) = (0x10|6); 213 *(u_int32_t *)(ioasic_base + IOASIC_CSR) = 0x00000f00; 214#endif 215 /* 216 * Initialize interrupts. 217 */ 218 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = KMIN_IM0; 219 *(u_int32_t *)(ioasic_base + IOASIC_INTR) = 0; 220 221 /* 222 * The kmin memory hardware seems to wrap memory addresses 223 * with 4Mbyte SIMMs, which causes the physmem computation 224 * to lose. Find out how big the SIMMS are and set 225 * max_ physmem accordingly. 226 */ 227 physmem_boardmax = KMIN_PHYS_MEMORY_END + 1; 228 if ((*(int *)(MIPS_PHYS_TO_KSEG1(KMIN_REG_MSR)) & 229 KMIN_MSR_SIZE_16Mb) == 0) 230 physmem_boardmax = physmem_boardmax >> 2; 231 physmem_boardmax = MIPS_PHYS_TO_KSEG1(physmem_boardmax); 232 233 /* clear any memory errors from probes */ 234 *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0; 235 kn02ba_wbflush(); 236 237 kmin_tc3_imask = 238 (KMIN_INTR_CLOCK | KMIN_INTR_PSWARN | KMIN_INTR_TIMEOUT); 239 240 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = 241 kmin_tc3_imask | 242 (KMIN_IM0 & ~(KN03_INTR_TC_0|KN03_INTR_TC_1|KN03_INTR_TC_2)); 243} 244 245 246void 247dec_3min_cons_init() 248{ 249 /* notyet */ 250} 251 252 253void 254dec_3min_device_register(dev, aux) 255 struct device *dev; 256 void *aux; 257{ 258 panic("dec_3min_device_register unimplemented"); 259} 260 261 262void 263dec_3min_enable_intr(slotno, handler, sc, on) 264 unsigned int slotno; 265 int (*handler) __P((void* softc)); 266 void *sc; 267 int on; 268{ 269 unsigned mask; 270 271 switch (slotno) { 272 /* slots 0-2 don't interrupt through the IOASIC. */ 273 case 0: 274 mask = MIPS_INT_MASK_0; break; 275 case 1: 276 mask = MIPS_INT_MASK_1; break; 277 case 2: 278 mask = MIPS_INT_MASK_2; break; 279 280 case KMIN_SCSI_SLOT: 281 mask = (IOASIC_INTR_SCSI | IOASIC_INTR_SCSI_PTR_LOAD | 282 IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E); 283 break; 284 285 case KMIN_LANCE_SLOT: 286 mask = KMIN_INTR_LANCE; 287 break; 288 case KMIN_SCC0_SLOT: 289 mask = KMIN_INTR_SCC_0; 290 break; 291 case KMIN_SCC1_SLOT: 292 mask = KMIN_INTR_SCC_1; 293 break; 294 case KMIN_ASIC_SLOT: 295 mask = KMIN_INTR_ASIC; 296 break; 297 default: 298 return; 299 } 300 301#if defined(DEBUG) || defined(DIAGNOSTIC) 302 printf("3MIN: imask %lx, %sabling slot %d, sc %p handler %p\n", 303 kmin_tc3_imask, (on? "en" : "dis"), slotno, sc, handler); 304#endif 305 306 /* 307 * Enable the interrupt handler, and if it's an IOASIC 308 * slot, set the IOASIC interrupt mask. 309 * Otherwise, set the appropriate spl level in the R3000 310 * register. 311 * Be careful to set handlers before enabling, and disable 312 * interrupts before clearing handlers. 313 */ 314 315 if (on) { 316 /* Set the interrupt handler and argument ... */ 317 tc_slot_info[slotno].intr = handler; 318 tc_slot_info[slotno].sc = sc; 319 320 /* ... and set the relevant mask */ 321 if (slotno <= 2) { 322 /* it's an option slot */ 323 int s = splhigh(); 324 s |= mask; 325 splx(s); 326 } else { 327 /* it's a baseboard device going via the ASIC */ 328 kmin_tc3_imask |= mask; 329 } 330 } else { 331 /* Clear the relevant mask... */ 332 if (slotno <= 2) { 333 /* it's an option slot */ 334 int s = splhigh(); 335 printf("kmin_intr: cannot disable option slot %d\n", 336 slotno); 337 s &= ~mask; 338 splx(s); 339 } else { 340 /* it's a baseboard device going via the ASIC */ 341 kmin_tc3_imask &= ~mask; 342 } 343 /* ... and clear the handler */ 344 tc_slot_info[slotno].intr = 0; 345 tc_slot_info[slotno].sc = 0; 346 } 347} 348 349 350 351/* 352 * 3min hardware interrupts. (DECstation 5000/1xx) 353 */ 354int 355dec_3min_intr(cpumask, pc, status, cause) 356 unsigned cpumask; 357 unsigned pc; 358 unsigned status; 359 unsigned cause; 360{ 361 static int user_warned = 0; 362 static int intr_depth = 0; 363 u_int32_t old_mask; 364 365 intr_depth++; 366 old_mask = *(u_int32_t *)(ioasic_base + IOASIC_IMSK); 367 368 if (cpumask & MIPS_INT_MASK_4) 369 prom_haltbutton(); 370 371 if (cpumask & MIPS_INT_MASK_3) { 372 /* NB: status & MIPS_INT_MASK3 must also be set */ 373 /* masked interrupts are still observable */ 374 u_int32_t intr, imsk, turnoff; 375 376 turnoff = 0; 377 intr = *(u_int32_t *)(ioasic_base + IOASIC_INTR); 378 imsk = *(u_int32_t *)(ioasic_base + IOASIC_IMSK); 379 intr &= imsk; 380 381 if (intr & IOASIC_INTR_SCSI_PTR_LOAD) { 382 turnoff |= IOASIC_INTR_SCSI_PTR_LOAD; 383#ifdef notdef 384 asc_dma_intr(); 385#endif 386 } 387 388 if (intr & (IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E)) 389 turnoff |= IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E; 390 391 if (intr & IOASIC_INTR_LANCE_READ_E) 392 turnoff |= IOASIC_INTR_LANCE_READ_E; 393 394 if (turnoff) 395 *(u_int32_t *)(ioasic_base + IOASIC_INTR) = ~turnoff; 396 397 if (intr & KMIN_INTR_TIMEOUT) 398 kn02ba_errintr(); 399 400 if (intr & KMIN_INTR_CLOCK) { 401 struct clockframe cf; 402 struct chiptime *clk; 403 volatile int temp; 404 405 clk = (void *)(ioasic_base + IOASIC_SLOT_8_START); 406 temp = clk->regc; /* XXX clear interrupt bits */ 407 408#ifdef MIPS3 409 if (CPUISMIPS3) { 410 latched_cycle_cnt = mips3_cycle_count(); 411 } 412#endif 413 cf.pc = pc; 414 cf.sr = status; 415 hardclock(&cf); 416 intrcnt[HARDCLOCK]++; 417 } 418 419 /* If clock interrups were enabled, re-enable them ASAP. */ 420 if (old_mask & KMIN_INTR_CLOCK) { 421 /* ioctl interrupt mask to splclock and higher */ 422 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) 423 = old_mask & 424 ~(KMIN_INTR_SCC_0|KMIN_INTR_SCC_1 | 425 IOASIC_INTR_LANCE|IOASIC_INTR_SCSI); 426 kn02ba_wbflush(); 427 _splset(MIPS_SR_INT_IE | (status & MIPS_INT_MASK_3)); 428 } 429 430 if (intr_depth > 1) 431 goto done; 432 433 if ((intr & KMIN_INTR_SCC_0) && 434 tc_slot_info[KMIN_SCC0_SLOT].intr) { 435 (*(tc_slot_info[KMIN_SCC0_SLOT].intr)) 436 (tc_slot_info[KMIN_SCC0_SLOT].sc); 437 intrcnt[SERIAL0_INTR]++; 438 } 439 440 if ((intr & KMIN_INTR_SCC_1) && 441 tc_slot_info[KMIN_SCC1_SLOT].intr) { 442 (*(tc_slot_info[KMIN_SCC1_SLOT].intr)) 443 (tc_slot_info[KMIN_SCC1_SLOT].sc); 444 intrcnt[SERIAL1_INTR]++; 445 } 446 447#ifdef notyet /* untested */ 448 /* If tty interrupts were enabled, re-enable them ASAP. */ 449 if ((old_mask & (KMIN_INTR_SCC_1|KMIN_INTR_SCC_0)) == 450 (KMIN_INTR_SCC_1|KMIN_INTR_SCC_0)) { 451 *imaskp = old_mask & 452 ~(KMIN_INTR_SCC_0|KMIN_INTR_SCC_1 | 453 IOASIC_INTR_LANCE|IOASIC_INTR_SCSI); 454 kn02ba_wbflush(); 455 } 456 457 /* XXX until we know about SPLs of TC options. */ 458 if (intr_depth > 1) 459 goto done; 460#endif 461 if ((intr & IOASIC_INTR_LANCE) && 462 tc_slot_info[KMIN_LANCE_SLOT].intr) { 463 (*(tc_slot_info[KMIN_LANCE_SLOT].intr)) 464 (tc_slot_info[KMIN_LANCE_SLOT].sc); 465 intrcnt[LANCE_INTR]++; 466 } 467 468 if ((intr & IOASIC_INTR_SCSI) && 469 tc_slot_info[KMIN_SCSI_SLOT].intr) { 470 (*(tc_slot_info[KMIN_SCSI_SLOT].intr)) 471 (tc_slot_info[KMIN_SCSI_SLOT].sc); 472 intrcnt[SCSI_INTR]++; 473 } 474 475 if (user_warned && ((intr & KMIN_INTR_PSWARN) == 0)) { 476 printf("%s\n", "Power supply ok now."); 477 user_warned = 0; 478 } 479 if ((intr & KMIN_INTR_PSWARN) && (user_warned < 3)) { 480 user_warned++; 481 printf("%s\n", "Power supply overheating"); 482 } 483 } 484 if ((cpumask & MIPS_INT_MASK_0) && tc_slot_info[0].intr) { 485 (*tc_slot_info[0].intr)(tc_slot_info[0].sc); 486 intrcnt[SLOT0_INTR]++; 487 } 488 489 if ((cpumask & MIPS_INT_MASK_1) && tc_slot_info[1].intr) { 490 (*tc_slot_info[1].intr)(tc_slot_info[1].sc); 491 intrcnt[SLOT1_INTR]++; 492 } 493 if ((cpumask & MIPS_INT_MASK_2) && tc_slot_info[2].intr) { 494 (*tc_slot_info[2].intr)(tc_slot_info[2].sc); 495 intrcnt[SLOT2_INTR]++; 496 } 497 498done: 499 /* restore entry state */ 500 splhigh(); 501 intr_depth--; 502 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = old_mask; 503 504 505 return (MIPS_SR_INT_IE | (status & ~cause & MIPS_HARD_INT_MASK)); 506} 507 508 509 510/* 511 ************************************************************************ 512 * Extra functions 513 ************************************************************************ 514 */ 515 516 517 518 519/* 520 * Count instructions between 4ms mcclock interrupt requests, 521 * using the ioasic clock-interrupt-pending bit to determine 522 * when clock ticks occur. 523 * Set up iosiac to allow only clock interrupts, then 524 * call 525 */ 526void 527dec_3min_mcclock_cpuspeed(mcclock_addr, clockmask) 528 volatile struct chiptime *mcclock_addr; 529 int clockmask; 530{ 531 u_int32_t saved_imask; 532 533 saved_imask = *(u_int32_t *)(ioasic_base + IOASIC_IMSK); 534 535 /* Allow only clock interrupts through ioasic. */ 536 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = KMIN_INTR_CLOCK; 537 kn02ba_wbflush(); 538 539 mc_cpuspeed(mcclock_addr, clockmask); 540 541 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = saved_imask; 542 kn02ba_wbflush(); 543} 544 545void 546kn02ba_wbflush() 547{ 548 /* read twice IOASIC_IMSK */ 549 __asm __volatile("lw $0,%0; lw $0,%0" :: "i"(0xbc040120)); 550} 551 552unsigned 553kn02ba_clkread() 554{ 555#ifdef MIPS3 556 if (CPUISMIPS3) { 557 u_int32_t mips3_cycles; 558 559 mips3_cycles = mips3_cycle_count() - latched_cycle_cnt; 560 /* XXX divides take 78 cycles: approximate with * 41/2048 */ 561 return((mips3_cycles >> 6) + (mips3_cycles >> 8) + 562 (mips3_cycles >> 11)); 563 } 564#endif 565 return 0; 566} 567