dec_3min.c revision 1.22
1/* $NetBSD: dec_3min.c,v 1.22 1999/11/12 09:55:38 nisimura Exp $ */ 2 3/* 4 * Copyright (c) 1998 Jonathan Stone. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Jonathan Stone for 17 * the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Copyright (c) 1988 University of Utah. 35 * Copyright (c) 1992, 1993 36 * The Regents of the University of California. All rights reserved. 37 * 38 * This code is derived from software contributed to Berkeley by 39 * the Systems Programming Group of the University of Utah Computer 40 * Science Department, The Mach Operating System project at 41 * Carnegie-Mellon University and Ralph Campbell. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by the University of 54 * California, Berkeley and its contributors. 55 * 4. Neither the name of the University nor the names of its contributors 56 * may be used to endorse or promote products derived from this software 57 * without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 61 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 62 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 63 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 64 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 65 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69 * SUCH DAMAGE. 70 * 71 * @(#)machdep.c 8.3 (Berkeley) 1/12/94 72 */ 73 74#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 75 76__KERNEL_RCSID(0, "$NetBSD: dec_3min.c,v 1.22 1999/11/12 09:55:38 nisimura Exp $"); 77 78 79#include <sys/types.h> 80#include <sys/systm.h> 81 82#include <machine/cpu.h> 83#include <machine/intr.h> 84#include <machine/reg.h> 85#include <machine/psl.h> 86#include <machine/autoconf.h> /* intr_arg_t */ 87#include <machine/sysconf.h> 88 89#include <mips/mips/mips_mcclock.h> /* mcclock CPUspeed estimation */ 90 91/* all these to get ioasic_base */ 92#include <sys/device.h> /* struct cfdata for.. */ 93#include <dev/tc/tcvar.h> /* tc type definitions for.. */ 94#include <dev/tc/ioasicreg.h> /* ioasic interrrupt masks */ 95#include <dev/tc/ioasicvar.h> /* ioasic_base */ 96 97#include <pmax/pmax/turbochannel.h> 98#include <pmax/pmax/machdep.h> 99 100#include <pmax/pmax/kmin.h> /* 3min baseboard addresses */ 101#include <pmax/pmax/memc.h> /* 3min/maxine memory errors */ 102 103 104/* 105 * forward declarations 106 */ 107void dec_3min_init __P((void)); 108void dec_3min_bus_reset __P((void)); 109 110void dec_3min_enable_intr 111 __P ((u_int slotno, int (*handler) __P((intr_arg_t sc)), 112 intr_arg_t sc, int onoff)); 113int dec_3min_intr __P((unsigned, unsigned, unsigned, unsigned)); 114void dec_3min_device_register __P((struct device *, void *)); 115void dec_3min_cons_init __P((void)); 116 117 118/* 119 * Local declarations. 120 */ 121void dec_3min_mcclock_cpuspeed __P((volatile struct chiptime *mcclock_addr, 122 int clockmask)); 123void kn02ba_wbflush __P((void)); 124unsigned kn02ba_clkread __P((void)); 125 126static u_int32_t kmin_tc3_imask; 127 128#ifdef MIPS3 129static unsigned latched_cycle_cnt; 130extern u_int32_t mips3_cycle_count __P((void)); 131#endif 132 133 134void 135dec_3min_init() 136{ 137 extern char cpu_model[]; 138 extern int physmem_boardmax; 139 140 platform.iobus = "tc3min"; 141 platform.bus_reset = dec_3min_bus_reset; 142 platform.cons_init = dec_3min_cons_init; 143 platform.device_register = dec_3min_device_register; 144 platform.iointr = dec_3min_intr; 145 platform.clkread = kn02ba_clkread; 146 147 /* clear any memory errors */ 148 *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0; 149 kn02ba_wbflush(); 150 151 ioasic_base = MIPS_PHYS_TO_KSEG1(KMIN_SYS_ASIC); 152 mips_hardware_intr = dec_3min_intr; 153 tc_enable_interrupt = dec_3min_enable_intr; 154 155 /* 156 * Since all the motherboard interrupts come through the 157 * IOASIC, it has to be turned off for all the spls and 158 * since we don't know what kinds of devices are in the 159 * TURBOchannel option slots, just splhigh(). 160 */ 161 splvec.splbio = MIPS_SPL_0_1_2_3; 162 splvec.splnet = MIPS_SPL_0_1_2_3; 163 splvec.spltty = MIPS_SPL_0_1_2_3; 164 splvec.splimp = MIPS_SPL_0_1_2_3; 165 splvec.splclock = MIPS_SPL_0_1_2_3; 166 splvec.splstatclock = MIPS_SPL_0_1_2_3; 167 168 /* calibrate cpu_mhz value */ 169 dec_3min_mcclock_cpuspeed( 170 (void *)(ioasic_base + IOASIC_SLOT_8_START), MIPS_INT_MASK_3); 171 172 *(u_int32_t *)(ioasic_base + IOASIC_LANCE_DECODE) = 0x3; 173 *(u_int32_t *)(ioasic_base + IOASIC_SCSI_DECODE) = 0xe; 174#if 0 175 *(u_int32_t *)(ioasic_base + IOASIC_SCC0_DECODE) = (0x10|4); 176 *(u_int32_t *)(ioasic_base + IOASIC_SCC1_DECODE) = (0x10|6); 177 *(u_int32_t *)(ioasic_base + IOASIC_CSR) = 0x00000f00; 178#endif 179 180 /* sanitize interrupt mask */ 181 kmin_tc3_imask = (KMIN_INTR_CLOCK|KMIN_INTR_PSWARN|KMIN_INTR_TIMEOUT); 182 *(u_int32_t *)(ioasic_base + IOASIC_INTR) = 0; 183 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = kmin_tc3_imask; 184 185 /* 186 * The kmin memory hardware seems to wrap memory addresses 187 * with 4Mbyte SIMMs, which causes the physmem computation 188 * to lose. Find out how big the SIMMS are and set 189 * max_ physmem accordingly. 190 * XXX Do MAXINEs lose the same way? 191 */ 192 physmem_boardmax = KMIN_PHYS_MEMORY_END + 1; 193 if ((KMIN_MSR_SIZE_16Mb & *(int *)MIPS_PHYS_TO_KSEG1(KMIN_REG_MSR)) 194 == 0) 195 physmem_boardmax = physmem_boardmax >> 2; 196 physmem_boardmax = MIPS_PHYS_TO_KSEG1(physmem_boardmax); 197 198 sprintf(cpu_model, "DECstation 5000/1%d (3MIN)", cpu_mhz); 199} 200 201/* 202 * Initalize the memory system and I/O buses. 203 */ 204void 205dec_3min_bus_reset() 206{ 207 208 /* 209 * Reset interrupts, clear any errors from newconf probes 210 */ 211 212 *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0; 213 kn02ba_wbflush(); 214 215 *(u_int32_t *)(ioasic_base + IOASIC_INTR) = 0; 216 kn02ba_wbflush(); 217} 218 219void 220dec_3min_cons_init() 221{ 222 /* notyet */ 223} 224 225 226void 227dec_3min_device_register(dev, aux) 228 struct device *dev; 229 void *aux; 230{ 231 panic("dec_3min_device_register unimplemented"); 232} 233 234 235void 236dec_3min_enable_intr(slotno, handler, sc, on) 237 unsigned int slotno; 238 int (*handler) __P((void* softc)); 239 void *sc; 240 int on; 241{ 242 unsigned mask; 243 244 switch (slotno) { 245 /* slots 0-2 don't interrupt through the IOASIC. */ 246 case 0: 247 mask = MIPS_INT_MASK_0; break; 248 case 1: 249 mask = MIPS_INT_MASK_1; break; 250 case 2: 251 mask = MIPS_INT_MASK_2; break; 252 253 case KMIN_SCSI_SLOT: 254 mask = (IOASIC_INTR_SCSI | IOASIC_INTR_SCSI_PTR_LOAD | 255 IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E); 256 break; 257 258 case KMIN_LANCE_SLOT: 259 mask = KMIN_INTR_LANCE; 260 break; 261 case KMIN_SCC0_SLOT: 262 mask = KMIN_INTR_SCC_0; 263 break; 264 case KMIN_SCC1_SLOT: 265 mask = KMIN_INTR_SCC_1; 266 break; 267 case KMIN_ASIC_SLOT: 268 mask = KMIN_INTR_ASIC; 269 break; 270 default: 271 return; 272 } 273 274#if defined(DEBUG) || defined(DIAGNOSTIC) 275 printf("3MIN: imask %lx, %sabling slot %d, sc %p handler %p\n", 276 kmin_tc3_imask, (on? "en" : "dis"), slotno, sc, handler); 277#endif 278 279 /* 280 * Enable the interrupt handler, and if it's an IOASIC 281 * slot, set the IOASIC interrupt mask. 282 * Otherwise, set the appropriate spl level in the R3000 283 * register. 284 * Be careful to set handlers before enabling, and disable 285 * interrupts before clearing handlers. 286 */ 287 288 if (on) { 289 /* Set the interrupt handler and argument ... */ 290 tc_slot_info[slotno].intr = handler; 291 tc_slot_info[slotno].sc = sc; 292 293 /* ... and set the relevant mask */ 294 if (slotno <= 2) { 295 /* it's an option slot */ 296 int s = splhigh(); 297 s |= mask; 298 splx(s); 299 } else { 300 /* it's a baseboard device going via the ASIC */ 301 kmin_tc3_imask |= mask; 302 } 303 } else { 304 /* Clear the relevant mask... */ 305 if (slotno <= 2) { 306 /* it's an option slot */ 307 int s = splhigh(); 308 printf("kmin_intr: cannot disable option slot %d\n", 309 slotno); 310 s &= ~mask; 311 splx(s); 312 } else { 313 /* it's a baseboard device going via the ASIC */ 314 kmin_tc3_imask &= ~mask; 315 } 316 /* ... and clear the handler */ 317 tc_slot_info[slotno].intr = 0; 318 tc_slot_info[slotno].sc = 0; 319 } 320} 321 322 323 324/* 325 * 3min hardware interrupts. (DECstation 5000/1xx) 326 */ 327int 328dec_3min_intr(cpumask, pc, status, cause) 329 unsigned cpumask; 330 unsigned pc; 331 unsigned status; 332 unsigned cause; 333{ 334 static int user_warned = 0; 335 static int intr_depth = 0; 336 u_int32_t old_mask; 337 338 intr_depth++; 339 old_mask = *(u_int32_t *)(ioasic_base + IOASIC_IMSK); 340 341 if (cpumask & MIPS_INT_MASK_4) 342 prom_haltbutton(); 343 344 if (cpumask & MIPS_INT_MASK_3) { 345 /* NB: status & MIPS_INT_MASK3 must also be set */ 346 /* masked interrupts are still observable */ 347 u_int32_t intr, imsk, turnoff; 348 349 turnoff = 0; 350 intr = *(u_int32_t *)(ioasic_base + IOASIC_INTR); 351 imsk = *(u_int32_t *)(ioasic_base + IOASIC_IMSK); 352 intr &= imsk; 353 354 if (intr & IOASIC_INTR_SCSI_PTR_LOAD) { 355 turnoff |= IOASIC_INTR_SCSI_PTR_LOAD; 356#ifdef notdef 357 asc_dma_intr(); 358#endif 359 } 360 361 if (intr & (IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E)) 362 turnoff |= IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E; 363 364 if (intr & IOASIC_INTR_LANCE_READ_E) 365 turnoff |= IOASIC_INTR_LANCE_READ_E; 366 367 if (turnoff) 368 *(u_int32_t *)(ioasic_base + IOASIC_INTR) = ~turnoff; 369 370 if (intr & KMIN_INTR_TIMEOUT) 371 kn02ba_errintr(); 372 373 if (intr & KMIN_INTR_CLOCK) { 374 struct clockframe cf; 375 376 __asm __volatile("lbu $0,48(%0)" :: 377 "r"(ioasic_base + IOASIC_SLOT_8_START)); 378#ifdef MIPS3 379 if (CPUISMIPS3) { 380 latched_cycle_cnt = mips3_cycle_count(); 381 } 382#endif 383 cf.pc = pc; 384 cf.sr = status; 385 hardclock(&cf); 386 intrcnt[HARDCLOCK]++; 387 } 388 389 /* If clock interrups were enabled, re-enable them ASAP. */ 390 if (old_mask & KMIN_INTR_CLOCK) { 391 /* ioctl interrupt mask to splclock and higher */ 392 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) 393 = old_mask & 394 ~(KMIN_INTR_SCC_0|KMIN_INTR_SCC_1 | 395 IOASIC_INTR_LANCE|IOASIC_INTR_SCSI); 396 kn02ba_wbflush(); 397 _splset(MIPS_SR_INT_IE | (status & MIPS_INT_MASK_3)); 398 } 399 400 if (intr_depth > 1) 401 goto done; 402 403 if ((intr & KMIN_INTR_SCC_0) && 404 tc_slot_info[KMIN_SCC0_SLOT].intr) { 405 (*(tc_slot_info[KMIN_SCC0_SLOT].intr)) 406 (tc_slot_info[KMIN_SCC0_SLOT].sc); 407 intrcnt[SERIAL0_INTR]++; 408 } 409 410 if ((intr & KMIN_INTR_SCC_1) && 411 tc_slot_info[KMIN_SCC1_SLOT].intr) { 412 (*(tc_slot_info[KMIN_SCC1_SLOT].intr)) 413 (tc_slot_info[KMIN_SCC1_SLOT].sc); 414 intrcnt[SERIAL1_INTR]++; 415 } 416 417#ifdef notyet /* untested */ 418 /* If tty interrupts were enabled, re-enable them ASAP. */ 419 if ((old_mask & (KMIN_INTR_SCC_1|KMIN_INTR_SCC_0)) == 420 (KMIN_INTR_SCC_1|KMIN_INTR_SCC_0)) { 421 *imaskp = old_mask & 422 ~(KMIN_INTR_SCC_0|KMIN_INTR_SCC_1 | 423 IOASIC_INTR_LANCE|IOASIC_INTR_SCSI); 424 kn02ba_wbflush(); 425 } 426 427 /* XXX until we know about SPLs of TC options. */ 428 if (intr_depth > 1) 429 goto done; 430#endif 431 if ((intr & IOASIC_INTR_LANCE) && 432 tc_slot_info[KMIN_LANCE_SLOT].intr) { 433 (*(tc_slot_info[KMIN_LANCE_SLOT].intr)) 434 (tc_slot_info[KMIN_LANCE_SLOT].sc); 435 intrcnt[LANCE_INTR]++; 436 } 437 438 if ((intr & IOASIC_INTR_SCSI) && 439 tc_slot_info[KMIN_SCSI_SLOT].intr) { 440 (*(tc_slot_info[KMIN_SCSI_SLOT].intr)) 441 (tc_slot_info[KMIN_SCSI_SLOT].sc); 442 intrcnt[SCSI_INTR]++; 443 } 444 445 if (user_warned && ((intr & KMIN_INTR_PSWARN) == 0)) { 446 printf("%s\n", "Power supply ok now."); 447 user_warned = 0; 448 } 449 if ((intr & KMIN_INTR_PSWARN) && (user_warned < 3)) { 450 user_warned++; 451 printf("%s\n", "Power supply overheating"); 452 } 453 } 454 if ((cpumask & MIPS_INT_MASK_0) && tc_slot_info[0].intr) { 455 (*tc_slot_info[0].intr)(tc_slot_info[0].sc); 456 intrcnt[SLOT0_INTR]++; 457 } 458 459 if ((cpumask & MIPS_INT_MASK_1) && tc_slot_info[1].intr) { 460 (*tc_slot_info[1].intr)(tc_slot_info[1].sc); 461 intrcnt[SLOT1_INTR]++; 462 } 463 if ((cpumask & MIPS_INT_MASK_2) && tc_slot_info[2].intr) { 464 (*tc_slot_info[2].intr)(tc_slot_info[2].sc); 465 intrcnt[SLOT2_INTR]++; 466 } 467 468done: 469 /* restore entry state */ 470 splhigh(); 471 intr_depth--; 472 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = old_mask; 473 474 475 return (MIPS_SR_INT_IE | (status & ~cause & MIPS_HARD_INT_MASK)); 476} 477 478 479 480/* 481 ************************************************************************ 482 * Extra functions 483 ************************************************************************ 484 */ 485 486 487 488 489/* 490 * Count instructions between 4ms mcclock interrupt requests, 491 * using the ioasic clock-interrupt-pending bit to determine 492 * when clock ticks occur. 493 * Set up iosiac to allow only clock interrupts, then 494 * call 495 */ 496void 497dec_3min_mcclock_cpuspeed(mcclock_addr, clockmask) 498 volatile struct chiptime *mcclock_addr; 499 int clockmask; 500{ 501 u_int32_t saved_imask; 502 503 saved_imask = *(u_int32_t *)(ioasic_base + IOASIC_IMSK); 504 505 /* Allow only clock interrupts through ioasic. */ 506 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = KMIN_INTR_CLOCK; 507 kn02ba_wbflush(); 508 509 mc_cpuspeed(mcclock_addr, clockmask); 510 511 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = saved_imask; 512 kn02ba_wbflush(); 513} 514 515void 516kn02ba_wbflush() 517{ 518 /* read twice IOASIC_IMSK */ 519 __asm __volatile("lw $0,%0; lw $0,%0" :: "i"(0xbc040120)); 520} 521 522unsigned 523kn02ba_clkread() 524{ 525#ifdef MIPS3 526 if (CPUISMIPS3) { 527 u_int32_t mips3_cycles; 528 529 mips3_cycles = mips3_cycle_count() - latched_cycle_cnt; 530 /* XXX divides take 78 cycles: approximate with * 41/2048 */ 531 return((mips3_cycles >> 6) + (mips3_cycles >> 8) + 532 (mips3_cycles >> 11)); 533 } 534#endif 535 return 0; 536} 537