dec_3min.c revision 1.34
1/* $NetBSD: dec_3min.c,v 1.34 2000/02/03 04:09:02 nisimura Exp $ */ 2 3/* 4 * Copyright (c) 1998 Jonathan Stone. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Jonathan Stone for 17 * the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Copyright (c) 1988 University of Utah. 35 * Copyright (c) 1992, 1993 36 * The Regents of the University of California. All rights reserved. 37 * 38 * This code is derived from software contributed to Berkeley by 39 * the Systems Programming Group of the University of Utah Computer 40 * Science Department, The Mach Operating System project at 41 * Carnegie-Mellon University and Ralph Campbell. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by the University of 54 * California, Berkeley and its contributors. 55 * 4. Neither the name of the University nor the names of its contributors 56 * may be used to endorse or promote products derived from this software 57 * without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 61 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 62 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 63 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 64 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 65 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69 * SUCH DAMAGE. 70 * 71 * @(#)machdep.c 8.3 (Berkeley) 1/12/94 72 */ 73 74#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 75 76__KERNEL_RCSID(0, "$NetBSD: dec_3min.c,v 1.34 2000/02/03 04:09:02 nisimura Exp $"); 77 78 79#include <sys/param.h> 80#include <sys/systm.h> 81#include <sys/device.h> 82 83#include <machine/cpu.h> 84#include <machine/intr.h> 85#include <machine/sysconf.h> 86 87#include <mips/mips/mips_mcclock.h> /* mcclock CPUspeed estimation */ 88 89/* all these to get ioasic_base */ 90#include <dev/tc/tcvar.h> /* tc type definitions for.. */ 91#include <dev/tc/ioasicreg.h> /* ioasic interrrupt masks */ 92#include <dev/tc/ioasicvar.h> /* ioasic_base */ 93 94#include <pmax/pmax/machdep.h> 95#include <pmax/pmax/kmin.h> /* 3min baseboard addresses */ 96#include <pmax/pmax/memc.h> /* 3min/maxine memory errors */ 97#include <pmax/tc/sccvar.h> 98 99#include "rasterconsole.h" 100 101 102/* 103 * forward declarations 104 */ 105void dec_3min_init __P((void)); /* XXX */ 106static void dec_3min_bus_reset __P((void)); 107static void dec_3min_cons_init __P((void)); 108static void dec_3min_device_register __P((struct device *, void *)); 109static int dec_3min_intr __P((unsigned, unsigned, unsigned, unsigned)); 110static void dec_3min_intr_establish __P((struct device *, void *, 111 int, int (*)(void *), void *)); 112static void dec_3min_intr_disestablish __P((struct device *, void *)); 113 114static void kn02ba_wbflush __P((void)); 115static unsigned kn02ba_clkread __P((void)); 116 117 118/* 119 * Local declarations. 120 */ 121static u_int32_t kmin_tc3_imask; 122 123#ifdef MIPS3 124static unsigned latched_cycle_cnt; 125#endif 126 127 128void 129dec_3min_init() 130{ 131 int physmem_boardmax; 132 133 platform.iobus = "tcbus"; 134 platform.bus_reset = dec_3min_bus_reset; 135 platform.cons_init = dec_3min_cons_init; 136 platform.device_register = dec_3min_device_register; 137 platform.iointr = dec_3min_intr; 138 platform.intr_establish = dec_3min_intr_establish; 139 platform.intr_disestablish = dec_3min_intr_disestablish; 140 platform.memsize = memsize_scan; 141 platform.clkread = kn02ba_clkread; 142 143 /* clear any memory errors */ 144 *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0; 145 kn02ba_wbflush(); 146 147 ioasic_base = MIPS_PHYS_TO_KSEG1(KMIN_SYS_ASIC); 148 mips_hardware_intr = dec_3min_intr; 149 150 /* 151 * Since all the motherboard interrupts come through the 152 * IOASIC, it has to be turned off for all the spls and 153 * since we don't know what kinds of devices are in the 154 * TURBOchannel option slots, just splhigh(). 155 */ 156 splvec.splbio = MIPS_SPL_0_1_2_3; 157 splvec.splnet = MIPS_SPL_0_1_2_3; 158 splvec.spltty = MIPS_SPL_0_1_2_3; 159 splvec.splimp = MIPS_SPL_0_1_2_3; 160 splvec.splclock = MIPS_SPL_0_1_2_3; 161 splvec.splstatclock = MIPS_SPL_0_1_2_3; 162 163 /* enable posting of MIPS_INT_MASK_3 to CAUSE register */ 164 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = KMIN_INTR_CLOCK; 165 /* calibrate cpu_mhz value */ 166 mc_cpuspeed(ioasic_base+IOASIC_SLOT_8_START, MIPS_INT_MASK_3); 167 168 *(u_int32_t *)(ioasic_base + IOASIC_LANCE_DECODE) = 0x3; 169 *(u_int32_t *)(ioasic_base + IOASIC_SCSI_DECODE) = 0xe; 170#if 0 171 *(u_int32_t *)(ioasic_base + IOASIC_SCC0_DECODE) = (0x10|4); 172 *(u_int32_t *)(ioasic_base + IOASIC_SCC1_DECODE) = (0x10|6); 173 *(u_int32_t *)(ioasic_base + IOASIC_CSR) = 0x00000f00; 174#endif 175 176 /* sanitize interrupt mask */ 177 kmin_tc3_imask = (KMIN_INTR_CLOCK|KMIN_INTR_PSWARN|KMIN_INTR_TIMEOUT); 178 *(u_int32_t *)(ioasic_base + IOASIC_INTR) = 0; 179 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = kmin_tc3_imask; 180 181 /* 182 * The kmin memory hardware seems to wrap memory addresses 183 * with 4Mbyte SIMMs, which causes the physmem computation 184 * to lose. Find out how big the SIMMS are and set 185 * max_ physmem accordingly. 186 * XXX Do MAXINEs lose the same way? 187 */ 188 physmem_boardmax = KMIN_PHYS_MEMORY_END + 1; 189 if ((KMIN_MSR_SIZE_16Mb & *(int *)MIPS_PHYS_TO_KSEG1(KMIN_REG_MSR)) 190 == 0) 191 physmem_boardmax = physmem_boardmax >> 2; 192 physmem_boardmax = MIPS_PHYS_TO_KSEG1(physmem_boardmax); 193 194 sprintf(cpu_model, "DECstation 5000/1%d (3MIN)", cpu_mhz); 195} 196 197/* 198 * Initalize the memory system and I/O buses. 199 */ 200static void 201dec_3min_bus_reset() 202{ 203 204 /* 205 * Reset interrupts, clear any errors from newconf probes 206 */ 207 208 *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0; 209 kn02ba_wbflush(); 210 211 *(u_int32_t *)(ioasic_base + IOASIC_INTR) = 0; 212 kn02ba_wbflush(); 213} 214 215static void 216dec_3min_cons_init() 217{ 218 int kbd, crt, screen; 219 extern int tcfb_cnattach __P((int)); /* XXX */ 220 221 kbd = crt = screen = 0; 222 prom_findcons(&kbd, &crt, &screen); 223 224 if (screen > 0) { 225#if NRASTERCONSOLE > 0 226 if (tcfb_cnattach(crt) > 0) { 227 scc_lk201_cnattach(ioasic_base, 0x180000); 228 return; 229 } 230#endif 231 printf("No framebuffer device configured for slot %d: ", crt); 232 printf("using serial console\n"); 233 } 234 /* 235 * Delay to allow PROM putchars to complete. 236 * FIFO depth * character time, 237 * character time = (1000000 / (defaultrate / 10)) 238 */ 239 DELAY(160000000 / 9600); /* XXX */ 240 241 scc_cnattach(ioasic_base, 0x180000); 242} 243 244 245static void 246dec_3min_device_register(dev, aux) 247 struct device *dev; 248 void *aux; 249{ 250 panic("dec_3min_device_register unimplemented"); 251} 252 253 254static void 255dec_3min_intr_establish(dev, cookie, level, handler, arg) 256 struct device *dev; 257 void *cookie; 258 int level; 259 int (*handler) __P((void *)); 260 void *arg; 261{ 262 int slotno = (int)cookie; 263 unsigned mask; 264 265 switch (slotno) { 266 /* slots 0-2 don't interrupt through the IOASIC. */ 267 case 0: 268 mask = MIPS_INT_MASK_0; 269 break; 270 case 1: 271 mask = MIPS_INT_MASK_1; 272 break; 273 case 2: 274 mask = MIPS_INT_MASK_2; 275 break; 276 277 case KMIN_SCSI_SLOT: 278 mask = (IOASIC_INTR_SCSI | IOASIC_INTR_SCSI_PTR_LOAD | 279 IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E); 280 break; 281 case KMIN_LANCE_SLOT: 282 mask = KMIN_INTR_LANCE; 283 break; 284 case KMIN_SCC0_SLOT: 285 mask = KMIN_INTR_SCC_0; 286 break; 287 case KMIN_SCC1_SLOT: 288 mask = KMIN_INTR_SCC_1; 289 break; 290 case KMIN_ASIC_SLOT: 291 mask = KMIN_INTR_ASIC; 292 break; 293 default: 294#ifdef DIAGNOSTIC 295 printf("warning: enabling unknown intr %x\n", slotno); 296#endif 297 return; 298 } 299 300#if defined(DEBUG) || defined(DIAGNOSTIC) 301 printf("3MIN: imask %x, %sabling slot %d, sc %p handler %p\n", 302 kmin_tc3_imask, (on? "en" : "dis"), slotno, sc, handler); 303#endif 304 305 /* 306 * Enable the interrupt handler, and if it's an IOASIC 307 * slot, set the IOASIC interrupt mask. 308 * Otherwise, set the appropriate spl level in the R3000 309 * register. 310 * Be careful to set handlers before enabling, and disable 311 * interrupts before clearing handlers. 312 */ 313 314 /* Set the interrupt handler and argument ... */ 315 intrtab[slotno].ih_func = handler; 316 intrtab[slotno].ih_arg = arg; 317 /* ... and set the relevant mask */ 318 if (slotno <= 2) { 319 /* it's an option slot */ 320 int s = splhigh(); 321 s |= mask; 322 splx(s); 323 } else { 324 /* it's a baseboard device going via the ASIC */ 325 kmin_tc3_imask |= mask; 326 } 327 328 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = kmin_tc3_imask; 329 kn02ba_wbflush(); 330} 331 332 333static void 334dec_3min_intr_disestablish(dev, arg) 335 struct device *dev; 336 void *arg; 337{ 338 printf("dec_3min_intr_distestablish: not implemented\n"); 339} 340 341 342/* 343 * 3min hardware interrupts. (DECstation 5000/1xx) 344 */ 345static int 346dec_3min_intr(cpumask, pc, status, cause) 347 unsigned cpumask; 348 unsigned pc; 349 unsigned status; 350 unsigned cause; 351{ 352 static int user_warned = 0; 353 static int intr_depth = 0; 354 u_int32_t old_mask; 355 356 intr_depth++; 357 old_mask = *(u_int32_t *)(ioasic_base + IOASIC_IMSK); 358 359 if (cpumask & MIPS_INT_MASK_4) 360 prom_haltbutton(); 361 362 if (cpumask & MIPS_INT_MASK_3) { 363 /* NB: status & MIPS_INT_MASK3 must also be set */ 364 /* masked interrupts are still observable */ 365 u_int32_t intr, imsk, turnoff; 366 367 turnoff = 0; 368 intr = *(u_int32_t *)(ioasic_base + IOASIC_INTR); 369 imsk = *(u_int32_t *)(ioasic_base + IOASIC_IMSK); 370 intr &= imsk; 371 372 if (intr & IOASIC_INTR_SCSI_PTR_LOAD) { 373 turnoff |= IOASIC_INTR_SCSI_PTR_LOAD; 374#ifdef notdef 375 asc_dma_intr(); 376#endif 377 } 378 379 if (intr & (IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E)) 380 turnoff |= IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E; 381 382 if (intr & IOASIC_INTR_LANCE_READ_E) 383 turnoff |= IOASIC_INTR_LANCE_READ_E; 384 385 if (turnoff) 386 *(u_int32_t *)(ioasic_base + IOASIC_INTR) = ~turnoff; 387 388 if (intr & KMIN_INTR_TIMEOUT) 389 kn02ba_errintr(); 390 391 if (intr & KMIN_INTR_CLOCK) { 392 struct clockframe cf; 393 394 __asm __volatile("lbu $0,48(%0)" :: 395 "r"(ioasic_base + IOASIC_SLOT_8_START)); 396#ifdef MIPS3 397 if (CPUISMIPS3) { 398 latched_cycle_cnt = mips3_cycle_count(); 399 } 400#endif 401 cf.pc = pc; 402 cf.sr = status; 403 hardclock(&cf); 404 intrcnt[HARDCLOCK]++; 405 } 406 407 /* If clock interrups were enabled, re-enable them ASAP. */ 408 if (old_mask & KMIN_INTR_CLOCK) { 409 /* ioctl interrupt mask to splclock and higher */ 410 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) 411 = old_mask & 412 ~(KMIN_INTR_SCC_0|KMIN_INTR_SCC_1 | 413 IOASIC_INTR_LANCE|IOASIC_INTR_SCSI); 414 kn02ba_wbflush(); 415 _splset(MIPS_SR_INT_IE | (status & MIPS_INT_MASK_3)); 416 } 417 418 if (intr_depth > 1) 419 goto done; 420 421 if ((intr & KMIN_INTR_SCC_0) && 422 intrtab[KMIN_SCC0_SLOT].ih_func) { 423 (*(intrtab[KMIN_SCC0_SLOT].ih_func)) 424 (intrtab[KMIN_SCC0_SLOT].ih_arg); 425 intrcnt[SERIAL0_INTR]++; 426 } 427 428 if ((intr & KMIN_INTR_SCC_1) && 429 intrtab[KMIN_SCC1_SLOT].ih_func) { 430 (*(intrtab[KMIN_SCC1_SLOT].ih_func)) 431 (intrtab[KMIN_SCC1_SLOT].ih_arg); 432 intrcnt[SERIAL1_INTR]++; 433 } 434 435#ifdef notyet /* untested */ 436 /* If tty interrupts were enabled, re-enable them ASAP. */ 437 if ((old_mask & (KMIN_INTR_SCC_1|KMIN_INTR_SCC_0)) == 438 (KMIN_INTR_SCC_1|KMIN_INTR_SCC_0)) { 439 *imaskp = old_mask & 440 ~(KMIN_INTR_SCC_0|KMIN_INTR_SCC_1 | 441 IOASIC_INTR_LANCE|IOASIC_INTR_SCSI); 442 kn02ba_wbflush(); 443 } 444 445 /* XXX until we know about SPLs of TC options. */ 446 if (intr_depth > 1) 447 goto done; 448#endif 449 if ((intr & IOASIC_INTR_LANCE) && 450 intrtab[KMIN_LANCE_SLOT].ih_func) { 451 (*(intrtab[KMIN_LANCE_SLOT].ih_func)) 452 (intrtab[KMIN_LANCE_SLOT].ih_arg); 453 intrcnt[LANCE_INTR]++; 454 } 455 456 if ((intr & IOASIC_INTR_SCSI) && 457 intrtab[KMIN_SCSI_SLOT].ih_func) { 458 (*(intrtab[KMIN_SCSI_SLOT].ih_func)) 459 (intrtab[KMIN_SCSI_SLOT].ih_arg); 460 intrcnt[SCSI_INTR]++; 461 } 462 463 if (user_warned && ((intr & KMIN_INTR_PSWARN) == 0)) { 464 printf("%s\n", "Power supply ok now."); 465 user_warned = 0; 466 } 467 if ((intr & KMIN_INTR_PSWARN) && (user_warned < 3)) { 468 user_warned++; 469 printf("%s\n", "Power supply overheating"); 470 } 471 } 472 if ((cpumask & MIPS_INT_MASK_0) && intrtab[0].ih_func) { 473 (*intrtab[0].ih_func)(intrtab[0].ih_arg); 474 intrcnt[SLOT0_INTR]++; 475 } 476 477 if ((cpumask & MIPS_INT_MASK_1) && intrtab[1].ih_func) { 478 (*intrtab[1].ih_func)(intrtab[1].ih_arg); 479 intrcnt[SLOT1_INTR]++; 480 } 481 if ((cpumask & MIPS_INT_MASK_2) && intrtab[2].ih_func) { 482 (*intrtab[2].ih_func)(intrtab[2].ih_arg); 483 intrcnt[SLOT2_INTR]++; 484 } 485 486done: 487 /* restore entry state */ 488 splhigh(); 489 intr_depth--; 490 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = old_mask; 491 492 493 return (MIPS_SR_INT_IE | (status & ~cause & MIPS_HARD_INT_MASK)); 494} 495 496 497 498/* 499 ************************************************************************ 500 * Extra functions 501 ************************************************************************ 502 */ 503 504static void 505kn02ba_wbflush() 506{ 507 /* read twice IOASIC_IMSK */ 508 __asm __volatile("lw $0,%0; lw $0,%0" :: 509 "i"(MIPS_PHYS_TO_KSEG1(KMIN_REG_IMSK))); 510} 511 512static unsigned 513kn02ba_clkread() 514{ 515#ifdef MIPS3 516 if (CPUISMIPS3) { 517 u_int32_t mips3_cycles; 518 519 mips3_cycles = mips3_cycle_count() - latched_cycle_cnt; 520 /* XXX divides take 78 cycles: approximate with * 41/2048 */ 521 return((mips3_cycles >> 6) + (mips3_cycles >> 8) + 522 (mips3_cycles >> 11)); 523 } 524#endif 525 return 0; 526} 527