dec_3min.c revision 1.38
1/* $NetBSD: dec_3min.c,v 1.38 2000/04/05 17:49:55 ad Exp $ */ 2 3/* 4 * Copyright (c) 1998 Jonathan Stone. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Jonathan Stone for 17 * the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Copyright (c) 1988 University of Utah. 35 * Copyright (c) 1992, 1993 36 * The Regents of the University of California. All rights reserved. 37 * 38 * This code is derived from software contributed to Berkeley by 39 * the Systems Programming Group of the University of Utah Computer 40 * Science Department, The Mach Operating System project at 41 * Carnegie-Mellon University and Ralph Campbell. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by the University of 54 * California, Berkeley and its contributors. 55 * 4. Neither the name of the University nor the names of its contributors 56 * may be used to endorse or promote products derived from this software 57 * without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 61 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 62 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 63 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 64 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 65 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69 * SUCH DAMAGE. 70 * 71 * @(#)machdep.c 8.3 (Berkeley) 1/12/94 72 */ 73 74#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 75 76__KERNEL_RCSID(0, "$NetBSD: dec_3min.c,v 1.38 2000/04/05 17:49:55 ad Exp $"); 77 78#include <sys/param.h> 79#include <sys/systm.h> 80#include <sys/device.h> 81 82#include <machine/cpu.h> 83#include <machine/intr.h> 84#include <machine/sysconf.h> 85 86#include <mips/mips/mips_mcclock.h> /* mcclock CPUspeed estimation */ 87 88/* all these to get ioasic_base */ 89#include <dev/tc/tcvar.h> /* tc type definitions for.. */ 90#include <dev/tc/ioasicreg.h> /* ioasic interrrupt masks */ 91#include <dev/tc/ioasicvar.h> /* ioasic_base */ 92 93#include <pmax/pmax/machdep.h> 94#include <pmax/pmax/kmin.h> /* 3min baseboard addresses */ 95#include <pmax/pmax/memc.h> /* 3min/maxine memory errors */ 96#include <pmax/tc/sccvar.h> 97 98#include "rasterconsole.h" 99 100void dec_3min_init __P((void)); /* XXX */ 101static void dec_3min_bus_reset __P((void)); 102static void dec_3min_cons_init __P((void)); 103static int dec_3min_intr __P((unsigned, unsigned, unsigned, unsigned)); 104static void dec_3min_intr_establish __P((struct device *, void *, 105 int, int (*)(void *), void *)); 106 107static void kn02ba_wbflush __P((void)); 108static unsigned kn02ba_clkread __P((void)); 109 110 111/* 112 * Local declarations. 113 */ 114static u_int32_t kmin_tc3_imask; 115 116#ifdef MIPS3 117static unsigned latched_cycle_cnt; 118#endif 119 120 121void 122dec_3min_init() 123{ 124 int physmem_boardmax; 125 126 platform.iobus = "tcbus"; 127 platform.bus_reset = dec_3min_bus_reset; 128 platform.cons_init = dec_3min_cons_init; 129 platform.iointr = dec_3min_intr; 130 platform.intr_establish = dec_3min_intr_establish; 131 platform.memsize = memsize_scan; 132 platform.clkread = kn02ba_clkread; 133 134 /* clear any memory errors */ 135 *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0; 136 kn02ba_wbflush(); 137 138 ioasic_base = MIPS_PHYS_TO_KSEG1(KMIN_SYS_ASIC); 139 mips_hardware_intr = dec_3min_intr; 140 141 /* 142 * Since all the motherboard interrupts come through the 143 * IOASIC, it has to be turned off for all the spls and 144 * since we don't know what kinds of devices are in the 145 * TURBOchannel option slots, just splhigh(). 146 */ 147 splvec.splbio = MIPS_SPL_0_1_2_3; 148 splvec.splnet = MIPS_SPL_0_1_2_3; 149 splvec.spltty = MIPS_SPL_0_1_2_3; 150 splvec.splimp = MIPS_SPL_0_1_2_3; 151 splvec.splclock = MIPS_SPL_0_1_2_3; 152 splvec.splstatclock = MIPS_SPL_0_1_2_3; 153 154 /* enable posting of MIPS_INT_MASK_3 to CAUSE register */ 155 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = KMIN_INTR_CLOCK; 156 /* calibrate cpu_mhz value */ 157 mc_cpuspeed(ioasic_base+IOASIC_SLOT_8_START, MIPS_INT_MASK_3); 158 159 *(u_int32_t *)(ioasic_base + IOASIC_LANCE_DECODE) = 0x3; 160 *(u_int32_t *)(ioasic_base + IOASIC_SCSI_DECODE) = 0xe; 161#if 0 162 *(u_int32_t *)(ioasic_base + IOASIC_SCC0_DECODE) = (0x10|4); 163 *(u_int32_t *)(ioasic_base + IOASIC_SCC1_DECODE) = (0x10|6); 164 *(u_int32_t *)(ioasic_base + IOASIC_CSR) = 0x00000f00; 165#endif 166 167 /* sanitize interrupt mask */ 168 kmin_tc3_imask = (KMIN_INTR_CLOCK|KMIN_INTR_PSWARN|KMIN_INTR_TIMEOUT); 169 *(u_int32_t *)(ioasic_base + IOASIC_INTR) = 0; 170 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = kmin_tc3_imask; 171 172 /* 173 * The kmin memory hardware seems to wrap memory addresses 174 * with 4Mbyte SIMMs, which causes the physmem computation 175 * to lose. Find out how big the SIMMS are and set 176 * max_ physmem accordingly. 177 * XXX Do MAXINEs lose the same way? 178 */ 179 physmem_boardmax = KMIN_PHYS_MEMORY_END + 1; 180 if ((KMIN_MSR_SIZE_16Mb & *(int *)MIPS_PHYS_TO_KSEG1(KMIN_REG_MSR)) 181 == 0) 182 physmem_boardmax = physmem_boardmax >> 2; 183 physmem_boardmax = MIPS_PHYS_TO_KSEG1(physmem_boardmax); 184 185 sprintf(cpu_model, "DECstation 5000/1%d (3MIN)", cpu_mhz); 186} 187 188/* 189 * Initalize the memory system and I/O buses. 190 */ 191static void 192dec_3min_bus_reset() 193{ 194 195 /* 196 * Reset interrupts, clear any errors from newconf probes 197 */ 198 199 *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0; 200 kn02ba_wbflush(); 201 202 *(u_int32_t *)(ioasic_base + IOASIC_INTR) = 0; 203 kn02ba_wbflush(); 204} 205 206static void 207dec_3min_cons_init() 208{ 209 int kbd, crt, screen; 210 extern int tcfb_cnattach __P((int)); /* XXX */ 211 212 kbd = crt = screen = 0; 213 prom_findcons(&kbd, &crt, &screen); 214 215 if (screen > 0) { 216#if NRASTERCONSOLE > 0 217 if (tcfb_cnattach(crt) > 0) { 218 scc_lk201_cnattach(ioasic_base, 0x180000); 219 return; 220 } 221#endif 222 printf("No framebuffer device configured for slot %d: ", crt); 223 printf("using serial console\n"); 224 } 225 /* 226 * Delay to allow PROM putchars to complete. 227 * FIFO depth * character time, 228 * character time = (1000000 / (defaultrate / 10)) 229 */ 230 DELAY(160000000 / 9600); /* XXX */ 231 232 scc_cnattach(ioasic_base, 0x180000); 233} 234 235static void 236dec_3min_intr_establish(dev, cookie, level, handler, arg) 237 struct device *dev; 238 void *cookie; 239 int level; 240 int (*handler) __P((void *)); 241 void *arg; 242{ 243 unsigned mask; 244 245 switch ((int)cookie) { 246 /* slots 0-2 don't interrupt through the IOASIC. */ 247 case SYS_DEV_OPT0: 248 mask = MIPS_INT_MASK_0; 249 break; 250 case SYS_DEV_OPT1: 251 mask = MIPS_INT_MASK_1; 252 break; 253 case SYS_DEV_OPT2: 254 mask = MIPS_INT_MASK_2; 255 break; 256 257 case SYS_DEV_SCSI: 258 mask = (IOASIC_INTR_SCSI | IOASIC_INTR_SCSI_PTR_LOAD | 259 IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E); 260 break; 261 case SYS_DEV_LANCE: 262 mask = KMIN_INTR_LANCE; 263 break; 264 case SYS_DEV_SCC0: 265 mask = KMIN_INTR_SCC_0; 266 break; 267 case SYS_DEV_SCC1: 268 mask = KMIN_INTR_SCC_1; 269 break; 270 default: 271#ifdef DIAGNOSTIC 272 printf("warning: enabling unknown intr %x\n", (int)cookie); 273#endif 274 return; 275 } 276 277#if defined(DEBUG) 278 printf("3MIN: imask %x, enabling slot %d, dev %p handler %p\n", 279 kmin_tc3_imask, (int)cookie, dev, handler); 280#endif 281 282 /* 283 * Enable the interrupt handler, and if it's an IOASIC 284 * slot, set the IOASIC interrupt mask. 285 * Otherwise, set the appropriate spl level in the R3000 286 * register. 287 * Be careful to set handlers before enabling, and disable 288 * interrupts before clearing handlers. 289 */ 290 291 /* Set the interrupt handler and argument ... */ 292 intrtab[(int)cookie].ih_func = handler; 293 intrtab[(int)cookie].ih_arg = arg; 294 /* ... and set the relevant mask */ 295 switch ((int)cookie) { 296 case SYS_DEV_OPT0: 297 case SYS_DEV_OPT1: 298 case SYS_DEV_OPT2: 299 /* it's an option slot */ 300 { 301 int s = splhigh(); 302 s |= mask; 303 splx(s); 304 } 305 break; 306 default: 307 /* it's a baseboard device going via the IOASIC */ 308 kmin_tc3_imask |= mask; 309 break; 310 } 311 312 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = kmin_tc3_imask; 313 kn02ba_wbflush(); 314} 315 316 317#define CHECKINTR(slot, bits) \ 318 do { \ 319 if (can_serve & (bits)) { \ 320 intrcnt[slot] += 1; \ 321 (*intrtab[slot].ih_func)(intrtab[slot].ih_arg); \ 322 } \ 323 } while (0) 324 325static int 326dec_3min_intr(cpumask, pc, status, cause) 327 unsigned cpumask; 328 unsigned pc; 329 unsigned status; 330 unsigned cause; 331{ 332 static int user_warned = 0; 333 static int intr_depth = 0; 334 u_int32_t old_mask; 335 336 intr_depth++; 337 old_mask = *(u_int32_t *)(ioasic_base + IOASIC_IMSK); 338 339 if (cpumask & MIPS_INT_MASK_4) 340 prom_haltbutton(); 341 342 if (cpumask & MIPS_INT_MASK_3) { 343 /* NB: status & MIPS_INT_MASK3 must also be set */ 344 /* masked interrupts are still observable */ 345 u_int32_t intr, imsk, can_serve, turnoff; 346 347 turnoff = 0; 348 intr = *(u_int32_t *)(ioasic_base + IOASIC_INTR); 349 imsk = *(u_int32_t *)(ioasic_base + IOASIC_IMSK); 350 can_serve = intr & imsk; 351 352 if (intr & IOASIC_INTR_SCSI_PTR_LOAD) { 353 turnoff |= IOASIC_INTR_SCSI_PTR_LOAD; 354#ifdef notdef 355 asc_dma_intr(); 356#endif 357 } 358 359 if (intr & (IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E)) 360 turnoff |= IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E; 361 362 if (intr & IOASIC_INTR_LANCE_READ_E) 363 turnoff |= IOASIC_INTR_LANCE_READ_E; 364 365 if (turnoff) 366 *(u_int32_t *)(ioasic_base + IOASIC_INTR) = ~turnoff; 367 368 if (intr & KMIN_INTR_TIMEOUT) 369 kn02ba_errintr(); 370 371 if (intr & KMIN_INTR_CLOCK) { 372 struct clockframe cf; 373 374 __asm __volatile("lbu $0,48(%0)" :: 375 "r"(ioasic_base + IOASIC_SLOT_8_START)); 376#ifdef MIPS3 377 if (CPUISMIPS3) { 378 latched_cycle_cnt = mips3_cycle_count(); 379 } 380#endif 381 cf.pc = pc; 382 cf.sr = status; 383 hardclock(&cf); 384 intrcnt[HARDCLOCK]++; 385 } 386 387 /* If clock interrups were enabled, re-enable them ASAP. */ 388 if (old_mask & KMIN_INTR_CLOCK) { 389 /* ioctl interrupt mask to splclock and higher */ 390 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) 391 = old_mask & 392 ~(KMIN_INTR_SCC_0|KMIN_INTR_SCC_1 | 393 IOASIC_INTR_LANCE|IOASIC_INTR_SCSI); 394 kn02ba_wbflush(); 395 _splset(MIPS_SR_INT_IE | (status & MIPS_INT_MASK_3)); 396 } 397 398 if (intr_depth > 1) 399 goto done; 400 401 CHECKINTR(SYS_DEV_SCC0, IOASIC_INTR_SCC_0); 402 CHECKINTR(SYS_DEV_SCC1, IOASIC_INTR_SCC_1); 403 404#ifdef notyet /* untested */ 405 /* If tty interrupts were enabled, re-enable them ASAP. */ 406 if ((old_mask & (KMIN_INTR_SCC_1|KMIN_INTR_SCC_0)) == 407 (KMIN_INTR_SCC_1|KMIN_INTR_SCC_0)) { 408 *imaskp = old_mask & 409 ~(KMIN_INTR_SCC_0|KMIN_INTR_SCC_1 | 410 IOASIC_INTR_LANCE|IOASIC_INTR_SCSI); 411 kn02ba_wbflush(); 412 } 413 414 /* XXX until we know about SPLs of TC options. */ 415 if (intr_depth > 1) 416 goto done; 417#endif 418 CHECKINTR(SYS_DEV_LANCE, IOASIC_INTR_LANCE); 419 CHECKINTR(SYS_DEV_SCSI, IOASIC_INTR_SCSI); 420 421 if (user_warned && ((intr & KMIN_INTR_PSWARN) == 0)) { 422 printf("%s\n", "Power supply ok now."); 423 user_warned = 0; 424 } 425 if ((intr & KMIN_INTR_PSWARN) && (user_warned < 3)) { 426 user_warned++; 427 printf("%s\n", "Power supply overheating"); 428 } 429 } 430 if ((cpumask & MIPS_INT_MASK_0) && intrtab[SYS_DEV_OPT0].ih_func) { 431 (*intrtab[SYS_DEV_OPT0].ih_func)(intrtab[SYS_DEV_OPT0].ih_arg); 432 intrcnt[SYS_DEV_OPT0]++; 433 } 434 435 if ((cpumask & MIPS_INT_MASK_1) && intrtab[SYS_DEV_OPT1].ih_func) { 436 (*intrtab[SYS_DEV_OPT1].ih_func)(intrtab[SYS_DEV_OPT1].ih_arg); 437 intrcnt[SYS_DEV_OPT1]++; 438 } 439 if ((cpumask & MIPS_INT_MASK_2) && intrtab[SYS_DEV_OPT2].ih_func) { 440 (*intrtab[SYS_DEV_OPT2].ih_func)(intrtab[SYS_DEV_OPT2].ih_arg); 441 intrcnt[SYS_DEV_OPT2]++; 442 } 443 444done: 445 /* restore entry state */ 446 splhigh(); 447 intr_depth--; 448 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = old_mask; 449 450 451 return (MIPS_SR_INT_IE | (status & ~cause & MIPS_HARD_INT_MASK)); 452} 453 454 455 456/* 457 ************************************************************************ 458 * Extra functions 459 ************************************************************************ 460 */ 461 462static void 463kn02ba_wbflush() 464{ 465 /* read twice IOASIC_IMSK */ 466 __asm __volatile("lw $0,%0; lw $0,%0" :: 467 "i"(MIPS_PHYS_TO_KSEG1(KMIN_REG_IMSK))); 468} 469 470static unsigned 471kn02ba_clkread() 472{ 473#ifdef MIPS3 474 if (CPUISMIPS3) { 475 u_int32_t mips3_cycles; 476 477 mips3_cycles = mips3_cycle_count() - latched_cycle_cnt; 478 /* XXX divides take 78 cycles: approximate with * 41/2048 */ 479 return((mips3_cycles >> 6) + (mips3_cycles >> 8) + 480 (mips3_cycles >> 11)); 481 } 482#endif 483 return 0; 484} 485