dec_3min.c revision 1.54
1/* $NetBSD: dec_3min.c,v 1.54 2005/12/24 20:07:25 perry Exp $ */ 2 3/* 4 * Copyright (c) 1998 Jonathan Stone. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Jonathan Stone for 17 * the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Copyright (c) 1992, 1993 35 * The Regents of the University of California. All rights reserved. 36 * 37 * This code is derived from software contributed to Berkeley by 38 * the Systems Programming Group of the University of Utah Computer 39 * Science Department, The Mach Operating System project at 40 * Carnegie-Mellon University and Ralph Campbell. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. Neither the name of the University nor the names of its contributors 51 * may be used to endorse or promote products derived from this software 52 * without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 55 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 56 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 57 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 58 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 59 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 60 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 62 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 63 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 * 66 * @(#)machdep.c 8.3 (Berkeley) 1/12/94 67 */ 68/* 69 * Copyright (c) 1988 University of Utah. 70 * 71 * This code is derived from software contributed to Berkeley by 72 * the Systems Programming Group of the University of Utah Computer 73 * Science Department, The Mach Operating System project at 74 * Carnegie-Mellon University and Ralph Campbell. 75 * 76 * Redistribution and use in source and binary forms, with or without 77 * modification, are permitted provided that the following conditions 78 * are met: 79 * 1. Redistributions of source code must retain the above copyright 80 * notice, this list of conditions and the following disclaimer. 81 * 2. Redistributions in binary form must reproduce the above copyright 82 * notice, this list of conditions and the following disclaimer in the 83 * documentation and/or other materials provided with the distribution. 84 * 3. All advertising materials mentioning features or use of this software 85 * must display the following acknowledgement: 86 * This product includes software developed by the University of 87 * California, Berkeley and its contributors. 88 * 4. Neither the name of the University nor the names of its contributors 89 * may be used to endorse or promote products derived from this software 90 * without specific prior written permission. 91 * 92 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 93 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 94 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 95 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 96 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 97 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 98 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 99 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 100 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 101 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 102 * SUCH DAMAGE. 103 * 104 * @(#)machdep.c 8.3 (Berkeley) 1/12/94 105 */ 106 107#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 108 109__KERNEL_RCSID(0, "$NetBSD: dec_3min.c,v 1.54 2005/12/24 20:07:25 perry Exp $"); 110 111#include <sys/param.h> 112#include <sys/systm.h> 113#include <sys/device.h> 114 115#include <machine/cpu.h> 116#include <machine/intr.h> 117#include <machine/sysconf.h> 118 119#include <mips/mips/mips_mcclock.h> /* mcclock CPUspeed estimation */ 120 121/* all these to get ioasic_base */ 122#include <dev/tc/tcvar.h> /* tc type definitions for.. */ 123#include <dev/tc/ioasicreg.h> /* ioasic interrrupt masks */ 124#include <dev/tc/ioasicvar.h> /* ioasic_base */ 125 126#include <pmax/pmax/machdep.h> 127#include <pmax/pmax/kmin.h> /* 3min baseboard addresses */ 128#include <pmax/pmax/memc.h> /* 3min/maxine memory errors */ 129 130#ifdef WSCONS 131#include <pmax/pmax/cons.h> 132#include <dev/ic/z8530sc.h> 133#include <dev/tc/zs_ioasicvar.h> 134#include "wsdisplay.h" 135#else 136#include <pmax/tc/sccvar.h> 137#include "rasterconsole.h" 138#endif 139 140void dec_3min_init __P((void)); /* XXX */ 141static void dec_3min_bus_reset __P((void)); 142static void dec_3min_cons_init __P((void)); 143static void dec_3min_intr __P((unsigned, unsigned, unsigned, unsigned)); 144static void dec_3min_intr_establish __P((struct device *, void *, 145 int, int (*)(void *), void *)); 146 147static void kn02ba_wbflush __P((void)); 148static unsigned kn02ba_clkread __P((void)); 149 150 151/* 152 * Local declarations. 153 */ 154static u_int32_t kmin_tc3_imask; 155 156#ifdef MIPS3 157static unsigned latched_cycle_cnt; 158#endif 159 160 161void 162dec_3min_init() 163{ 164 platform.iobus = "tcbus"; 165 platform.bus_reset = dec_3min_bus_reset; 166 platform.cons_init = dec_3min_cons_init; 167 platform.iointr = dec_3min_intr; 168 platform.intr_establish = dec_3min_intr_establish; 169 platform.memsize = memsize_bitmap; 170 platform.clkread = kn02ba_clkread; 171 172 /* clear any memory errors */ 173 *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0; 174 kn02ba_wbflush(); 175 176 ioasic_base = MIPS_PHYS_TO_KSEG1(KMIN_SYS_ASIC); 177 178 /* 179 * Since all the motherboard interrupts come through the 180 * IOASIC, it has to be turned off for all the spls and 181 * since we don't know what kinds of devices are in the 182 * TURBOchannel option slots, just splhigh(). 183 */ 184 splvec.splbio = MIPS_SPL_0_1_2_3; 185 splvec.splnet = MIPS_SPL_0_1_2_3; 186 splvec.spltty = MIPS_SPL_0_1_2_3; 187 splvec.splvm = MIPS_SPL_0_1_2_3; 188 splvec.splclock = MIPS_SPL_0_1_2_3; 189 splvec.splstatclock = MIPS_SPL_0_1_2_3; 190 191 /* enable posting of MIPS_INT_MASK_3 to CAUSE register */ 192 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = KMIN_INTR_CLOCK; 193 /* calibrate cpu_mhz value */ 194 mc_cpuspeed(ioasic_base+IOASIC_SLOT_8_START, MIPS_INT_MASK_3); 195 196 *(u_int32_t *)(ioasic_base + IOASIC_LANCE_DECODE) = 0x3; 197 *(u_int32_t *)(ioasic_base + IOASIC_SCSI_DECODE) = 0xe; 198#if 0 199 *(u_int32_t *)(ioasic_base + IOASIC_SCC0_DECODE) = (0x10|4); 200 *(u_int32_t *)(ioasic_base + IOASIC_SCC1_DECODE) = (0x10|6); 201 *(u_int32_t *)(ioasic_base + IOASIC_CSR) = 0x00000f00; 202#endif 203 204 /* sanitize interrupt mask */ 205 kmin_tc3_imask = (KMIN_INTR_CLOCK|KMIN_INTR_PSWARN|KMIN_INTR_TIMEOUT); 206 *(u_int32_t *)(ioasic_base + IOASIC_INTR) = 0; 207 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = kmin_tc3_imask; 208 209 /* 210 * The kmin memory hardware seems to wrap memory addresses 211 * with 4Mbyte SIMMs, which causes the physmem computation 212 * to lose. Find out how big the SIMMS are and set 213 * max_ physmem accordingly. 214 * XXX Do MAXINEs lose the same way? 215 */ 216 physmem_boardmax = KMIN_PHYS_MEMORY_END + 1; 217 if ((KMIN_MSR_SIZE_16Mb & *(int *)MIPS_PHYS_TO_KSEG1(KMIN_REG_MSR)) 218 == 0) 219 physmem_boardmax = physmem_boardmax >> 2; 220 physmem_boardmax = MIPS_PHYS_TO_KSEG1(physmem_boardmax); 221 222 sprintf(cpu_model, "DECstation 5000/1%d (3MIN)", cpu_mhz); 223} 224 225/* 226 * Initialize the memory system and I/O buses. 227 */ 228static void 229dec_3min_bus_reset() 230{ 231 232 /* 233 * Reset interrupts, clear any errors from newconf probes 234 */ 235 236 *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0; 237 kn02ba_wbflush(); 238 239 *(u_int32_t *)(ioasic_base + IOASIC_INTR) = 0; 240 kn02ba_wbflush(); 241} 242 243static void 244dec_3min_cons_init() 245{ 246 int kbd, crt, screen; 247 248 kbd = crt = screen = 0; 249 prom_findcons(&kbd, &crt, &screen); 250 251 if (screen > 0) { 252#if NWSDISPLAY > 0 253 if (tcfb_cnattach(crt) > 0) { 254 zs_ioasic_lk201_cnattach(ioasic_base, 0x180000, 0); 255 return; 256 } 257#elif NRASTERCONSOLE > 0 258 extern int tcfb_cnattach __P((int)); /* XXX */ 259 260 if (tcfb_cnattach(crt) > 0) { 261 scc_lk201_cnattach(ioasic_base, 0x180000); 262 return; 263 } 264#endif 265 printf("No framebuffer device configured for slot %d: ", crt); 266 printf("using serial console\n"); 267 } 268 /* 269 * Delay to allow PROM putchars to complete. 270 * FIFO depth * character time, 271 * character time = (1000000 / (defaultrate / 10)) 272 */ 273 DELAY(160000000 / 9600); /* XXX */ 274 275#ifdef WSCONS 276 zs_ioasic_cnattach(ioasic_base, 0x180000, 1); 277#else 278 scc_cnattach(ioasic_base, 0x180000); 279#endif 280} 281 282static void 283dec_3min_intr_establish(dev, cookie, level, handler, arg) 284 struct device *dev; 285 void *cookie; 286 int level; 287 int (*handler) __P((void *)); 288 void *arg; 289{ 290 unsigned mask; 291 292 switch ((int)cookie) { 293 /* slots 0-2 don't interrupt through the IOASIC. */ 294 case SYS_DEV_OPT0: 295 mask = MIPS_INT_MASK_0; 296 break; 297 case SYS_DEV_OPT1: 298 mask = MIPS_INT_MASK_1; 299 break; 300 case SYS_DEV_OPT2: 301 mask = MIPS_INT_MASK_2; 302 break; 303 304 case SYS_DEV_SCSI: 305 mask = (IOASIC_INTR_SCSI | IOASIC_INTR_SCSI_PTR_LOAD | 306 IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E); 307 break; 308 case SYS_DEV_LANCE: 309 mask = KMIN_INTR_LANCE; 310 break; 311 case SYS_DEV_SCC0: 312 mask = KMIN_INTR_SCC_0; 313 break; 314 case SYS_DEV_SCC1: 315 mask = KMIN_INTR_SCC_1; 316 break; 317 default: 318#ifdef DIAGNOSTIC 319 printf("warning: enabling unknown intr %x\n", (int)cookie); 320#endif 321 return; 322 } 323 324#if defined(DEBUG) 325 printf("3MIN: imask %x, enabling slot %d, dev %p handler %p\n", 326 kmin_tc3_imask, (int)cookie, dev, handler); 327#endif 328 329 /* 330 * Enable the interrupt handler, and if it's an IOASIC 331 * slot, set the IOASIC interrupt mask. 332 * Otherwise, set the appropriate spl level in the R3000 333 * register. 334 * Be careful to set handlers before enabling, and disable 335 * interrupts before clearing handlers. 336 */ 337 338 /* Set the interrupt handler and argument ... */ 339 intrtab[(int)cookie].ih_func = handler; 340 intrtab[(int)cookie].ih_arg = arg; 341 /* ... and set the relevant mask */ 342 switch ((int)cookie) { 343 case SYS_DEV_OPT0: 344 case SYS_DEV_OPT1: 345 case SYS_DEV_OPT2: 346 /* it's an option slot */ 347 { 348 int s = splhigh(); 349 s |= mask; 350 splx(s); 351 } 352 break; 353 default: 354 /* it's a baseboard device going via the IOASIC */ 355 kmin_tc3_imask |= mask; 356 break; 357 } 358 359 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = kmin_tc3_imask; 360 kn02ba_wbflush(); 361} 362 363 364#define CHECKINTR(slot, bits) \ 365 do { \ 366 if (can_serve & (bits)) { \ 367 intrtab[slot].ih_count.ev_count++; \ 368 (*intrtab[slot].ih_func)(intrtab[slot].ih_arg); \ 369 } \ 370 } while (0) 371 372static void 373dec_3min_intr(status, cause, pc, ipending) 374 unsigned status; 375 unsigned cause; 376 unsigned pc; 377 unsigned ipending; 378{ 379 static int user_warned = 0; 380 static int intr_depth = 0; 381 u_int32_t old_mask; 382 383 intr_depth++; 384 old_mask = *(u_int32_t *)(ioasic_base + IOASIC_IMSK); 385 386 if (ipending & MIPS_INT_MASK_4) 387 prom_haltbutton(); 388 389 if (ipending & MIPS_INT_MASK_3) { 390 /* NB: status & MIPS_INT_MASK3 must also be set */ 391 /* masked interrupts are still observable */ 392 u_int32_t intr, imsk, can_serve, turnoff; 393 394 turnoff = 0; 395 intr = *(u_int32_t *)(ioasic_base + IOASIC_INTR); 396 imsk = *(u_int32_t *)(ioasic_base + IOASIC_IMSK); 397 can_serve = intr & imsk; 398 399 if (intr & IOASIC_INTR_SCSI_PTR_LOAD) { 400 turnoff |= IOASIC_INTR_SCSI_PTR_LOAD; 401#ifdef notdef 402 asc_dma_intr(); 403#endif 404 } 405 406 if (intr & (IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E)) 407 turnoff |= IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E; 408 409 if (intr & IOASIC_INTR_LANCE_READ_E) 410 turnoff |= IOASIC_INTR_LANCE_READ_E; 411 412 if (turnoff) 413 *(u_int32_t *)(ioasic_base + IOASIC_INTR) = ~turnoff; 414 415 if (intr & KMIN_INTR_TIMEOUT) { 416 kn02ba_errintr(); 417 pmax_memerr_evcnt.ev_count++; 418 } 419 420 if (intr & KMIN_INTR_CLOCK) { 421 struct clockframe cf; 422 423 __asm volatile("lbu $0,48(%0)" :: 424 "r"(ioasic_base + IOASIC_SLOT_8_START)); 425#ifdef MIPS3 426 if (CPUISMIPS3) { 427 latched_cycle_cnt = mips3_cp0_count_read(); 428 } 429#endif 430 cf.pc = pc; 431 cf.sr = status; 432 hardclock(&cf); 433 pmax_clock_evcnt.ev_count++; 434 } 435 436 /* If clock interrups were enabled, re-enable them ASAP. */ 437 if (old_mask & KMIN_INTR_CLOCK) { 438 /* ioctl interrupt mask to splclock and higher */ 439 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) 440 = old_mask & 441 ~(KMIN_INTR_SCC_0|KMIN_INTR_SCC_1 | 442 IOASIC_INTR_LANCE|IOASIC_INTR_SCSI); 443 kn02ba_wbflush(); 444 _splset(MIPS_SR_INT_IE | (status & MIPS_INT_MASK_3)); 445 } 446 447 if (intr_depth > 1) 448 goto done; 449 450 CHECKINTR(SYS_DEV_SCC0, IOASIC_INTR_SCC_0); 451 CHECKINTR(SYS_DEV_SCC1, IOASIC_INTR_SCC_1); 452 453#ifdef notyet /* untested */ 454 /* If tty interrupts were enabled, re-enable them ASAP. */ 455 if ((old_mask & (KMIN_INTR_SCC_1|KMIN_INTR_SCC_0)) == 456 (KMIN_INTR_SCC_1|KMIN_INTR_SCC_0)) { 457 *imaskp = old_mask & 458 ~(KMIN_INTR_SCC_0|KMIN_INTR_SCC_1 | 459 IOASIC_INTR_LANCE|IOASIC_INTR_SCSI); 460 kn02ba_wbflush(); 461 } 462 463 /* XXX until we know about SPLs of TC options. */ 464 if (intr_depth > 1) 465 goto done; 466#endif 467 CHECKINTR(SYS_DEV_LANCE, IOASIC_INTR_LANCE); 468 CHECKINTR(SYS_DEV_SCSI, IOASIC_INTR_SCSI); 469 470 if (user_warned && ((intr & KMIN_INTR_PSWARN) == 0)) { 471 printf("%s\n", "Power supply ok now."); 472 user_warned = 0; 473 } 474 if ((intr & KMIN_INTR_PSWARN) && (user_warned < 3)) { 475 user_warned++; 476 printf("%s\n", "Power supply overheating"); 477 } 478 } 479 if ((ipending & MIPS_INT_MASK_0) && intrtab[SYS_DEV_OPT0].ih_func) { 480 (*intrtab[SYS_DEV_OPT0].ih_func)(intrtab[SYS_DEV_OPT0].ih_arg); 481 intrtab[SYS_DEV_OPT0].ih_count.ev_count++; 482 } 483 484 if ((ipending & MIPS_INT_MASK_1) && intrtab[SYS_DEV_OPT1].ih_func) { 485 (*intrtab[SYS_DEV_OPT1].ih_func)(intrtab[SYS_DEV_OPT1].ih_arg); 486 intrtab[SYS_DEV_OPT1].ih_count.ev_count++; 487 } 488 if ((ipending & MIPS_INT_MASK_2) && intrtab[SYS_DEV_OPT2].ih_func) { 489 (*intrtab[SYS_DEV_OPT2].ih_func)(intrtab[SYS_DEV_OPT2].ih_arg); 490 intrtab[SYS_DEV_OPT2].ih_count.ev_count++; 491 } 492 493done: 494 /* restore entry state */ 495 splhigh(); 496 intr_depth--; 497 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = old_mask; 498 499 _splset(MIPS_SR_INT_IE | (status & ~cause & MIPS_HARD_INT_MASK)); 500} 501 502 503 504/* 505 ************************************************************************ 506 * Extra functions 507 ************************************************************************ 508 */ 509 510static void 511kn02ba_wbflush() 512{ 513 /* read twice IOASIC_IMSK */ 514 __asm volatile("lw $0,%0; lw $0,%0" :: 515 "i"(MIPS_PHYS_TO_KSEG1(KMIN_REG_IMSK))); 516} 517 518static unsigned 519kn02ba_clkread() 520{ 521#ifdef MIPS3 522 if (CPUISMIPS3) { 523 u_int32_t mips3_cycles; 524 525 mips3_cycles = mips3_cp0_count_read() - latched_cycle_cnt; 526 /* XXX divides take 78 cycles: approximate with * 41/2048 */ 527 return((mips3_cycles >> 6) + (mips3_cycles >> 8) + 528 (mips3_cycles >> 11)); 529 } 530#endif 531 return 0; 532} 533