dec_3min.c revision 1.57
1/* $NetBSD: dec_3min.c,v 1.57 2006/12/21 15:55:24 yamt Exp $ */ 2 3/* 4 * Copyright (c) 1998 Jonathan Stone. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Jonathan Stone for 17 * the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Copyright (c) 1992, 1993 35 * The Regents of the University of California. All rights reserved. 36 * 37 * This code is derived from software contributed to Berkeley by 38 * the Systems Programming Group of the University of Utah Computer 39 * Science Department, The Mach Operating System project at 40 * Carnegie-Mellon University and Ralph Campbell. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. Neither the name of the University nor the names of its contributors 51 * may be used to endorse or promote products derived from this software 52 * without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 55 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 56 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 57 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 58 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 59 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 60 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 62 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 63 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 * 66 * @(#)machdep.c 8.3 (Berkeley) 1/12/94 67 */ 68/* 69 * Copyright (c) 1988 University of Utah. 70 * 71 * This code is derived from software contributed to Berkeley by 72 * the Systems Programming Group of the University of Utah Computer 73 * Science Department, The Mach Operating System project at 74 * Carnegie-Mellon University and Ralph Campbell. 75 * 76 * Redistribution and use in source and binary forms, with or without 77 * modification, are permitted provided that the following conditions 78 * are met: 79 * 1. Redistributions of source code must retain the above copyright 80 * notice, this list of conditions and the following disclaimer. 81 * 2. Redistributions in binary form must reproduce the above copyright 82 * notice, this list of conditions and the following disclaimer in the 83 * documentation and/or other materials provided with the distribution. 84 * 3. All advertising materials mentioning features or use of this software 85 * must display the following acknowledgement: 86 * This product includes software developed by the University of 87 * California, Berkeley and its contributors. 88 * 4. Neither the name of the University nor the names of its contributors 89 * may be used to endorse or promote products derived from this software 90 * without specific prior written permission. 91 * 92 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 93 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 94 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 95 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 96 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 97 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 98 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 99 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 100 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 101 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 102 * SUCH DAMAGE. 103 * 104 * @(#)machdep.c 8.3 (Berkeley) 1/12/94 105 */ 106 107#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 108 109__KERNEL_RCSID(0, "$NetBSD: dec_3min.c,v 1.57 2006/12/21 15:55:24 yamt Exp $"); 110 111#include <sys/param.h> 112#include <sys/systm.h> 113#include <sys/device.h> 114 115#include <machine/cpu.h> 116#include <machine/intr.h> 117#include <machine/sysconf.h> 118 119#include <mips/mips/mips_mcclock.h> /* mcclock CPUspeed estimation */ 120 121/* all these to get ioasic_base */ 122#include <dev/tc/tcvar.h> /* tc type definitions for.. */ 123#include <dev/tc/ioasicreg.h> /* ioasic interrrupt masks */ 124#include <dev/tc/ioasicvar.h> /* ioasic_base */ 125 126#include <pmax/pmax/machdep.h> 127#include <pmax/pmax/kmin.h> /* 3min baseboard addresses */ 128#include <pmax/pmax/memc.h> /* 3min/maxine memory errors */ 129 130#include <pmax/pmax/cons.h> 131#include <dev/ic/z8530sc.h> 132#include <dev/tc/zs_ioasicvar.h> 133#include "wsdisplay.h" 134 135void dec_3min_init __P((void)); /* XXX */ 136static void dec_3min_bus_reset __P((void)); 137static void dec_3min_cons_init __P((void)); 138static void dec_3min_intr __P((unsigned, unsigned, unsigned, unsigned)); 139static void dec_3min_intr_establish __P((struct device *, void *, 140 int, int (*)(void *), void *)); 141 142static void kn02ba_wbflush __P((void)); 143static unsigned kn02ba_clkread __P((void)); 144 145 146/* 147 * Local declarations. 148 */ 149static u_int32_t kmin_tc3_imask; 150 151#ifdef MIPS3 152static unsigned latched_cycle_cnt; 153#endif 154 155static const int dec_3min_ipl2spl_table[] = { 156 [IPL_NONE] = 0, 157 [IPL_SOFT] = _SPL_SOFT, 158 [IPL_SOFTCLOCK] = _SPL_SOFTCLOCK, 159 [IPL_SOFTNET] = _SPL_SOFTNET, 160 [IPL_SOFTSERIAL] = _SPL_SOFTSERIAL, 161 /* 162 * Since all the motherboard interrupts come through the 163 * IOASIC, it has to be turned off for all the spls and 164 * since we don't know what kinds of devices are in the 165 * TURBOchannel option slots, just splhigh(). 166 */ 167 [IPL_BIO] = MIPS_SPL_0_1_2_3, 168 [IPL_NET] = MIPS_SPL_0_1_2_3, 169 [IPL_TTY] = MIPS_SPL_0_1_2_3, 170 [IPL_VM] = MIPS_SPL_0_1_2_3, 171 [IPL_CLOCK] = MIPS_SPL_0_1_2_3, 172 [IPL_STATCLOCK] = MIPS_SPL_0_1_2_3, 173}; 174 175void 176dec_3min_init() 177{ 178 platform.iobus = "tcbus"; 179 platform.bus_reset = dec_3min_bus_reset; 180 platform.cons_init = dec_3min_cons_init; 181 platform.iointr = dec_3min_intr; 182 platform.intr_establish = dec_3min_intr_establish; 183 platform.memsize = memsize_bitmap; 184 platform.clkread = kn02ba_clkread; 185 186 /* clear any memory errors */ 187 *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0; 188 kn02ba_wbflush(); 189 190 ioasic_base = MIPS_PHYS_TO_KSEG1(KMIN_SYS_ASIC); 191 192 ipl2spl_table = dec_3min_ipl2spl_table; 193 194 /* enable posting of MIPS_INT_MASK_3 to CAUSE register */ 195 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = KMIN_INTR_CLOCK; 196 /* calibrate cpu_mhz value */ 197 mc_cpuspeed(ioasic_base+IOASIC_SLOT_8_START, MIPS_INT_MASK_3); 198 199 *(u_int32_t *)(ioasic_base + IOASIC_LANCE_DECODE) = 0x3; 200 *(u_int32_t *)(ioasic_base + IOASIC_SCSI_DECODE) = 0xe; 201#if 0 202 *(u_int32_t *)(ioasic_base + IOASIC_SCC0_DECODE) = (0x10|4); 203 *(u_int32_t *)(ioasic_base + IOASIC_SCC1_DECODE) = (0x10|6); 204 *(u_int32_t *)(ioasic_base + IOASIC_CSR) = 0x00000f00; 205#endif 206 207 /* sanitize interrupt mask */ 208 kmin_tc3_imask = (KMIN_INTR_CLOCK|KMIN_INTR_PSWARN|KMIN_INTR_TIMEOUT); 209 *(u_int32_t *)(ioasic_base + IOASIC_INTR) = 0; 210 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = kmin_tc3_imask; 211 212 /* 213 * The kmin memory hardware seems to wrap memory addresses 214 * with 4Mbyte SIMMs, which causes the physmem computation 215 * to lose. Find out how big the SIMMS are and set 216 * max_ physmem accordingly. 217 * XXX Do MAXINEs lose the same way? 218 */ 219 physmem_boardmax = KMIN_PHYS_MEMORY_END + 1; 220 if ((KMIN_MSR_SIZE_16Mb & *(int *)MIPS_PHYS_TO_KSEG1(KMIN_REG_MSR)) 221 == 0) 222 physmem_boardmax = physmem_boardmax >> 2; 223 physmem_boardmax = MIPS_PHYS_TO_KSEG1(physmem_boardmax); 224 225 sprintf(cpu_model, "DECstation 5000/1%d (3MIN)", cpu_mhz); 226} 227 228/* 229 * Initialize the memory system and I/O buses. 230 */ 231static void 232dec_3min_bus_reset() 233{ 234 235 /* 236 * Reset interrupts, clear any errors from newconf probes 237 */ 238 239 *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0; 240 kn02ba_wbflush(); 241 242 *(u_int32_t *)(ioasic_base + IOASIC_INTR) = 0; 243 kn02ba_wbflush(); 244} 245 246static void 247dec_3min_cons_init() 248{ 249 int kbd, crt, screen; 250 251 kbd = crt = screen = 0; 252 prom_findcons(&kbd, &crt, &screen); 253 254 if (screen > 0) { 255#if NWSDISPLAY > 0 256 if (tcfb_cnattach(crt) > 0) { 257 zs_ioasic_lk201_cnattach(ioasic_base, 0x180000, 0); 258 return; 259 } 260#endif 261 printf("No framebuffer device configured for slot %d: ", crt); 262 printf("using serial console\n"); 263 } 264 /* 265 * Delay to allow PROM putchars to complete. 266 * FIFO depth * character time, 267 * character time = (1000000 / (defaultrate / 10)) 268 */ 269 DELAY(160000000 / 9600); /* XXX */ 270 271 zs_ioasic_cnattach(ioasic_base, 0x180000, 1); 272} 273 274static void 275dec_3min_intr_establish(dev, cookie, level, handler, arg) 276 struct device *dev; 277 void *cookie; 278 int level; 279 int (*handler) __P((void *)); 280 void *arg; 281{ 282 unsigned mask; 283 284 switch ((int)cookie) { 285 /* slots 0-2 don't interrupt through the IOASIC. */ 286 case SYS_DEV_OPT0: 287 mask = MIPS_INT_MASK_0; 288 break; 289 case SYS_DEV_OPT1: 290 mask = MIPS_INT_MASK_1; 291 break; 292 case SYS_DEV_OPT2: 293 mask = MIPS_INT_MASK_2; 294 break; 295 296 case SYS_DEV_SCSI: 297 mask = (IOASIC_INTR_SCSI | IOASIC_INTR_SCSI_PTR_LOAD | 298 IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E); 299 break; 300 case SYS_DEV_LANCE: 301 mask = KMIN_INTR_LANCE; 302 break; 303 case SYS_DEV_SCC0: 304 mask = KMIN_INTR_SCC_0; 305 break; 306 case SYS_DEV_SCC1: 307 mask = KMIN_INTR_SCC_1; 308 break; 309 default: 310#ifdef DIAGNOSTIC 311 printf("warning: enabling unknown intr %x\n", (int)cookie); 312#endif 313 return; 314 } 315 316#if defined(DEBUG) 317 printf("3MIN: imask %x, enabling slot %d, dev %p handler %p\n", 318 kmin_tc3_imask, (int)cookie, dev, handler); 319#endif 320 321 /* 322 * Enable the interrupt handler, and if it's an IOASIC 323 * slot, set the IOASIC interrupt mask. 324 * Otherwise, set the appropriate spl level in the R3000 325 * register. 326 * Be careful to set handlers before enabling, and disable 327 * interrupts before clearing handlers. 328 */ 329 330 /* Set the interrupt handler and argument ... */ 331 intrtab[(int)cookie].ih_func = handler; 332 intrtab[(int)cookie].ih_arg = arg; 333 /* ... and set the relevant mask */ 334 switch ((int)cookie) { 335 case SYS_DEV_OPT0: 336 case SYS_DEV_OPT1: 337 case SYS_DEV_OPT2: 338 /* it's an option slot */ 339 { 340 int s = splhigh(); 341 s |= mask; 342 splx(s); 343 } 344 break; 345 default: 346 /* it's a baseboard device going via the IOASIC */ 347 kmin_tc3_imask |= mask; 348 break; 349 } 350 351 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = kmin_tc3_imask; 352 kn02ba_wbflush(); 353} 354 355 356#define CHECKINTR(slot, bits) \ 357 do { \ 358 if (can_serve & (bits)) { \ 359 intrtab[slot].ih_count.ev_count++; \ 360 (*intrtab[slot].ih_func)(intrtab[slot].ih_arg); \ 361 } \ 362 } while (0) 363 364static void 365dec_3min_intr(status, cause, pc, ipending) 366 unsigned status; 367 unsigned cause; 368 unsigned pc; 369 unsigned ipending; 370{ 371 static int user_warned = 0; 372 static int intr_depth = 0; 373 u_int32_t old_mask; 374 375 intr_depth++; 376 old_mask = *(u_int32_t *)(ioasic_base + IOASIC_IMSK); 377 378 if (ipending & MIPS_INT_MASK_4) 379 prom_haltbutton(); 380 381 if (ipending & MIPS_INT_MASK_3) { 382 /* NB: status & MIPS_INT_MASK3 must also be set */ 383 /* masked interrupts are still observable */ 384 u_int32_t intr, imsk, can_serve, turnoff; 385 386 turnoff = 0; 387 intr = *(u_int32_t *)(ioasic_base + IOASIC_INTR); 388 imsk = *(u_int32_t *)(ioasic_base + IOASIC_IMSK); 389 can_serve = intr & imsk; 390 391 if (intr & IOASIC_INTR_SCSI_PTR_LOAD) { 392 turnoff |= IOASIC_INTR_SCSI_PTR_LOAD; 393#ifdef notdef 394 asc_dma_intr(); 395#endif 396 } 397 398 if (intr & (IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E)) 399 turnoff |= IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E; 400 401 if (intr & IOASIC_INTR_LANCE_READ_E) 402 turnoff |= IOASIC_INTR_LANCE_READ_E; 403 404 if (turnoff) 405 *(u_int32_t *)(ioasic_base + IOASIC_INTR) = ~turnoff; 406 407 if (intr & KMIN_INTR_TIMEOUT) { 408 kn02ba_errintr(); 409 pmax_memerr_evcnt.ev_count++; 410 } 411 412 if (intr & KMIN_INTR_CLOCK) { 413 struct clockframe cf; 414 415 __asm volatile("lbu $0,48(%0)" :: 416 "r"(ioasic_base + IOASIC_SLOT_8_START)); 417#ifdef MIPS3 418 if (CPUISMIPS3) { 419 latched_cycle_cnt = mips3_cp0_count_read(); 420 } 421#endif 422 cf.pc = pc; 423 cf.sr = status; 424 hardclock(&cf); 425 pmax_clock_evcnt.ev_count++; 426 } 427 428 /* If clock interrupts were enabled, re-enable them ASAP. */ 429 if (old_mask & KMIN_INTR_CLOCK) { 430 /* ioctl interrupt mask to splclock and higher */ 431 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) 432 = old_mask & 433 ~(KMIN_INTR_SCC_0|KMIN_INTR_SCC_1 | 434 IOASIC_INTR_LANCE|IOASIC_INTR_SCSI); 435 kn02ba_wbflush(); 436 _splset(MIPS_SR_INT_IE | (status & MIPS_INT_MASK_3)); 437 } 438 439 if (intr_depth > 1) 440 goto done; 441 442 CHECKINTR(SYS_DEV_SCC0, IOASIC_INTR_SCC_0); 443 CHECKINTR(SYS_DEV_SCC1, IOASIC_INTR_SCC_1); 444 445#ifdef notyet /* untested */ 446 /* If tty interrupts were enabled, re-enable them ASAP. */ 447 if ((old_mask & (KMIN_INTR_SCC_1|KMIN_INTR_SCC_0)) == 448 (KMIN_INTR_SCC_1|KMIN_INTR_SCC_0)) { 449 *imaskp = old_mask & 450 ~(KMIN_INTR_SCC_0|KMIN_INTR_SCC_1 | 451 IOASIC_INTR_LANCE|IOASIC_INTR_SCSI); 452 kn02ba_wbflush(); 453 } 454 455 /* XXX until we know about SPLs of TC options. */ 456 if (intr_depth > 1) 457 goto done; 458#endif 459 CHECKINTR(SYS_DEV_LANCE, IOASIC_INTR_LANCE); 460 CHECKINTR(SYS_DEV_SCSI, IOASIC_INTR_SCSI); 461 462 if (user_warned && ((intr & KMIN_INTR_PSWARN) == 0)) { 463 printf("%s\n", "Power supply ok now."); 464 user_warned = 0; 465 } 466 if ((intr & KMIN_INTR_PSWARN) && (user_warned < 3)) { 467 user_warned++; 468 printf("%s\n", "Power supply overheating"); 469 } 470 } 471 if ((ipending & MIPS_INT_MASK_0) && intrtab[SYS_DEV_OPT0].ih_func) { 472 (*intrtab[SYS_DEV_OPT0].ih_func)(intrtab[SYS_DEV_OPT0].ih_arg); 473 intrtab[SYS_DEV_OPT0].ih_count.ev_count++; 474 } 475 476 if ((ipending & MIPS_INT_MASK_1) && intrtab[SYS_DEV_OPT1].ih_func) { 477 (*intrtab[SYS_DEV_OPT1].ih_func)(intrtab[SYS_DEV_OPT1].ih_arg); 478 intrtab[SYS_DEV_OPT1].ih_count.ev_count++; 479 } 480 if ((ipending & MIPS_INT_MASK_2) && intrtab[SYS_DEV_OPT2].ih_func) { 481 (*intrtab[SYS_DEV_OPT2].ih_func)(intrtab[SYS_DEV_OPT2].ih_arg); 482 intrtab[SYS_DEV_OPT2].ih_count.ev_count++; 483 } 484 485done: 486 /* restore entry state */ 487 splhigh(); 488 intr_depth--; 489 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = old_mask; 490 491 _splset(MIPS_SR_INT_IE | (status & ~cause & MIPS_HARD_INT_MASK)); 492} 493 494 495 496/* 497 ************************************************************************ 498 * Extra functions 499 ************************************************************************ 500 */ 501 502static void 503kn02ba_wbflush() 504{ 505 /* read twice IOASIC_IMSK */ 506 __asm volatile("lw $0,%0; lw $0,%0" :: 507 "i"(MIPS_PHYS_TO_KSEG1(KMIN_REG_IMSK))); 508} 509 510static unsigned 511kn02ba_clkread() 512{ 513#ifdef MIPS3 514 if (CPUISMIPS3) { 515 u_int32_t mips3_cycles; 516 517 mips3_cycles = mips3_cp0_count_read() - latched_cycle_cnt; 518 /* XXX divides take 78 cycles: approximate with * 41/2048 */ 519 return((mips3_cycles >> 6) + (mips3_cycles >> 8) + 520 (mips3_cycles >> 11)); 521 } 522#endif 523 return 0; 524} 525