dec_3min.c revision 1.61
1/* $NetBSD: dec_3min.c,v 1.61 2009/03/14 14:46:04 dsl Exp $ */ 2 3/* 4 * Copyright (c) 1998 Jonathan Stone. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Jonathan Stone for 17 * the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Copyright (c) 1992, 1993 35 * The Regents of the University of California. All rights reserved. 36 * 37 * This code is derived from software contributed to Berkeley by 38 * the Systems Programming Group of the University of Utah Computer 39 * Science Department, The Mach Operating System project at 40 * Carnegie-Mellon University and Ralph Campbell. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. Neither the name of the University nor the names of its contributors 51 * may be used to endorse or promote products derived from this software 52 * without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 55 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 56 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 57 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 58 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 59 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 60 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 61 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 62 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 63 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 64 * SUCH DAMAGE. 65 * 66 * @(#)machdep.c 8.3 (Berkeley) 1/12/94 67 */ 68/* 69 * Copyright (c) 1988 University of Utah. 70 * 71 * This code is derived from software contributed to Berkeley by 72 * the Systems Programming Group of the University of Utah Computer 73 * Science Department, The Mach Operating System project at 74 * Carnegie-Mellon University and Ralph Campbell. 75 * 76 * Redistribution and use in source and binary forms, with or without 77 * modification, are permitted provided that the following conditions 78 * are met: 79 * 1. Redistributions of source code must retain the above copyright 80 * notice, this list of conditions and the following disclaimer. 81 * 2. Redistributions in binary form must reproduce the above copyright 82 * notice, this list of conditions and the following disclaimer in the 83 * documentation and/or other materials provided with the distribution. 84 * 3. All advertising materials mentioning features or use of this software 85 * must display the following acknowledgement: 86 * This product includes software developed by the University of 87 * California, Berkeley and its contributors. 88 * 4. Neither the name of the University nor the names of its contributors 89 * may be used to endorse or promote products derived from this software 90 * without specific prior written permission. 91 * 92 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 93 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 94 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 95 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 96 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 97 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 98 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 99 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 100 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 101 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 102 * SUCH DAMAGE. 103 * 104 * @(#)machdep.c 8.3 (Berkeley) 1/12/94 105 */ 106 107#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 108 109__KERNEL_RCSID(0, "$NetBSD: dec_3min.c,v 1.61 2009/03/14 14:46:04 dsl Exp $"); 110 111#include <sys/param.h> 112#include <sys/systm.h> 113#include <sys/device.h> 114#include <sys/timetc.h> 115 116#include <machine/cpu.h> 117#include <machine/intr.h> 118#include <machine/sysconf.h> 119 120#include <mips/mips/mips_mcclock.h> /* mcclock CPUspeed estimation */ 121 122/* all these to get ioasic_base */ 123#include <dev/tc/tcvar.h> /* tc type definitions for.. */ 124#include <dev/tc/ioasicreg.h> /* ioasic interrrupt masks */ 125#include <dev/tc/ioasicvar.h> /* ioasic_base */ 126 127#include <pmax/pmax/machdep.h> 128#include <pmax/pmax/kmin.h> /* 3min baseboard addresses */ 129#include <pmax/pmax/memc.h> /* 3min/maxine memory errors */ 130 131#include <pmax/pmax/cons.h> 132#include <dev/ic/z8530sc.h> 133#include <dev/tc/zs_ioasicvar.h> 134#include "wsdisplay.h" 135 136void dec_3min_init(void); /* XXX */ 137static void dec_3min_bus_reset(void); 138static void dec_3min_cons_init(void); 139static void dec_3min_intr(unsigned, unsigned, unsigned, unsigned); 140static void dec_3min_intr_establish(struct device *, void *, 141 int, int (*)(void *), void *); 142 143static void kn02ba_wbflush(void); 144 145static void dec_3min_tc_init(void); 146 147/* 148 * Local declarations. 149 */ 150static u_int32_t kmin_tc3_imask; 151 152static const int dec_3min_ipl2spl_table[] = { 153 [IPL_NONE] = 0, 154 [IPL_SOFTCLOCK] = _SPL_SOFTCLOCK, 155 [IPL_SOFTNET] = _SPL_SOFTNET, 156 /* 157 * Since all the motherboard interrupts come through the 158 * IOASIC, it has to be turned off for all the spls and 159 * since we don't know what kinds of devices are in the 160 * TURBOchannel option slots, just splhigh(). 161 */ 162 [IPL_VM] = MIPS_SPL_0_1_2_3, 163 [IPL_SCHED] = MIPS_SPL_0_1_2_3, 164 [IPL_HIGH] = MIPS_SPL_0_1_2_3, 165}; 166 167void 168dec_3min_init() 169{ 170 platform.iobus = "tcbus"; 171 platform.bus_reset = dec_3min_bus_reset; 172 platform.cons_init = dec_3min_cons_init; 173 platform.iointr = dec_3min_intr; 174 platform.intr_establish = dec_3min_intr_establish; 175 platform.memsize = memsize_bitmap; 176 platform.tc_init = dec_3min_tc_init; 177 178 /* clear any memory errors */ 179 *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0; 180 kn02ba_wbflush(); 181 182 ioasic_base = MIPS_PHYS_TO_KSEG1(KMIN_SYS_ASIC); 183 184 ipl2spl_table = dec_3min_ipl2spl_table; 185 186 /* enable posting of MIPS_INT_MASK_3 to CAUSE register */ 187 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = KMIN_INTR_CLOCK; 188 /* calibrate cpu_mhz value */ 189 mc_cpuspeed(ioasic_base+IOASIC_SLOT_8_START, MIPS_INT_MASK_3); 190 191 *(u_int32_t *)(ioasic_base + IOASIC_LANCE_DECODE) = 0x3; 192 *(u_int32_t *)(ioasic_base + IOASIC_SCSI_DECODE) = 0xe; 193#if 0 194 *(u_int32_t *)(ioasic_base + IOASIC_SCC0_DECODE) = (0x10|4); 195 *(u_int32_t *)(ioasic_base + IOASIC_SCC1_DECODE) = (0x10|6); 196 *(u_int32_t *)(ioasic_base + IOASIC_CSR) = 0x00000f00; 197#endif 198 199 /* sanitize interrupt mask */ 200 kmin_tc3_imask = (KMIN_INTR_CLOCK|KMIN_INTR_PSWARN|KMIN_INTR_TIMEOUT); 201 *(u_int32_t *)(ioasic_base + IOASIC_INTR) = 0; 202 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = kmin_tc3_imask; 203 204 /* 205 * The kmin memory hardware seems to wrap memory addresses 206 * with 4Mbyte SIMMs, which causes the physmem computation 207 * to lose. Find out how big the SIMMS are and set 208 * max_ physmem accordingly. 209 * XXX Do MAXINEs lose the same way? 210 */ 211 physmem_boardmax = KMIN_PHYS_MEMORY_END + 1; 212 if ((KMIN_MSR_SIZE_16Mb & *(int *)MIPS_PHYS_TO_KSEG1(KMIN_REG_MSR)) 213 == 0) 214 physmem_boardmax = physmem_boardmax >> 2; 215 physmem_boardmax = MIPS_PHYS_TO_KSEG1(physmem_boardmax); 216 217 sprintf(cpu_model, "DECstation 5000/1%d (3MIN)", cpu_mhz); 218} 219 220/* 221 * Initialize the memory system and I/O buses. 222 */ 223static void 224dec_3min_bus_reset() 225{ 226 227 /* 228 * Reset interrupts, clear any errors from newconf probes 229 */ 230 231 *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0; 232 kn02ba_wbflush(); 233 234 *(u_int32_t *)(ioasic_base + IOASIC_INTR) = 0; 235 kn02ba_wbflush(); 236} 237 238static void 239dec_3min_cons_init() 240{ 241 int kbd, crt, screen; 242 243 kbd = crt = screen = 0; 244 prom_findcons(&kbd, &crt, &screen); 245 246 if (screen > 0) { 247#if NWSDISPLAY > 0 248 if (tcfb_cnattach(crt) > 0) { 249 zs_ioasic_lk201_cnattach(ioasic_base, 0x180000, 0); 250 return; 251 } 252#endif 253 printf("No framebuffer device configured for slot %d: ", crt); 254 printf("using serial console\n"); 255 } 256 /* 257 * Delay to allow PROM putchars to complete. 258 * FIFO depth * character time, 259 * character time = (1000000 / (defaultrate / 10)) 260 */ 261 DELAY(160000000 / 9600); /* XXX */ 262 263 zs_ioasic_cnattach(ioasic_base, 0x180000, 1); 264} 265 266static void 267dec_3min_intr_establish(dev, cookie, level, handler, arg) 268 struct device *dev; 269 void *cookie; 270 int level; 271 int (*handler)(void *); 272 void *arg; 273{ 274 unsigned mask; 275 276 switch ((int)cookie) { 277 /* slots 0-2 don't interrupt through the IOASIC. */ 278 case SYS_DEV_OPT0: 279 mask = MIPS_INT_MASK_0; 280 break; 281 case SYS_DEV_OPT1: 282 mask = MIPS_INT_MASK_1; 283 break; 284 case SYS_DEV_OPT2: 285 mask = MIPS_INT_MASK_2; 286 break; 287 288 case SYS_DEV_SCSI: 289 mask = (IOASIC_INTR_SCSI | IOASIC_INTR_SCSI_PTR_LOAD | 290 IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E); 291 break; 292 case SYS_DEV_LANCE: 293 mask = KMIN_INTR_LANCE; 294 break; 295 case SYS_DEV_SCC0: 296 mask = KMIN_INTR_SCC_0; 297 break; 298 case SYS_DEV_SCC1: 299 mask = KMIN_INTR_SCC_1; 300 break; 301 default: 302#ifdef DIAGNOSTIC 303 printf("warning: enabling unknown intr %x\n", (int)cookie); 304#endif 305 return; 306 } 307 308#if defined(DEBUG) 309 printf("3MIN: imask %x, enabling slot %d, dev %p handler %p\n", 310 kmin_tc3_imask, (int)cookie, dev, handler); 311#endif 312 313 /* 314 * Enable the interrupt handler, and if it's an IOASIC 315 * slot, set the IOASIC interrupt mask. 316 * Otherwise, set the appropriate spl level in the R3000 317 * register. 318 * Be careful to set handlers before enabling, and disable 319 * interrupts before clearing handlers. 320 */ 321 322 /* Set the interrupt handler and argument ... */ 323 intrtab[(int)cookie].ih_func = handler; 324 intrtab[(int)cookie].ih_arg = arg; 325 /* ... and set the relevant mask */ 326 switch ((int)cookie) { 327 case SYS_DEV_OPT0: 328 case SYS_DEV_OPT1: 329 case SYS_DEV_OPT2: 330 /* it's an option slot */ 331 { 332 int s = splhigh(); 333 s |= mask; 334 splx(s); 335 } 336 break; 337 default: 338 /* it's a baseboard device going via the IOASIC */ 339 kmin_tc3_imask |= mask; 340 break; 341 } 342 343 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = kmin_tc3_imask; 344 kn02ba_wbflush(); 345} 346 347 348#define CHECKINTR(slot, bits) \ 349 do { \ 350 if (can_serve & (bits)) { \ 351 intrtab[slot].ih_count.ev_count++; \ 352 (*intrtab[slot].ih_func)(intrtab[slot].ih_arg); \ 353 } \ 354 } while (0) 355 356static void 357dec_3min_intr(status, cause, pc, ipending) 358 unsigned status; 359 unsigned cause; 360 unsigned pc; 361 unsigned ipending; 362{ 363 static int user_warned = 0; 364 static int intr_depth = 0; 365 u_int32_t old_mask; 366 367 intr_depth++; 368 old_mask = *(u_int32_t *)(ioasic_base + IOASIC_IMSK); 369 370 if (ipending & MIPS_INT_MASK_4) 371 prom_haltbutton(); 372 373 if (ipending & MIPS_INT_MASK_3) { 374 /* NB: status & MIPS_INT_MASK3 must also be set */ 375 /* masked interrupts are still observable */ 376 u_int32_t intr, imsk, can_serve, turnoff; 377 378 turnoff = 0; 379 intr = *(u_int32_t *)(ioasic_base + IOASIC_INTR); 380 imsk = *(u_int32_t *)(ioasic_base + IOASIC_IMSK); 381 can_serve = intr & imsk; 382 383 if (intr & IOASIC_INTR_SCSI_PTR_LOAD) { 384 turnoff |= IOASIC_INTR_SCSI_PTR_LOAD; 385#ifdef notdef 386 asc_dma_intr(); 387#endif 388 } 389 390 if (intr & (IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E)) 391 turnoff |= IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E; 392 393 if (intr & IOASIC_INTR_LANCE_READ_E) 394 turnoff |= IOASIC_INTR_LANCE_READ_E; 395 396 if (turnoff) 397 *(u_int32_t *)(ioasic_base + IOASIC_INTR) = ~turnoff; 398 399 if (intr & KMIN_INTR_TIMEOUT) { 400 kn02ba_errintr(); 401 pmax_memerr_evcnt.ev_count++; 402 } 403 404 if (intr & KMIN_INTR_CLOCK) { 405 struct clockframe cf; 406 407 __asm volatile("lbu $0,48(%0)" :: 408 "r"(ioasic_base + IOASIC_SLOT_8_START)); 409 410 cf.pc = pc; 411 cf.sr = status; 412 hardclock(&cf); 413 pmax_clock_evcnt.ev_count++; 414 } 415 416 /* If clock interrupts were enabled, re-enable them ASAP. */ 417 if (old_mask & KMIN_INTR_CLOCK) { 418 /* ioctl interrupt mask to splclock and higher */ 419 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) 420 = old_mask & 421 ~(KMIN_INTR_SCC_0|KMIN_INTR_SCC_1 | 422 IOASIC_INTR_LANCE|IOASIC_INTR_SCSI); 423 kn02ba_wbflush(); 424 _splset(MIPS_SR_INT_IE | (status & MIPS_INT_MASK_3)); 425 } 426 427 if (intr_depth > 1) 428 goto done; 429 430 CHECKINTR(SYS_DEV_SCC0, IOASIC_INTR_SCC_0); 431 CHECKINTR(SYS_DEV_SCC1, IOASIC_INTR_SCC_1); 432 433#ifdef notyet /* untested */ 434 /* If tty interrupts were enabled, re-enable them ASAP. */ 435 if ((old_mask & (KMIN_INTR_SCC_1|KMIN_INTR_SCC_0)) == 436 (KMIN_INTR_SCC_1|KMIN_INTR_SCC_0)) { 437 *imaskp = old_mask & 438 ~(KMIN_INTR_SCC_0|KMIN_INTR_SCC_1 | 439 IOASIC_INTR_LANCE|IOASIC_INTR_SCSI); 440 kn02ba_wbflush(); 441 } 442 443 /* XXX until we know about SPLs of TC options. */ 444 if (intr_depth > 1) 445 goto done; 446#endif 447 CHECKINTR(SYS_DEV_LANCE, IOASIC_INTR_LANCE); 448 CHECKINTR(SYS_DEV_SCSI, IOASIC_INTR_SCSI); 449 450 if (user_warned && ((intr & KMIN_INTR_PSWARN) == 0)) { 451 printf("%s\n", "Power supply ok now."); 452 user_warned = 0; 453 } 454 if ((intr & KMIN_INTR_PSWARN) && (user_warned < 3)) { 455 user_warned++; 456 printf("%s\n", "Power supply overheating"); 457 } 458 } 459 if ((ipending & MIPS_INT_MASK_0) && intrtab[SYS_DEV_OPT0].ih_func) { 460 (*intrtab[SYS_DEV_OPT0].ih_func)(intrtab[SYS_DEV_OPT0].ih_arg); 461 intrtab[SYS_DEV_OPT0].ih_count.ev_count++; 462 } 463 464 if ((ipending & MIPS_INT_MASK_1) && intrtab[SYS_DEV_OPT1].ih_func) { 465 (*intrtab[SYS_DEV_OPT1].ih_func)(intrtab[SYS_DEV_OPT1].ih_arg); 466 intrtab[SYS_DEV_OPT1].ih_count.ev_count++; 467 } 468 if ((ipending & MIPS_INT_MASK_2) && intrtab[SYS_DEV_OPT2].ih_func) { 469 (*intrtab[SYS_DEV_OPT2].ih_func)(intrtab[SYS_DEV_OPT2].ih_arg); 470 intrtab[SYS_DEV_OPT2].ih_count.ev_count++; 471 } 472 473done: 474 /* restore entry state */ 475 splhigh(); 476 intr_depth--; 477 *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = old_mask; 478 479 _splset(MIPS_SR_INT_IE | (status & ~cause & MIPS_HARD_INT_MASK)); 480} 481 482 483 484/* 485 ************************************************************************ 486 * Extra functions 487 ************************************************************************ 488 */ 489 490static void 491kn02ba_wbflush() 492{ 493 /* read twice IOASIC_IMSK */ 494 __asm volatile("lw $0,%0; lw $0,%0" :: 495 "i"(MIPS_PHYS_TO_KSEG1(KMIN_REG_IMSK))); 496} 497 498/* 499 * Support for using the MIPS 3 clock as a timecounter. 500 */ 501 502void 503dec_3min_tc_init(void) 504{ 505#if defined(MIPS3) 506 static struct timecounter tc = { 507 .tc_get_timecount = (timecounter_get_t *)mips3_cp0_count_read, 508 .tc_counter_mask = ~0u, 509 .tc_name = "mips3_cp0_counter", 510 .tc_quality = 100, 511 }; 512 513 if (MIPS_HAS_CLOCK) { 514 tc.tc_frequency = cpu_mhz * 1000000; 515 if (mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT) { 516 tc.tc_frequency /= 2; 517 } 518 519 tc_init(&tc); 520 } 521#endif 522} 523