dec_3min.c revision 1.67
1/* $NetBSD: dec_3min.c,v 1.67 2011/02/08 20:20:22 rmind Exp $ */ 2 3/* 4 * Copyright (c) 1998 Jonathan Stone. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Jonathan Stone for 17 * the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Copyright (c) 1988 University of Utah. 35 * Copyright (c) 1992, 1993 36 * The Regents of the University of California. All rights reserved. 37 * 38 * This code is derived from software contributed to Berkeley by 39 * the Systems Programming Group of the University of Utah Computer 40 * Science Department, The Mach Operating System project at 41 * Carnegie-Mellon University and Ralph Campbell. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of the University nor the names of its contributors 52 * may be used to endorse or promote products derived from this software 53 * without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * @(#)machdep.c 8.3 (Berkeley) 1/12/94 68 */ 69 70#include <sys/cdefs.h> 71__KERNEL_RCSID(0, "$NetBSD: dec_3min.c,v 1.67 2011/02/08 20:20:22 rmind Exp $"); 72 73#include <sys/param.h> 74#include <sys/systm.h> 75#include <sys/device.h> 76#include <sys/timetc.h> 77 78#include <machine/cpu.h> 79#include <machine/intr.h> 80#include <machine/sysconf.h> 81 82#include <mips/mips/mips_mcclock.h> /* mcclock CPUspeed estimation */ 83 84/* all these to get ioasic_base */ 85#include <dev/tc/tcvar.h> /* tc type definitions for.. */ 86#include <dev/tc/ioasicreg.h> /* ioasic interrrupt masks */ 87#include <dev/tc/ioasicvar.h> /* ioasic_base */ 88 89#include <pmax/pmax/machdep.h> 90#include <pmax/pmax/kmin.h> /* 3min baseboard addresses */ 91#include <pmax/pmax/memc.h> /* 3min/maxine memory errors */ 92 93#include <pmax/pmax/cons.h> 94#include <dev/ic/z8530sc.h> 95#include <dev/tc/zs_ioasicvar.h> 96#include "wsdisplay.h" 97 98void dec_3min_init(void); /* XXX */ 99static void dec_3min_bus_reset(void); 100static void dec_3min_cons_init(void); 101static void dec_3min_intr(unsigned, unsigned, unsigned, unsigned); 102static void dec_3min_intr_establish(struct device *, void *, 103 int, int (*)(void *), void *); 104 105static void kn02ba_wbflush(void); 106 107static void dec_3min_tc_init(void); 108 109/* 110 * Local declarations. 111 */ 112static uint32_t kmin_tc3_imask; 113 114static const int dec_3min_ipl2spl_table[] = { 115 [IPL_NONE] = 0, 116 [IPL_SOFTCLOCK] = _SPL_SOFTCLOCK, 117 [IPL_SOFTNET] = _SPL_SOFTNET, 118 /* 119 * Since all the motherboard interrupts come through the 120 * IOASIC, it has to be turned off for all the spls and 121 * since we don't know what kinds of devices are in the 122 * TURBOchannel option slots, just splhigh(). 123 */ 124 [IPL_VM] = MIPS_SPL_0_1_2_3, 125 [IPL_SCHED] = MIPS_SPL_0_1_2_3, 126 [IPL_HIGH] = MIPS_SPL_0_1_2_3, 127}; 128 129void 130dec_3min_init(void) 131{ 132 133 platform.iobus = "tcbus"; 134 platform.bus_reset = dec_3min_bus_reset; 135 platform.cons_init = dec_3min_cons_init; 136 platform.iointr = dec_3min_intr; 137 platform.intr_establish = dec_3min_intr_establish; 138 platform.memsize = memsize_bitmap; 139 platform.tc_init = dec_3min_tc_init; 140 141 /* clear any memory errors */ 142 *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0; 143 kn02ba_wbflush(); 144 145 ioasic_base = MIPS_PHYS_TO_KSEG1(KMIN_SYS_ASIC); 146 147 ipl2spl_table = dec_3min_ipl2spl_table; 148 149 /* enable posting of MIPS_INT_MASK_3 to CAUSE register */ 150 *(volatile uint32_t *)(ioasic_base + IOASIC_IMSK) = KMIN_INTR_CLOCK; 151 /* calibrate cpu_mhz value */ 152 mc_cpuspeed(ioasic_base+IOASIC_SLOT_8_START, MIPS_INT_MASK_3); 153 154 *(volatile uint32_t *)(ioasic_base + IOASIC_LANCE_DECODE) = 0x3; 155 *(volatile uint32_t *)(ioasic_base + IOASIC_SCSI_DECODE) = 0xe; 156#if 0 157 *(volatile uint32_t *)(ioasic_base + IOASIC_SCC0_DECODE) = (0x10|4); 158 *(volatile uint32_t *)(ioasic_base + IOASIC_SCC1_DECODE) = (0x10|6); 159 *(volatile uint32_t *)(ioasic_base + IOASIC_CSR) = 0x00000f00; 160#endif 161 162 /* sanitize interrupt mask */ 163 kmin_tc3_imask = (KMIN_INTR_CLOCK|KMIN_INTR_PSWARN|KMIN_INTR_TIMEOUT); 164 *(volatile uint32_t *)(ioasic_base + IOASIC_INTR) = 0; 165 *(volatile uint32_t *)(ioasic_base + IOASIC_IMSK) = kmin_tc3_imask; 166 167 /* 168 * The kmin memory hardware seems to wrap memory addresses 169 * with 4Mbyte SIMMs, which causes the physmem computation 170 * to lose. Find out how big the SIMMS are and set 171 * max_ physmem accordingly. 172 * XXX Do MAXINEs lose the same way? 173 */ 174 physmem_boardmax = KMIN_PHYS_MEMORY_END + 1; 175 if ((KMIN_MSR_SIZE_16Mb & *(int *)MIPS_PHYS_TO_KSEG1(KMIN_REG_MSR)) 176 == 0) 177 physmem_boardmax = physmem_boardmax >> 2; 178 physmem_boardmax = MIPS_PHYS_TO_KSEG1(physmem_boardmax); 179 180 sprintf(cpu_model, "DECstation 5000/1%d (3MIN)", cpu_mhz); 181} 182 183/* 184 * Initialize the memory system and I/O buses. 185 */ 186static void 187dec_3min_bus_reset(void) 188{ 189 190 /* 191 * Reset interrupts, clear any errors from newconf probes 192 */ 193 194 *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0; 195 kn02ba_wbflush(); 196 197 *(volatile uint32_t *)(ioasic_base + IOASIC_INTR) = 0; 198 kn02ba_wbflush(); 199} 200 201static void 202dec_3min_cons_init(void) 203{ 204 int kbd, crt, screen; 205 206 kbd = crt = screen = 0; 207 prom_findcons(&kbd, &crt, &screen); 208 209 if (screen > 0) { 210#if NWSDISPLAY > 0 211 if (tcfb_cnattach(crt) > 0) { 212 zs_ioasic_lk201_cnattach(ioasic_base, 0x180000, 0); 213 return; 214 } 215#endif 216 printf("No framebuffer device configured for slot %d: ", crt); 217 printf("using serial console\n"); 218 } 219 /* 220 * Delay to allow PROM putchars to complete. 221 * FIFO depth * character time, 222 * character time = (1000000 / (defaultrate / 10)) 223 */ 224 DELAY(160000000 / 9600); /* XXX */ 225 226 zs_ioasic_cnattach(ioasic_base, 0x180000, 1); 227} 228 229static void 230dec_3min_intr_establish(struct device *dev, void *cookie, int level, 231 int (*handler)(void *), void *arg) 232{ 233 uint32_t mask; 234 235 switch ((uintptr_t)cookie) { 236 /* slots 0-2 don't interrupt through the IOASIC. */ 237 case SYS_DEV_OPT0: 238 mask = MIPS_INT_MASK_0; 239 break; 240 case SYS_DEV_OPT1: 241 mask = MIPS_INT_MASK_1; 242 break; 243 case SYS_DEV_OPT2: 244 mask = MIPS_INT_MASK_2; 245 break; 246 247 case SYS_DEV_SCSI: 248 mask = (IOASIC_INTR_SCSI | IOASIC_INTR_SCSI_PTR_LOAD | 249 IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E); 250 break; 251 case SYS_DEV_LANCE: 252 mask = KMIN_INTR_LANCE; 253 break; 254 case SYS_DEV_SCC0: 255 mask = KMIN_INTR_SCC_0; 256 break; 257 case SYS_DEV_SCC1: 258 mask = KMIN_INTR_SCC_1; 259 break; 260 default: 261#ifdef DIAGNOSTIC 262 printf("warning: enabling unknown intr %p\n", cookie); 263#endif 264 return; 265 } 266 267#if defined(DEBUG) 268 printf("3MIN: imask %x, enabling slot %p, dev %p handler %p\n", 269 kmin_tc3_imask, cookie, dev, handler); 270#endif 271 272 /* 273 * Enable the interrupt handler, and if it's an IOASIC 274 * slot, set the IOASIC interrupt mask. 275 * Otherwise, set the appropriate spl level in the R3000 276 * register. 277 * Be careful to set handlers before enabling, and disable 278 * interrupts before clearing handlers. 279 */ 280 281 /* Set the interrupt handler and argument ... */ 282 intrtab[(uintptr_t)cookie].ih_func = handler; 283 intrtab[(uintptr_t)cookie].ih_arg = arg; 284 /* ... and set the relevant mask */ 285 switch ((uintptr_t)cookie) { 286 case SYS_DEV_OPT0: 287 case SYS_DEV_OPT1: 288 case SYS_DEV_OPT2: 289 /* it's an option slot */ 290 { 291 int s = splhigh(); 292 s |= mask; 293 splx(s); 294 } 295 break; 296 default: 297 /* it's a baseboard device going via the IOASIC */ 298 kmin_tc3_imask |= mask; 299 break; 300 } 301 302 *(volatile uint32_t *)(ioasic_base + IOASIC_IMSK) = kmin_tc3_imask; 303 kn02ba_wbflush(); 304} 305 306 307#define CHECKINTR(slot, bits) \ 308 do { \ 309 if (can_serve & (bits)) { \ 310 intrtab[slot].ih_count.ev_count++; \ 311 (*intrtab[slot].ih_func)(intrtab[slot].ih_arg); \ 312 } \ 313 } while (/*CONSTCOND*/0) 314 315static void 316dec_3min_intr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending) 317{ 318 static int user_warned = 0; 319 static int intr_depth = 0; 320 uint32_t old_mask; 321 322 intr_depth++; 323 old_mask = *(volatile uint32_t *)(ioasic_base + IOASIC_IMSK); 324 325 if (ipending & MIPS_INT_MASK_4) 326 prom_haltbutton(); 327 328 if (ipending & MIPS_INT_MASK_3) { 329 /* NB: status & MIPS_INT_MASK3 must also be set */ 330 /* masked interrupts are still observable */ 331 uint32_t intr, imsk, can_serve, turnoff; 332 333 turnoff = 0; 334 intr = *(volatile uint32_t *)(ioasic_base + IOASIC_INTR); 335 imsk = *(volatile uint32_t *)(ioasic_base + IOASIC_IMSK); 336 can_serve = intr & imsk; 337 338 if (intr & IOASIC_INTR_SCSI_PTR_LOAD) { 339 turnoff |= IOASIC_INTR_SCSI_PTR_LOAD; 340#ifdef notdef 341 asc_dma_intr(); 342#endif 343 } 344 345 if (intr & (IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E)) 346 turnoff |= 347 IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E; 348 349 if (intr & IOASIC_INTR_LANCE_READ_E) 350 turnoff |= IOASIC_INTR_LANCE_READ_E; 351 352 if (turnoff) 353 *(volatile uint32_t *)(ioasic_base + IOASIC_INTR) = 354 ~turnoff; 355 356 if (intr & KMIN_INTR_TIMEOUT) { 357 kn02ba_errintr(); 358 pmax_memerr_evcnt.ev_count++; 359 } 360 361 if (intr & KMIN_INTR_CLOCK) { 362 struct clockframe cf; 363 364 __asm volatile("lbu $0,48(%0)" :: 365 "r"(ioasic_base + IOASIC_SLOT_8_START)); 366 367 cf.pc = pc; 368 cf.sr = status; 369 hardclock(&cf); 370 pmax_clock_evcnt.ev_count++; 371 } 372 373 /* If clock interrupts were enabled, re-enable them ASAP. */ 374 if (old_mask & KMIN_INTR_CLOCK) { 375 /* ioctl interrupt mask to splclock and higher */ 376 *(volatile uint32_t *)(ioasic_base + IOASIC_IMSK) 377 = old_mask & 378 ~(KMIN_INTR_SCC_0|KMIN_INTR_SCC_1 | 379 IOASIC_INTR_LANCE|IOASIC_INTR_SCSI); 380 kn02ba_wbflush(); 381 _splset(MIPS_SR_INT_IE | (status & MIPS_INT_MASK_3)); 382 } 383 384 if (intr_depth > 1) 385 goto done; 386 387 CHECKINTR(SYS_DEV_SCC0, IOASIC_INTR_SCC_0); 388 CHECKINTR(SYS_DEV_SCC1, IOASIC_INTR_SCC_1); 389 390#ifdef notyet /* untested */ 391 /* If tty interrupts were enabled, re-enable them ASAP. */ 392 if ((old_mask & (KMIN_INTR_SCC_1|KMIN_INTR_SCC_0)) == 393 (KMIN_INTR_SCC_1|KMIN_INTR_SCC_0)) { 394 *imaskp = old_mask & 395 ~(KMIN_INTR_SCC_0|KMIN_INTR_SCC_1 | 396 IOASIC_INTR_LANCE|IOASIC_INTR_SCSI); 397 kn02ba_wbflush(); 398 } 399 400 /* XXX until we know about SPLs of TC options. */ 401 if (intr_depth > 1) 402 goto done; 403#endif 404 CHECKINTR(SYS_DEV_LANCE, IOASIC_INTR_LANCE); 405 CHECKINTR(SYS_DEV_SCSI, IOASIC_INTR_SCSI); 406 407 if (user_warned && ((intr & KMIN_INTR_PSWARN) == 0)) { 408 printf("%s\n", "Power supply ok now."); 409 user_warned = 0; 410 } 411 if ((intr & KMIN_INTR_PSWARN) && (user_warned < 3)) { 412 user_warned++; 413 printf("%s\n", "Power supply overheating"); 414 } 415 } 416 if ((ipending & MIPS_INT_MASK_0) && intrtab[SYS_DEV_OPT0].ih_func) { 417 (*intrtab[SYS_DEV_OPT0].ih_func)(intrtab[SYS_DEV_OPT0].ih_arg); 418 intrtab[SYS_DEV_OPT0].ih_count.ev_count++; 419 } 420 421 if ((ipending & MIPS_INT_MASK_1) && intrtab[SYS_DEV_OPT1].ih_func) { 422 (*intrtab[SYS_DEV_OPT1].ih_func)(intrtab[SYS_DEV_OPT1].ih_arg); 423 intrtab[SYS_DEV_OPT1].ih_count.ev_count++; 424 } 425 if ((ipending & MIPS_INT_MASK_2) && intrtab[SYS_DEV_OPT2].ih_func) { 426 (*intrtab[SYS_DEV_OPT2].ih_func)(intrtab[SYS_DEV_OPT2].ih_arg); 427 intrtab[SYS_DEV_OPT2].ih_count.ev_count++; 428 } 429 430done: 431 /* restore entry state */ 432 splhigh(); 433 intr_depth--; 434 *(volatile uint32_t *)(ioasic_base + IOASIC_IMSK) = old_mask; 435 436 _splset(MIPS_SR_INT_IE | (status & ~cause & MIPS_HARD_INT_MASK)); 437} 438 439 440 441/* 442 ************************************************************************ 443 * Extra functions 444 ************************************************************************ 445 */ 446 447static void 448kn02ba_wbflush(void) 449{ 450 451 /* read twice IOASIC_IMSK */ 452 __asm volatile("lw $0,%0; lw $0,%0" :: 453 "i"(MIPS_PHYS_TO_KSEG1(KMIN_REG_IMSK))); 454} 455 456/* 457 * Support for using the MIPS 3 clock as a timecounter. 458 */ 459 460void 461dec_3min_tc_init(void) 462{ 463#if defined(MIPS3) 464 static struct timecounter tc = { 465 .tc_get_timecount = (timecounter_get_t *)mips3_cp0_count_read, 466 .tc_counter_mask = ~0u, 467 .tc_name = "mips3_cp0_counter", 468 .tc_quality = 100, 469 }; 470 471 if (MIPS_HAS_CLOCK) { 472 tc.tc_frequency = cpu_mhz * 1000000; 473 if (mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT) { 474 tc.tc_frequency /= 2; 475 } 476 477 tc_init(&tc); 478 } 479#endif 480} 481