dec_3min.c revision 1.9
1/* $NetBSD: dec_3min.c,v 1.9 1999/03/02 09:24:17 jonathan Exp $ */ 2 3/* 4 * Copyright (c) 1998 Jonathan Stone. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Jonathan Stone for 17 * the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Copyright (c) 1988 University of Utah. 35 * Copyright (c) 1992, 1993 36 * The Regents of the University of California. All rights reserved. 37 * 38 * This code is derived from software contributed to Berkeley by 39 * the Systems Programming Group of the University of Utah Computer 40 * Science Department, The Mach Operating System project at 41 * Carnegie-Mellon University and Ralph Campbell. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by the University of 54 * California, Berkeley and its contributors. 55 * 4. Neither the name of the University nor the names of its contributors 56 * may be used to endorse or promote products derived from this software 57 * without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 61 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 62 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 63 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 64 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 65 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69 * SUCH DAMAGE. 70 * 71 * @(#)machdep.c 8.3 (Berkeley) 1/12/94 72 */ 73 74#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 75 76__KERNEL_RCSID(0, "$NetBSD: dec_3min.c,v 1.9 1999/03/02 09:24:17 jonathan Exp $"); 77 78 79#include <sys/types.h> 80#include <sys/systm.h> 81 82#include <machine/cpu.h> 83#include <machine/intr.h> 84#include <machine/reg.h> 85#include <machine/psl.h> 86#include <machine/locore.h> /* wbflush() */ 87#include <machine/autoconf.h> /* intr_arg_t */ 88#include <machine/sysconf.h> 89 90#include <mips/mips_param.h> /* hokey spl()s */ 91#include <mips/mips/mips_mcclock.h> /* mcclock CPUspeed estimation */ 92 93/* all these to get ioasic_base */ 94#include <sys/device.h> /* struct cfdata for.. */ 95#include <dev/tc/tcvar.h> /* tc type definitions for.. */ 96#include <dev/tc/ioasicreg.h> /* ioasic interrrupt masks */ 97#include <dev/tc/ioasicvar.h> /* ioasic_base */ 98 99#include <pmax/pmax/clockreg.h> 100#include <pmax/pmax/turbochannel.h> 101#include <pmax/pmax/pmaxtype.h> 102 103#include <pmax/pmax/machdep.h> /* XXXjrs replace with vectors */ 104 105#include <pmax/pmax/kmin.h> /* 3min baseboard addresses */ 106#include <pmax/pmax/dec_kn02_subr.h> /* 3min/maxine memory errors */ 107 108 109/* 110 * forward declarations 111 */ 112void dec_3min_init __P((void)); 113void dec_3min_os_init __P((void)); 114void dec_3min_bus_reset __P((void)); 115void dec_3maxplus_device_register __P((struct device *, void *)); 116 117void dec_3min_enable_intr 118 __P ((u_int slotno, int (*handler) __P((intr_arg_t sc)), 119 intr_arg_t sc, int onoff)); 120int dec_3min_intr __P((u_int mask, u_int pc, 121 u_int statusReg, u_int causeReg)); 122 123void dec_3min_device_register __P((struct device *, void *)); 124void dec_3min_cons_init __P((void)); 125 126 127/* 128 * Local declarations. 129 */ 130void dec_3min_mcclock_cpuspeed __P((volatile struct chiptime *mcclock_addr, 131 int clockmask)); 132u_long kmin_tc3_imask; 133 134 135/* 136 * Fill in platform struct. 137 */ 138void 139dec_3min_init() 140{ 141 142 platform.iobus = "tcbus"; 143 144 platform.os_init = dec_3min_os_init; 145 platform.bus_reset = dec_3min_bus_reset; 146 platform.cons_init = dec_3min_cons_init; 147 platform.device_register = dec_3min_device_register; 148 149 dec_3min_os_init(); 150 151 sprintf(cpu_model, "DECstation 5000/1%d (3MIN)", cpu_mhz); 152} 153 154 155/* 156 * Initalize the memory system and I/O buses. 157 */ 158void 159dec_3min_bus_reset() 160{ 161 162 /* 163 * Reset interrupts, clear any errors from newconf probes 164 */ 165 166 *(volatile u_int *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0; 167 wbflush(); 168 169 *(volatile u_int *)IOASIC_REG_INTR(ioasic_base) = 0; 170 wbflush(); 171 172} 173 174 175void 176dec_3min_os_init() 177{ 178 ioasic_base = MIPS_PHYS_TO_KSEG1(KMIN_SYS_ASIC); 179 mips_hardware_intr = dec_3min_intr; 180 tc_enable_interrupt = dec_3min_enable_intr; 181 kmin_tc3_imask = (KMIN_INTR_CLOCK | KMIN_INTR_PSWARN | 182 KMIN_INTR_TIMEOUT); 183 184 /* 185 * All the baseboard interrupts come through the I/O ASIC 186 * (at INT_MASK_3), so it has to be turned off for all the spls. 187 * Since we don't know what kinds of devices are in the 188 * turbochannel option slots, just block them all. 189 */ 190 Mach_splbio = cpu_spl3; 191 Mach_splnet = cpu_spl3; 192 Mach_spltty = cpu_spl3; 193 Mach_splimp = cpu_spl3; 194 Mach_splclock = cpu_spl3; 195 Mach_splstatclock = cpu_spl3; 196 mcclock_addr = (volatile struct chiptime *) 197 MIPS_PHYS_TO_KSEG1(KMIN_SYS_CLOCK); 198 dec_3min_mcclock_cpuspeed(mcclock_addr, MIPS_INT_MASK_3); 199 200 /* 201 * Initialize interrupts. 202 */ 203 *(u_int *)IOASIC_REG_IMSK(ioasic_base) = KMIN_IM0; 204 *(u_int *)IOASIC_REG_INTR(ioasic_base) = 0; 205 206 /* clear any memory errors from probes */ 207 208 *(volatile u_int *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0; 209 wbflush(); 210 211 /* 212 * The kmin memory hardware seems to wrap memory addresses 213 * with 4Mbyte SIMMs, which causes the physmem computation 214 * to lose. Find out how big the SIMMS are and set 215 * max_ physmem accordingly. 216 * XXX Do MAXINEs lose the same way? 217 */ 218 physmem_boardmax = KMIN_PHYS_MEMORY_END + 1; 219 if ((*(int*)(MIPS_PHYS_TO_KSEG1(KMIN_REG_MSR)) & 220 KMIN_MSR_SIZE_16Mb) == 0) 221 physmem_boardmax = physmem_boardmax >> 2; 222 physmem_boardmax = MIPS_PHYS_TO_KSEG1(physmem_boardmax); 223} 224 225 226void 227dec_3min_cons_init() 228{ 229 /* notyet */ 230} 231 232 233void 234dec_3min_device_register(dev, aux) 235 struct device *dev; 236 void *aux; 237{ 238 panic("dec_3min_device_register unimplemented"); 239} 240 241 242void 243dec_3min_enable_intr(slotno, handler, sc, on) 244 register unsigned int slotno; 245 int (*handler) __P((void* softc)); 246 void *sc; 247 int on; 248{ 249 register unsigned mask; 250 251 switch (slotno) { 252 /* slots 0-2 don't interrupt through the IOASIC. */ 253 case 0: 254 mask = MIPS_INT_MASK_0; break; 255 case 1: 256 mask = MIPS_INT_MASK_1; break; 257 case 2: 258 mask = MIPS_INT_MASK_2; break; 259 260 case KMIN_SCSI_SLOT: 261 mask = (IOASIC_INTR_SCSI | IOASIC_INTR_SCSI_PTR_LOAD | 262 IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E); 263 break; 264 265 case KMIN_LANCE_SLOT: 266 mask = KMIN_INTR_LANCE; 267 break; 268 case KMIN_SCC0_SLOT: 269 mask = KMIN_INTR_SCC_0; 270 break; 271 case KMIN_SCC1_SLOT: 272 mask = KMIN_INTR_SCC_1; 273 break; 274 case KMIN_ASIC_SLOT: 275 mask = KMIN_INTR_ASIC; 276 break; 277 default: 278 return; 279 } 280 281#if defined(DEBUG) || defined(DIAGNOSTIC) 282 printf("3MIN: imask %lx, %sabling slot %d, sc %p handler %p\n", 283 kmin_tc3_imask, (on? "en" : "dis"), slotno, sc, handler); 284#endif 285 286 /* 287 * Enable the interrupt handler, and if it's an IOASIC 288 * slot, set the IOASIC interrupt mask. 289 * Otherwise, set the appropriate spl level in the R3000 290 * register. 291 * Be careful to set handlers before enabling, and disable 292 * interrupts before clearing handlers. 293 */ 294 295 if (on) { 296 /* Set the interrupt handler and argument ... */ 297 tc_slot_info[slotno].intr = handler; 298 tc_slot_info[slotno].sc = sc; 299 300 /* ... and set the relevant mask */ 301 if (slotno <= 2) { 302 /* it's an option slot */ 303 int s = splhigh(); 304 s |= mask; 305 splx(s); 306 } else { 307 /* it's a baseboard device going via the ASIC */ 308 kmin_tc3_imask |= mask; 309 } 310 } else { 311 /* Clear the relevant mask... */ 312 if (slotno <= 2) { 313 /* it's an option slot */ 314 int s = splhigh(); 315 printf("kmin_intr: cannot disable option slot %d\n", 316 slotno); 317 s &= ~mask; 318 splx(s); 319 } else { 320 /* it's a baseboard device going via the ASIC */ 321 kmin_tc3_imask &= ~mask; 322 } 323 /* ... and clear the handler */ 324 tc_slot_info[slotno].intr = 0; 325 tc_slot_info[slotno].sc = 0; 326 } 327} 328 329 330 331/* 332 * 3min hardware interrupts. (DECstation 5000/1xx) 333 */ 334int 335dec_3min_intr(mask, pc, statusReg, causeReg) 336 unsigned mask; 337 unsigned pc; 338 unsigned statusReg; 339 unsigned causeReg; 340{ 341 register u_int intr; 342 register volatile struct chiptime *c = 343 (volatile struct chiptime *) MIPS_PHYS_TO_KSEG1(KMIN_SYS_CLOCK); 344 volatile u_int *imaskp = 345 (volatile u_int *)MIPS_PHYS_TO_KSEG1(KMIN_REG_IMSK); 346 volatile u_int *intrp = 347 (volatile u_int *)MIPS_PHYS_TO_KSEG1(KMIN_REG_INTR); 348 unsigned int old_mask; 349 struct clockframe cf; 350 int temp; 351 static int user_warned = 0; 352 353 old_mask = *imaskp & kmin_tc3_imask; 354 *imaskp = kmin_tc3_imask | 355 (KMIN_IM0 & ~(KN03_INTR_TC_0|KN03_INTR_TC_1|KN03_INTR_TC_2)); 356 357 if (mask & MIPS_INT_MASK_4) 358 prom_haltbutton(); 359 360 if (mask & MIPS_INT_MASK_3) { 361 intr = *intrp; 362 363 /* masked interrupts are still observable */ 364 intr &= old_mask; 365 366 if (intr & IOASIC_INTR_SCSI_PTR_LOAD) { 367 *intrp &= ~IOASIC_INTR_SCSI_PTR_LOAD; 368#ifdef notdef 369 asc_dma_intr(); 370#endif 371 } 372 373 if (intr & (IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E)) 374 *intrp &= ~(IOASIC_INTR_SCSI_OVRUN | IOASIC_INTR_SCSI_READ_E); 375 376 if (intr & IOASIC_INTR_LANCE_READ_E) 377 *intrp &= ~IOASIC_INTR_LANCE_READ_E; 378 379 if (intr & KMIN_INTR_TIMEOUT) 380 kn02ba_errintr(); 381 382 if (intr & KMIN_INTR_CLOCK) { 383 extern u_int32_t mips3_cycle_count __P((void)); 384 385 temp = c->regc; /* XXX clear interrupt bits */ 386 cf.pc = pc; 387 cf.sr = statusReg; 388#ifdef MIPS3 389 if (CPUISMIPS3) { 390 latched_cycle_cnt = mips3_cycle_count(); 391 } 392#endif 393 hardclock(&cf); 394 intrcnt[HARDCLOCK]++; 395 } 396 397 if ((intr & KMIN_INTR_SCC_0) && 398 tc_slot_info[KMIN_SCC0_SLOT].intr) { 399 (*(tc_slot_info[KMIN_SCC0_SLOT].intr)) 400 (tc_slot_info[KMIN_SCC0_SLOT].sc); 401 intrcnt[SERIAL0_INTR]++; 402 } 403 404 if ((intr & KMIN_INTR_SCC_1) && 405 tc_slot_info[KMIN_SCC1_SLOT].intr) { 406 (*(tc_slot_info[KMIN_SCC1_SLOT].intr)) 407 (tc_slot_info[KMIN_SCC1_SLOT].sc); 408 intrcnt[SERIAL1_INTR]++; 409 } 410 411 if ((intr & IOASIC_INTR_LANCE) && 412 tc_slot_info[KMIN_LANCE_SLOT].intr) { 413 (*(tc_slot_info[KMIN_LANCE_SLOT].intr)) 414 (tc_slot_info[KMIN_LANCE_SLOT].sc); 415 intrcnt[LANCE_INTR]++; 416 } 417 418 if ((intr & IOASIC_INTR_SCSI) && 419 tc_slot_info[KMIN_SCSI_SLOT].intr) { 420 (*(tc_slot_info[KMIN_SCSI_SLOT].intr)) 421 (tc_slot_info[KMIN_SCSI_SLOT].sc); 422 intrcnt[SCSI_INTR]++; 423 } 424 425 if (user_warned && ((intr & KMIN_INTR_PSWARN) == 0)) { 426 printf("%s\n", "Power supply ok now."); 427 user_warned = 0; 428 } 429 if ((intr & KMIN_INTR_PSWARN) && (user_warned < 3)) { 430 user_warned++; 431 printf("%s\n", "Power supply overheating"); 432 } 433 } 434 if ((mask & MIPS_INT_MASK_0) && tc_slot_info[0].intr) { 435 (*tc_slot_info[0].intr)(tc_slot_info[0].sc); 436 intrcnt[SLOT0_INTR]++; 437 } 438 439 if ((mask & MIPS_INT_MASK_1) && tc_slot_info[1].intr) { 440 (*tc_slot_info[1].intr)(tc_slot_info[1].sc); 441 intrcnt[SLOT1_INTR]++; 442 } 443 if ((mask & MIPS_INT_MASK_2) && tc_slot_info[2].intr) { 444 (*tc_slot_info[2].intr)(tc_slot_info[2].sc); 445 intrcnt[SLOT2_INTR]++; 446 } 447 448#if 0 /*XXX*/ 449 if (mask & (MIPS_INT_MASK_2|MIPS_INT_MASK_1|MIPS_INT_MASK_0)) 450 printf("kmin: slot intr, mask 0x%x\n", 451 mask & 452 (MIPS_INT_MASK_2|MIPS_INT_MASK_1|MIPS_INT_MASK_0)); 453#endif 454 455 return ((statusReg & ~causeReg & MIPS_HARD_INT_MASK) | 456 MIPS_SR_INT_ENA_CUR); 457} 458 459 460 461/* 462 ************************************************************************ 463 * Extra functions 464 ************************************************************************ 465 */ 466 467 468 469 470/* 471 * Count instructions between 4ms mcclock interrupt requests, 472 * using the ioasic clock-interrupt-pending bit to determine 473 * when clock ticks occur. 474 * Set up iosiac to allow only clock interrupts, then 475 * call 476 */ 477void 478dec_3min_mcclock_cpuspeed(mcclock_addr, clockmask) 479 volatile struct chiptime *mcclock_addr; 480 int clockmask; 481{ 482 register volatile u_int * ioasic_intrmaskp = 483 (volatile u_int *)MIPS_PHYS_TO_KSEG1(KMIN_REG_IMSK); 484 485 register int saved_imask = *ioasic_intrmaskp; 486 487 /* Allow only clock interrupts through ioasic. */ 488 *ioasic_intrmaskp = KMIN_INTR_CLOCK; 489 wbflush(); 490 491 mc_cpuspeed(mcclock_addr, clockmask); 492 493 *ioasic_intrmaskp = saved_imask; 494 wbflush(); 495} 496 497