booke_cache.c revision 1.2.4.2
1 1.2.4.2 rmind /*- 2 1.2.4.2 rmind * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 3 1.2.4.2 rmind * All rights reserved. 4 1.2.4.2 rmind * 5 1.2.4.2 rmind * This code is derived from software contributed to The NetBSD Foundation 6 1.2.4.2 rmind * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 7 1.2.4.2 rmind * Agency and which was developed by Matt Thomas of 3am Software Foundry. 8 1.2.4.2 rmind * 9 1.2.4.2 rmind * This material is based upon work supported by the Defense Advanced Research 10 1.2.4.2 rmind * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 11 1.2.4.2 rmind * Contract No. N66001-09-C-2073. 12 1.2.4.2 rmind * Approved for Public Release, Distribution Unlimited 13 1.2.4.2 rmind * 14 1.2.4.2 rmind * Redistribution and use in source and binary forms, with or without 15 1.2.4.2 rmind * modification, are permitted provided that the following conditions 16 1.2.4.2 rmind * are met: 17 1.2.4.2 rmind * 1. Redistributions of source code must retain the above copyright 18 1.2.4.2 rmind * notice, this list of conditions and the following disclaimer. 19 1.2.4.2 rmind * 2. Redistributions in binary form must reproduce the above copyright 20 1.2.4.2 rmind * notice, this list of conditions and the following disclaimer in the 21 1.2.4.2 rmind * documentation and/or other materials provided with the distribution. 22 1.2.4.2 rmind * 23 1.2.4.2 rmind * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 1.2.4.2 rmind * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 1.2.4.2 rmind * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 1.2.4.2 rmind * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 1.2.4.2 rmind * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 1.2.4.2 rmind * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 1.2.4.2 rmind * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 1.2.4.2 rmind * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 1.2.4.2 rmind * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 1.2.4.2 rmind * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 1.2.4.2 rmind * POSSIBILITY OF SUCH DAMAGE. 34 1.2.4.2 rmind */ 35 1.2.4.2 rmind /* 36 1.2.4.2 rmind * 37 1.2.4.2 rmind */ 38 1.2.4.2 rmind #include <sys/cdefs.h> 39 1.2.4.2 rmind 40 1.2.4.2 rmind __KERNEL_RCSID(0, "$NetBSD: booke_cache.c,v 1.2.4.2 2011/03/05 20:51:33 rmind Exp $"); 41 1.2.4.2 rmind 42 1.2.4.2 rmind #include <sys/param.h> 43 1.2.4.2 rmind #include <sys/cpu.h> 44 1.2.4.2 rmind 45 1.2.4.2 rmind #include <uvm/uvm_extern.h> 46 1.2.4.2 rmind 47 1.2.4.2 rmind static void inline 48 1.2.4.2 rmind dcbf(vaddr_t va, vsize_t off) 49 1.2.4.2 rmind { 50 1.2.4.2 rmind __asm volatile("dcbf\t%0,%1" : : "b" (va), "r" (off)); 51 1.2.4.2 rmind } 52 1.2.4.2 rmind 53 1.2.4.2 rmind static void inline 54 1.2.4.2 rmind dcbst(vaddr_t va, vsize_t off) 55 1.2.4.2 rmind { 56 1.2.4.2 rmind __asm volatile("dcbst\t%0,%1" : : "b" (va), "r" (off)); 57 1.2.4.2 rmind } 58 1.2.4.2 rmind 59 1.2.4.2 rmind static void inline 60 1.2.4.2 rmind dcbi(vaddr_t va, vsize_t off) 61 1.2.4.2 rmind { 62 1.2.4.2 rmind __asm volatile("dcbi\t%0,%1" : : "b" (va), "r" (off)); 63 1.2.4.2 rmind } 64 1.2.4.2 rmind 65 1.2.4.2 rmind static void inline 66 1.2.4.2 rmind dcbz(vaddr_t va, vsize_t off) 67 1.2.4.2 rmind { 68 1.2.4.2 rmind __asm volatile("dcbz\t%0,%1" : : "b" (va), "r" (off)); 69 1.2.4.2 rmind } 70 1.2.4.2 rmind 71 1.2.4.2 rmind static void inline 72 1.2.4.2 rmind dcba(vaddr_t va, vsize_t off) 73 1.2.4.2 rmind { 74 1.2.4.2 rmind __asm volatile("dcba\t%0,%1" : : "b" (va), "r" (off)); 75 1.2.4.2 rmind } 76 1.2.4.2 rmind 77 1.2.4.2 rmind static void inline 78 1.2.4.2 rmind icbi(vaddr_t va, vsize_t off) 79 1.2.4.2 rmind { 80 1.2.4.2 rmind __asm volatile("icbi\t%0,%1" : : "b" (va), "r" (off)); 81 1.2.4.2 rmind } 82 1.2.4.2 rmind 83 1.2.4.2 rmind static inline void 84 1.2.4.2 rmind cache_op(vaddr_t va, vsize_t len, vsize_t line_size, 85 1.2.4.2 rmind void (*op)(vaddr_t, vsize_t)) 86 1.2.4.2 rmind { 87 1.2.4.2 rmind KASSERT(line_size > 0); 88 1.2.4.2 rmind 89 1.2.4.2 rmind if (len == 0) 90 1.2.4.2 rmind return; 91 1.2.4.2 rmind 92 1.2.4.2 rmind /* Make sure we flush all cache lines */ 93 1.2.4.2 rmind len += va & (line_size - 1); 94 1.2.4.2 rmind va &= -line_size; 95 1.2.4.2 rmind 96 1.2.4.2 rmind for (vsize_t i = 0; i < len; i += line_size) 97 1.2.4.2 rmind (*op)(va, i); 98 1.2.4.2 rmind __asm volatile("mbar 0"); 99 1.2.4.2 rmind } 100 1.2.4.2 rmind 101 1.2.4.2 rmind void 102 1.2.4.2 rmind dcache_wb_page(vaddr_t va) 103 1.2.4.2 rmind { 104 1.2.4.2 rmind cache_op(va, PAGE_SIZE, curcpu()->ci_ci.dcache_line_size, dcbst); 105 1.2.4.2 rmind } 106 1.2.4.2 rmind 107 1.2.4.2 rmind void 108 1.2.4.2 rmind dcache_wbinv_page(vaddr_t va) 109 1.2.4.2 rmind { 110 1.2.4.2 rmind cache_op(va, PAGE_SIZE, curcpu()->ci_ci.dcache_line_size, dcbf); 111 1.2.4.2 rmind } 112 1.2.4.2 rmind 113 1.2.4.2 rmind void 114 1.2.4.2 rmind dcache_inv_page(vaddr_t va) 115 1.2.4.2 rmind { 116 1.2.4.2 rmind cache_op(va, PAGE_SIZE, curcpu()->ci_ci.dcache_line_size, dcbi); 117 1.2.4.2 rmind } 118 1.2.4.2 rmind 119 1.2.4.2 rmind void 120 1.2.4.2 rmind dcache_zero_page(vaddr_t va) 121 1.2.4.2 rmind { 122 1.2.4.2 rmind cache_op(va, PAGE_SIZE, curcpu()->ci_ci.dcache_line_size, dcbz); 123 1.2.4.2 rmind } 124 1.2.4.2 rmind 125 1.2.4.2 rmind void 126 1.2.4.2 rmind icache_inv_page(vaddr_t va) 127 1.2.4.2 rmind { 128 1.2.4.2 rmind __asm("msync"); 129 1.2.4.2 rmind cache_op(va, PAGE_SIZE, curcpu()->ci_ci.icache_line_size, icbi); 130 1.2.4.2 rmind __asm("msync"); 131 1.2.4.2 rmind /* synchronizing instruction will be the rfi to user mode */ 132 1.2.4.2 rmind } 133 1.2.4.2 rmind 134 1.2.4.2 rmind void 135 1.2.4.2 rmind dcache_wb(vaddr_t va, vsize_t len) 136 1.2.4.2 rmind { 137 1.2.4.2 rmind cache_op(va, len, curcpu()->ci_ci.dcache_line_size, dcbst); 138 1.2.4.2 rmind } 139 1.2.4.2 rmind 140 1.2.4.2 rmind void 141 1.2.4.2 rmind dcache_wbinv(vaddr_t va, vsize_t len) 142 1.2.4.2 rmind { 143 1.2.4.2 rmind cache_op(va, len, curcpu()->ci_ci.dcache_line_size, dcbf); 144 1.2.4.2 rmind } 145 1.2.4.2 rmind 146 1.2.4.2 rmind void 147 1.2.4.2 rmind dcache_inv(vaddr_t va, vsize_t len) 148 1.2.4.2 rmind { 149 1.2.4.2 rmind cache_op(va, len, curcpu()->ci_ci.dcache_line_size, dcbi); 150 1.2.4.2 rmind } 151 1.2.4.2 rmind 152 1.2.4.2 rmind void 153 1.2.4.2 rmind icache_inv(vaddr_t va, vsize_t len) 154 1.2.4.2 rmind { 155 1.2.4.2 rmind __asm volatile("msync"); 156 1.2.4.2 rmind cache_op(va, len, curcpu()->ci_ci.icache_line_size, icbi); 157 1.2.4.2 rmind __asm volatile("msync"); 158 1.2.4.2 rmind } 159
Indexes created Sun Oct 12 20:09:57 GMT 2025