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booke_cache.c revision 1.1.2.1 
      1 /*	$NetBSD: booke_cache.c,v 1.1.2.1 2011/01/07 01:26:19 matt Exp $	*/
      2 /*-
      3  * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
      4  * All rights reserved.
      5  *
      6  * This code is derived from software contributed to The NetBSD Foundation
      7  * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects
      8  * Agency and which was developed by Matt Thomas of 3am Software Foundry.
      9  *
     10  * This material is based upon work supported by the Defense Advanced Research
     11  * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under
     12  * Contract No. N66001-09-C-2073.
     13  * Approved for Public Release, Distribution Unlimited
     14  *
     15  * Redistribution and use in source and binary forms, with or without
     16  * modification, are permitted provided that the following conditions
     17  * are met:
     18  * 1. Redistributions of source code must retain the above copyright
     19  *    notice, this list of conditions and the following disclaimer.
     20  * 2. Redistributions in binary form must reproduce the above copyright
     21  *    notice, this list of conditions and the following disclaimer in the
     22  *    documentation and/or other materials provided with the distribution.
     23  *
     24  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     25  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     26  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     27  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     28  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     29  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     30  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     31  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     32  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     33  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     34  * POSSIBILITY OF SUCH DAMAGE.
     35  */
     36 /*
     37  *
     38  */
     39 #include <sys/cdefs.h>
     40 
     41 __KERNEL_RCSID(0, "$NetBSD: booke_cache.c,v 1.1.2.1 2011/01/07 01:26:19 matt Exp $");
     42 
     43 #include <sys/param.h>
     44 #include <sys/cpu.h>
     45 
     46 #include <uvm/uvm_extern.h>
     47 
     48 static void inline
     49 dcbf(vaddr_t va, vsize_t off)
     50 {
     51 	__asm volatile("dcbf\t%0,%1" : : "b" (va), "r" (off));
     52 }
     53 
     54 static void inline
     55 dcbst(vaddr_t va, vsize_t off)
     56 {
     57 	__asm volatile("dcbst\t%0,%1" : : "b" (va), "r" (off));
     58 }
     59 
     60 static void inline
     61 dcbi(vaddr_t va, vsize_t off)
     62 {
     63 	__asm volatile("dcbi\t%0,%1" : : "b" (va), "r" (off));
     64 }
     65 
     66 static void inline
     67 dcbz(vaddr_t va, vsize_t off)
     68 {
     69 	__asm volatile("dcbz\t%0,%1" : : "b" (va), "r" (off));
     70 }
     71 
     72 static void inline
     73 dcba(vaddr_t va, vsize_t off)
     74 {
     75 	__asm volatile("dcba\t%0,%1" : : "b" (va), "r" (off));
     76 }
     77 
     78 static void inline
     79 icbi(vaddr_t va, vsize_t off)
     80 {
     81 	__asm volatile("icbi\t%0,%1" : : "b" (va), "r" (off));
     82 }
     83 
     84 static inline void
     85 cache_op(vaddr_t va, vsize_t len, vsize_t line_size,
     86 	void (*op)(vaddr_t, vsize_t))
     87 {
     88 	KASSERT(line_size > 0);
     89 
     90 	if (len == 0)
     91 		return;
     92 
     93 	/* Make sure we flush all cache lines */
     94 	len += va & (line_size - 1);
     95 	va &= ~(line_size - 1);
     96 
     97 	for (vsize_t i = 0; i < len; i += line_size)
     98 		(*op)(va, i);
     99 	__asm volatile("mbar 0");
    100 }
    101 
    102 void
    103 dcache_wb_page(vaddr_t va)
    104 {
    105 	cache_op(va, PAGE_SIZE, curcpu()->ci_ci.dcache_line_size, dcbst);
    106 }
    107 
    108 void
    109 dcache_wbinv_page(vaddr_t va)
    110 {
    111 	cache_op(va, PAGE_SIZE, curcpu()->ci_ci.dcache_line_size, dcbf);
    112 }
    113 
    114 void
    115 dcache_inv_page(vaddr_t va)
    116 {
    117 	cache_op(va, PAGE_SIZE, curcpu()->ci_ci.dcache_line_size, dcbi);
    118 }
    119 
    120 void
    121 dcache_zero_page(vaddr_t va)
    122 {
    123 	cache_op(va, PAGE_SIZE, curcpu()->ci_ci.dcache_line_size, dcbz);
    124 }
    125 
    126 void
    127 icache_inv_page(vaddr_t va)
    128 {
    129 	__asm("msync");
    130 	cache_op(va, PAGE_SIZE, curcpu()->ci_ci.icache_line_size, icbi);
    131 	__asm("msync");
    132 	/* synchronizing instruction will be the rfi to user mode */
    133 }
    134 
    135 void
    136 dcache_wb(vaddr_t va, vsize_t len)
    137 {
    138 	cache_op(va, len, curcpu()->ci_ci.dcache_line_size, dcbst);
    139 }
    140 
    141 void
    142 dcache_wbinv(vaddr_t va, vsize_t len)
    143 {
    144 	cache_op(va, len, curcpu()->ci_ci.dcache_line_size, dcbf);
    145 }
    146 
    147 void
    148 dcache_inv(vaddr_t va, vsize_t len)
    149 {
    150 	cache_op(va, len, curcpu()->ci_ci.dcache_line_size, dcbi);
    151 }
    152 
    153 void
    154 icache_inv(vaddr_t va, vsize_t len)
    155 {
    156 	__asm volatile("msync");
    157 	cache_op(va, len, curcpu()->ci_ci.icache_line_size, icbi);
    158 	__asm volatile("msync");
    159 }
    160